From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752224AbaH2WSq (ORCPT ); Fri, 29 Aug 2014 18:18:46 -0400 Received: from mail-ig0-f201.google.com ([209.85.213.201]:60350 "EHLO mail-ig0-f201.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751310AbaH2WOp (ORCPT ); Fri, 29 Aug 2014 18:14:45 -0400 From: Andrew Bresticker To: Ralf Baechle , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala Cc: Andrew Bresticker , Jeffrey Deans , Markos Chandras , Paul Burton , Thomas Gleixner , Jason Cooper , linux-mips@linux-mips.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 04/12] MIPS: GIC: Move MIPS_GIC_IRQ_BASE into platform irq.h Date: Fri, 29 Aug 2014 15:14:31 -0700 Message-Id: <1409350479-19108-5-git-send-email-abrestic@chromium.org> X-Mailer: git-send-email 2.1.0.rc2.206.gedb03e5 In-Reply-To: <1409350479-19108-1-git-send-email-abrestic@chromium.org> References: <1409350479-19108-1-git-send-email-abrestic@chromium.org> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Define a generic MIPS_GIC_IRQ_BASE which is suitable for Malta and the upcoming Danube board in . Since Sead-3 is different and uses a MIPS_GIC_IRQ_BASE equal to the CPU IRQ base (0), define its MIPS_GIC_IRQ_BASE in . Signed-off-by: Andrew Bresticker --- arch/mips/include/asm/mach-generic/irq.h | 6 ++++++ arch/mips/include/asm/mach-sead3/irq.h | 1 + arch/mips/include/asm/mips-boards/maltaint.h | 2 -- arch/mips/include/asm/mips-boards/sead3int.h | 2 -- 4 files changed, 7 insertions(+), 4 deletions(-) diff --git a/arch/mips/include/asm/mach-generic/irq.h b/arch/mips/include/asm/mach-generic/irq.h index 139cd20..c0fc62b 100644 --- a/arch/mips/include/asm/mach-generic/irq.h +++ b/arch/mips/include/asm/mach-generic/irq.h @@ -36,4 +36,10 @@ #endif /* CONFIG_IRQ_CPU */ +#ifdef CONFIG_IRQ_GIC +#ifndef MIPS_GIC_IRQ_BASE +#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8) +#endif +#endif /* CONFIG_IRQ_GIC */ + #endif /* __ASM_MACH_GENERIC_IRQ_H */ diff --git a/arch/mips/include/asm/mach-sead3/irq.h b/arch/mips/include/asm/mach-sead3/irq.h index d8106f7..52c75d5 100644 --- a/arch/mips/include/asm/mach-sead3/irq.h +++ b/arch/mips/include/asm/mach-sead3/irq.h @@ -1,6 +1,7 @@ #ifndef __ASM_MACH_MIPS_IRQ_H #define __ASM_MACH_MIPS_IRQ_H +#define MIPS_GIC_IRQ_BASE 0 #define GIC_NUM_INTRS (24 + NR_CPUS * 2) #define NR_IRQS 256 diff --git a/arch/mips/include/asm/mips-boards/maltaint.h b/arch/mips/include/asm/mips-boards/maltaint.h index e330732..9d23343 100644 --- a/arch/mips/include/asm/mips-boards/maltaint.h +++ b/arch/mips/include/asm/mips-boards/maltaint.h @@ -10,8 +10,6 @@ #ifndef _MIPS_MALTAINT_H #define _MIPS_MALTAINT_H -#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8) - /* * Interrupts 0..15 are used for Malta ISA compatible interrupts */ diff --git a/arch/mips/include/asm/mips-boards/sead3int.h b/arch/mips/include/asm/mips-boards/sead3int.h index 6b17aaf..11ebec9 100644 --- a/arch/mips/include/asm/mips-boards/sead3int.h +++ b/arch/mips/include/asm/mips-boards/sead3int.h @@ -14,6 +14,4 @@ #define GIC_BASE_ADDR 0x1b1c0000 #define GIC_ADDRSPACE_SZ (128 * 1024) -#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 0) - #endif /* !(_MIPS_SEAD3INT_H) */ -- 2.1.0.rc2.206.gedb03e5