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From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, rth@twiddle.net
Subject: [Qemu-devel] [PATCH v7 14/15] target-tricore: Add instructions of SLR, SSRO and SRO opcode format
Date: Mon,  1 Sep 2014 12:59:59 +0100	[thread overview]
Message-ID: <1409572800-4116-15-git-send-email-kbastian@mail.uni-paderborn.de> (raw)
In-Reply-To: <1409572800-4116-1-git-send-email-kbastian@mail.uni-paderborn.de>

Add instructions of SLR, SSRO and SRO opcode format.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>

Reviewed-by: Richard Henderson <rth@twiddle.net>
---
 target-tricore/translate.c | 121 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 121 insertions(+)

diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 5298712..e24479d 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -716,6 +716,84 @@ static void decode_sc_opc(DisasContext *ctx, int op1)
         break;
     }
 }
+
+static void decode_slr_opc(DisasContext *ctx, int op1)
+{
+    int r1, r2;
+
+    r1 = MASK_OP_SLR_D(ctx->opcode);
+    r2 = MASK_OP_SLR_S2(ctx->opcode);
+
+    switch (op1) {
+/* SLR-format */
+    case OPC1_16_SLR_LD_A:
+        tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
+        break;
+    case OPC1_16_SLR_LD_A_POSTINC:
+        tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
+        tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
+        break;
+    case OPC1_16_SLR_LD_BU:
+        tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
+        break;
+    case OPC1_16_SLR_LD_BU_POSTINC:
+        tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
+        tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1);
+        break;
+    case OPC1_16_SLR_LD_H:
+        tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
+        break;
+    case OPC1_16_SLR_LD_H_POSTINC:
+        tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
+        tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2);
+        break;
+    case OPC1_16_SLR_LD_W:
+        tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
+        break;
+    case OPC1_16_SLR_LD_W_POSTINC:
+        tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
+        tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
+        break;
+    }
+}
+
+static void decode_sro_opc(DisasContext *ctx, int op1)
+{
+    int r2;
+    int32_t address;
+
+    r2 = MASK_OP_SRO_S2(ctx->opcode);
+    address = MASK_OP_SRO_OFF4(ctx->opcode);
+
+/* SRO-format */
+    switch (op1) {
+    case OPC1_16_SRO_LD_A:
+        gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4, MO_LESL);
+        break;
+    case OPC1_16_SRO_LD_BU:
+        gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB);
+        break;
+    case OPC1_16_SRO_LD_H:
+        gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_LESW);
+        break;
+    case OPC1_16_SRO_LD_W:
+        gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL);
+        break;
+    case OPC1_16_SRO_ST_A:
+        gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4, MO_LESL);
+        break;
+    case OPC1_16_SRO_ST_B:
+        gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB);
+        break;
+    case OPC1_16_SRO_ST_H:
+        gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 2, MO_LESW);
+        break;
+    case OPC1_16_SRO_ST_W:
+        gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL);
+        break;
+    }
+}
+
 static void decode_16Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
 {
     int op1;
@@ -864,6 +942,49 @@ static void decode_16Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
     case OPC1_16_SC_SUB_A:
         decode_sc_opc(ctx, op1);
         break;
+/* SLR-format */
+    case OPC1_16_SLR_LD_A:
+    case OPC1_16_SLR_LD_A_POSTINC:
+    case OPC1_16_SLR_LD_BU:
+    case OPC1_16_SLR_LD_BU_POSTINC:
+    case OPC1_16_SLR_LD_H:
+    case OPC1_16_SLR_LD_H_POSTINC:
+    case OPC1_16_SLR_LD_W:
+    case OPC1_16_SLR_LD_W_POSTINC:
+        decode_slr_opc(ctx, op1);
+        break;
+/* SRO-format */
+    case OPC1_16_SRO_LD_A:
+    case OPC1_16_SRO_LD_BU:
+    case OPC1_16_SRO_LD_H:
+    case OPC1_16_SRO_LD_W:
+    case OPC1_16_SRO_ST_A:
+    case OPC1_16_SRO_ST_B:
+    case OPC1_16_SRO_ST_H:
+    case OPC1_16_SRO_ST_W:
+        decode_sro_opc(ctx, op1);
+        break;
+/* SSRO-format */
+    case OPC1_16_SSRO_ST_A:
+        r1 = MASK_OP_SSRO_S1(ctx->opcode);
+        const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
+        gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
+        break;
+    case OPC1_16_SSRO_ST_B:
+        r1 = MASK_OP_SSRO_S1(ctx->opcode);
+        const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
+        gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB);
+        break;
+    case OPC1_16_SSRO_ST_H:
+        r1 = MASK_OP_SSRO_S1(ctx->opcode);
+        const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
+        gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW);
+        break;
+    case OPC1_16_SSRO_ST_W:
+        r1 = MASK_OP_SSRO_S1(ctx->opcode);
+        const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
+        gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
+        break;
     }
 }
 
-- 
2.1.0

  parent reply	other threads:[~2014-09-01 10:56 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-09-01 11:59 [Qemu-devel] [PATCH v7 00/15] TriCore architecture guest implementation Bastian Koppelmann
2014-09-01 11:59 ` [Qemu-devel] [PATCH v7 01/15] target-tricore: Add target stubs and qom-cpu Bastian Koppelmann
2014-09-01 11:59 ` [Qemu-devel] [PATCH v7 02/15] target-tricore: Add board for systemmode Bastian Koppelmann
2014-09-01 12:48   ` Peter Maydell
2014-09-01 14:01     ` Bastian Koppelmann
2014-09-01 11:59 ` [Qemu-devel] [PATCH v7 03/15] target-tricore: Add softmmu support Bastian Koppelmann
2014-09-15 16:55   ` Peter Maydell
2014-09-01 11:59 ` [Qemu-devel] [PATCH v7 04/15] target-tricore: Add initialization for translation and activate target Bastian Koppelmann
2014-09-01 11:59 ` [Qemu-devel] [PATCH v7 05/15] target-tricore: Add masks and opcodes for decoding Bastian Koppelmann
2014-09-01 11:59 ` [Qemu-devel] [PATCH v7 06/15] target-tricore: Add instructions of SRC opcode format Bastian Koppelmann
2014-09-01 11:59 ` [Qemu-devel] [PATCH v7 07/15] target-tricore: Add instructions of SRR " Bastian Koppelmann
2014-09-01 11:59 ` [Qemu-devel] [PATCH v7 08/15] target-tricore: Add instructions of SSR " Bastian Koppelmann
2014-09-01 11:59 ` [Qemu-devel] [PATCH v7 09/15] target-tricore: Add instructions of SRRS and SLRO " Bastian Koppelmann
2014-09-01 11:59 ` [Qemu-devel] [PATCH v7 10/15] target-tricore: Add instructions of SB " Bastian Koppelmann
2014-09-01 11:59 ` [Qemu-devel] [PATCH v7 11/15] target-tricore: Add instructions of SBC and SBRN " Bastian Koppelmann
2014-09-01 11:59 ` [Qemu-devel] [PATCH v7 12/15] target-tricore: Add instructions of SBR " Bastian Koppelmann
2014-09-01 11:59 ` [Qemu-devel] [PATCH v7 13/15] target-tricore: Add instructions of SC " Bastian Koppelmann
2014-09-01 11:59 ` Bastian Koppelmann [this message]
2014-09-01 12:00 ` [Qemu-devel] [PATCH v7 15/15] target-tricore: Add instructions of SR " Bastian Koppelmann
2014-09-01 15:10 ` [Qemu-devel] [PATCH v7 00/15] TriCore architecture guest implementation Peter Maydell

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