From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33990) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XOPHS-0003NS-Vx for qemu-devel@nongnu.org; Mon, 01 Sep 2014 06:56:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XOPHN-0008Vw-Rs for qemu-devel@nongnu.org; Mon, 01 Sep 2014 06:56:14 -0400 Received: from mail.uni-paderborn.de ([131.234.142.9]:10083) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XOPHN-0008Vi-MC for qemu-devel@nongnu.org; Mon, 01 Sep 2014 06:56:09 -0400 From: Bastian Koppelmann Date: Mon, 1 Sep 2014 12:59:53 +0100 Message-Id: <1409572800-4116-9-git-send-email-kbastian@mail.uni-paderborn.de> In-Reply-To: <1409572800-4116-1-git-send-email-kbastian@mail.uni-paderborn.de> References: <1409572800-4116-1-git-send-email-kbastian@mail.uni-paderborn.de> Subject: [Qemu-devel] [PATCH v7 08/15] target-tricore: Add instructions of SSR opcode format List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, rth@twiddle.net Add instructions of SSR opcode format. Signed-off-by: Bastian Koppelmann Reviewed-by: Richard Henderson --- target-tricore/translate.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/target-tricore/translate.c b/target-tricore/translate.c index 717a42d..d8e23fc 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -471,6 +471,45 @@ static void decode_srr_opc(DisasContext *ctx, int op1) } } +static void decode_ssr_opc(DisasContext *ctx, int op1) +{ + int r1, r2; + + r1 = MASK_OP_SSR_S1(ctx->opcode); + r2 = MASK_OP_SSR_S2(ctx->opcode); + + switch (op1) { + case OPC1_16_SSR_ST_A: + tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL); + break; + case OPC1_16_SSR_ST_A_POSTINC: + tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL); + tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4); + break; + case OPC1_16_SSR_ST_B: + tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB); + break; + case OPC1_16_SSR_ST_B_POSTINC: + tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB); + tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1); + break; + case OPC1_16_SSR_ST_H: + tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW); + break; + case OPC1_16_SSR_ST_H_POSTINC: + tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW); + tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2); + break; + case OPC1_16_SSR_ST_W: + tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL); + break; + case OPC1_16_SSR_ST_W_POSTINC: + tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL); + tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4); + break; + } +} + static void decode_16Bit_opc(CPUTriCoreState *env, DisasContext *ctx) { int op1; @@ -518,6 +557,17 @@ static void decode_16Bit_opc(CPUTriCoreState *env, DisasContext *ctx) case OPC1_16_SRR_XOR: decode_srr_opc(ctx, op1); break; +/* SSR-format */ + case OPC1_16_SSR_ST_A: + case OPC1_16_SSR_ST_A_POSTINC: + case OPC1_16_SSR_ST_B: + case OPC1_16_SSR_ST_B_POSTINC: + case OPC1_16_SSR_ST_H: + case OPC1_16_SSR_ST_H_POSTINC: + case OPC1_16_SSR_ST_W: + case OPC1_16_SSR_ST_W_POSTINC: + decode_ssr_opc(ctx, op1); + break; } } -- 2.1.0