From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andrii Tseglytskyi Subject: [PATCH v03 10/10] arm: omap: introduce print pagetable function for GPU remoteproc Date: Tue, 2 Sep 2014 18:46:10 +0300 Message-ID: <1409672770-23164-11-git-send-email-andrii.tseglytskyi@globallogic.com> References: <1409672770-23164-1-git-send-email-andrii.tseglytskyi@globallogic.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1409672770-23164-1-git-send-email-andrii.tseglytskyi@globallogic.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Ian Campbell , Stefano Stabellini , Julien Grall , xen-devel@lists.xen.org List-Id: xen-devel@lists.xenproject.org This patch adds a possibility to dump all pagetables of GPU remoteproc. The only reason to have this patch - is a low level debug. Signed-off-by: Andrii Tseglytskyi --- xen/arch/arm/remoteproc/omap_iommu.c | 59 ++++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/xen/arch/arm/remoteproc/omap_iommu.c b/xen/arch/arm/remoteproc/omap_iommu.c index 70867e9..cf43250 100644 --- a/xen/arch/arm/remoteproc/omap_iommu.c +++ b/xen/arch/arm/remoteproc/omap_iommu.c @@ -76,6 +76,7 @@ static paddr_t mmu_ipu_translate_pagetable(struct mmu_info *mmu, struct mmu_page static paddr_t mmu_gpu_translate_pagetable(struct mmu_info *mmu, struct mmu_pagetable *pgt); static void mmu_ipu_print_pagetables(struct mmu_info *mmu); +static void mmu_gpu_print_pagetables(struct mmu_info *mmu); static u32 ipu_trap_offsets[] = { MMU_IPU_TTB_OFFSET, @@ -128,6 +129,7 @@ struct mmu_info omap_gpu_mmu = { .num_traps = ARRAY_SIZE(sgx_trap_offsets), .copy_pagetable_pfunc = mmu_omap_copy_pagetable, .translate_pfunc = mmu_gpu_translate_pagetable, + .print_pagetable_pfunc = mmu_gpu_print_pagetables, }; static bool translate_supersections_to_pages = true; @@ -425,6 +427,63 @@ static paddr_t mmu_ipu_translate_pagetable(struct mmu_info *mmu, struct mmu_page return __pa(hyp_pgt); } +static void mmu_gpu_print_one_pagetable(struct mmu_info *mmu, struct mmu_pagetable *pgt, u32 index) +{ + u32 *pagetable; + u32 i, page_counter = 0; + + ASSERT(pgt); + ASSERT(pgt->hyp_pagetable); + ASSERT(pgt->paddr); + ASSERT(pgt->maddr); + + pagetable = pgt->hyp_pagetable; + + pr_mmu(mmu, "pgt[%u][0x%"PRIpaddr"][0x%"PRIpaddr"]", index, pgt->paddr, pgt->maddr); + /* 1-st level translation */ + for ( i = 0; i < MMU_PTRS_PER_PGD(mmu); i++ ) + { + paddr_t pgd = pagetable[i]; + paddr_t *pte_table = NULL; + u32 j; + + if ( !pgd ) + continue; + + pr_mmu(mmu, "pgt[%u][0x%"PRIpaddr"][0x%"PRIpaddr"] pgd[%u] 0x%"PRIpaddr" (max %lu)", + index, pgt->paddr, pgt->maddr, i, pgd, MMU_PTRS_PER_PGD(mmu)); + + pte_table = __va(pgd & MMU_SECTION_MASK(mmu->pg_data->pte_shift)); + if ( !pte_table ) + { + pr_mmu(mmu, "failed to map pagetable"); + return; + } + + for ( j = 0; j < MMU_PTRS_PER_PTE(mmu); j++ ) + { + if ( !pte_table[j] ) + continue; + + page_counter++; + pr_mmu(mmu, "pgt[%u][0x%"PRIpaddr"][0x%"PRIpaddr"] pgd[%u]\t pte_table[%u] 0x%"PRIpaddr" (max %lu)", + index, pgt->paddr, pgt->maddr, i, j, pte_table[j], MMU_PTRS_PER_PTE(mmu)); + } + } + ASSERT(page_counter == pgt->page_counter); +} + +static void mmu_gpu_print_pagetables(struct mmu_info *mmu) +{ + struct mmu_pagetable *pgt; + u32 i = 0; + + list_for_each_entry(pgt, &mmu->pagetables_list, link_node) + { + mmu_gpu_print_one_pagetable(mmu, pgt, i++); + } +} + static paddr_t mmu_gpu_translate_pagetable(struct mmu_info *mmu, struct mmu_pagetable *pgt) { /* GPU pagetable consists of set of 32 bit pointers */ -- 1.9.1