From mboxrd@z Thu Jan 1 00:00:00 1970 From: Kumar Gala Subject: [PATCH v4 3/3] ata: qcom: Add device tree bindings information Date: Mon, 8 Sep 2014 11:39:50 -0500 Message-ID: <1410194390-29007-3-git-send-email-galak@codeaurora.org> References: <1410194390-29007-1-git-send-email-galak@codeaurora.org> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1410194390-29007-1-git-send-email-galak@codeaurora.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Tejun Heo , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell Cc: devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-ide@vger.kernel.org, Kumar Gala , linux-arm-kernel@lists.infradead.org List-Id: linux-arm-msm@vger.kernel.org Add device tree binding for Qualcomm AHCI SATA controller and specifically the sata controller on the IPQ806x family of SoCs. Signed-off-by: Kumar Gala --- .../devicetree/bindings/ata/qcom-sata.txt | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/devicetree/bindings/ata/qcom-sata.txt diff --git a/Documentation/devicetree/bindings/ata/qcom-sata.txt b/Documentation/devicetree/bindings/ata/qcom-sata.txt new file mode 100644 index 0000000..5e74e41 --- /dev/null +++ b/Documentation/devicetree/bindings/ata/qcom-sata.txt @@ -0,0 +1,40 @@ +* Qualcomm AHCI SATA Controller + +SATA nodes are defined to describe on-chip Serial ATA controllers. +Each SATA controller should have its own node. + +Required properties: +- compatible : compatible list, contains "qcom,msm-ahci" +- interrupts : +- reg : +- phys : Must contain exactly one entry as specified + in phy-bindings.txt +- phy-names : Must be "sata-phy" + +Required properties for "qcom,ipq806x-ahci" compatible: +- clocks : Must contain an entry for each entry in clock-names. +- clock-names : Shall be: + "slave_iface" - Fabric port AHB clock for SATA + "iface" - AHB clock + "core" - core clock + "rxoob" - RX out-of-band clock + "pmalive" - Power Module Alive clock + +Example: + sata@29000000 { + compatible = "qcom,ipq806x-ahci", "qcom,msm-ahci"; + reg = <0x29000000 0x180>; + + interrupts = <0 209 0x0>; + + clocks = <&gcc SFAB_SATA_S_H_CLK>, + <&gcc SATA_H_CLK>, + <&gcc SATA_A_CLK>, + <&gcc SATA_RXOOB_CLK>, + <&gcc SATA_PMALIVE_CLK>; + clock-names = "slave_iface", "iface", "core", + "rxoob", "pmalive"; + + phys = <&sata_phy>; + phy-names = "sata-phy"; + }; -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754769AbaIHQku (ORCPT ); Mon, 8 Sep 2014 12:40:50 -0400 Received: from smtp.codeaurora.org ([198.145.11.231]:42255 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754500AbaIHQj5 (ORCPT ); Mon, 8 Sep 2014 12:39:57 -0400 From: Kumar Gala To: Tejun Heo , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell Cc: Kumar Gala , linux-ide@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 3/3] ata: qcom: Add device tree bindings information Date: Mon, 8 Sep 2014 11:39:50 -0500 Message-Id: <1410194390-29007-3-git-send-email-galak@codeaurora.org> X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1410194390-29007-1-git-send-email-galak@codeaurora.org> References: <1410194390-29007-1-git-send-email-galak@codeaurora.org> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add device tree binding for Qualcomm AHCI SATA controller and specifically the sata controller on the IPQ806x family of SoCs. Signed-off-by: Kumar Gala --- .../devicetree/bindings/ata/qcom-sata.txt | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/devicetree/bindings/ata/qcom-sata.txt diff --git a/Documentation/devicetree/bindings/ata/qcom-sata.txt b/Documentation/devicetree/bindings/ata/qcom-sata.txt new file mode 100644 index 0000000..5e74e41 --- /dev/null +++ b/Documentation/devicetree/bindings/ata/qcom-sata.txt @@ -0,0 +1,40 @@ +* Qualcomm AHCI SATA Controller + +SATA nodes are defined to describe on-chip Serial ATA controllers. +Each SATA controller should have its own node. + +Required properties: +- compatible : compatible list, contains "qcom,msm-ahci" +- interrupts : +- reg : +- phys : Must contain exactly one entry as specified + in phy-bindings.txt +- phy-names : Must be "sata-phy" + +Required properties for "qcom,ipq806x-ahci" compatible: +- clocks : Must contain an entry for each entry in clock-names. +- clock-names : Shall be: + "slave_iface" - Fabric port AHB clock for SATA + "iface" - AHB clock + "core" - core clock + "rxoob" - RX out-of-band clock + "pmalive" - Power Module Alive clock + +Example: + sata@29000000 { + compatible = "qcom,ipq806x-ahci", "qcom,msm-ahci"; + reg = <0x29000000 0x180>; + + interrupts = <0 209 0x0>; + + clocks = <&gcc SFAB_SATA_S_H_CLK>, + <&gcc SATA_H_CLK>, + <&gcc SATA_A_CLK>, + <&gcc SATA_RXOOB_CLK>, + <&gcc SATA_PMALIVE_CLK>; + clock-names = "slave_iface", "iface", "core", + "rxoob", "pmalive"; + + phys = <&sata_phy>; + phy-names = "sata-phy"; + }; -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation From mboxrd@z Thu Jan 1 00:00:00 1970 From: galak@codeaurora.org (Kumar Gala) Date: Mon, 8 Sep 2014 11:39:50 -0500 Subject: [PATCH v4 3/3] ata: qcom: Add device tree bindings information In-Reply-To: <1410194390-29007-1-git-send-email-galak@codeaurora.org> References: <1410194390-29007-1-git-send-email-galak@codeaurora.org> Message-ID: <1410194390-29007-3-git-send-email-galak@codeaurora.org> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Add device tree binding for Qualcomm AHCI SATA controller and specifically the sata controller on the IPQ806x family of SoCs. Signed-off-by: Kumar Gala --- .../devicetree/bindings/ata/qcom-sata.txt | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/devicetree/bindings/ata/qcom-sata.txt diff --git a/Documentation/devicetree/bindings/ata/qcom-sata.txt b/Documentation/devicetree/bindings/ata/qcom-sata.txt new file mode 100644 index 0000000..5e74e41 --- /dev/null +++ b/Documentation/devicetree/bindings/ata/qcom-sata.txt @@ -0,0 +1,40 @@ +* Qualcomm AHCI SATA Controller + +SATA nodes are defined to describe on-chip Serial ATA controllers. +Each SATA controller should have its own node. + +Required properties: +- compatible : compatible list, contains "qcom,msm-ahci" +- interrupts : +- reg : +- phys : Must contain exactly one entry as specified + in phy-bindings.txt +- phy-names : Must be "sata-phy" + +Required properties for "qcom,ipq806x-ahci" compatible: +- clocks : Must contain an entry for each entry in clock-names. +- clock-names : Shall be: + "slave_iface" - Fabric port AHB clock for SATA + "iface" - AHB clock + "core" - core clock + "rxoob" - RX out-of-band clock + "pmalive" - Power Module Alive clock + +Example: + sata at 29000000 { + compatible = "qcom,ipq806x-ahci", "qcom,msm-ahci"; + reg = <0x29000000 0x180>; + + interrupts = <0 209 0x0>; + + clocks = <&gcc SFAB_SATA_S_H_CLK>, + <&gcc SATA_H_CLK>, + <&gcc SATA_A_CLK>, + <&gcc SATA_RXOOB_CLK>, + <&gcc SATA_PMALIVE_CLK>; + clock-names = "slave_iface", "iface", "core", + "rxoob", "pmalive"; + + phys = <&sata_phy>; + phy-names = "sata-phy"; + }; -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation