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From: heiko@sntech.de (Heiko Stuebner)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 1/7] clk: rockchip: fix rk3066 pll status register location
Date: Sat, 13 Sep 2014 00:30:24 +0200	[thread overview]
Message-ID: <1410561030-19127-2-git-send-email-heiko@sntech.de> (raw)
In-Reply-To: <1410561030-19127-1-git-send-email-heiko@sntech.de>

The register providing the pll lock status is at a different address on the
rk3066. The error became apparent while working on cpufreq support for
the rockchip SoCs.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 drivers/clk/rockchip/clk-rk3188.c | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c
index 0147614..1c5e644 100644
--- a/drivers/clk/rockchip/clk-rk3188.c
+++ b/drivers/clk/rockchip/clk-rk3188.c
@@ -19,6 +19,7 @@
 #include <dt-bindings/clock/rk3188-cru-common.h>
 #include "clk.h"
 
+#define RK3066_GRF_SOC_STATUS	0x15c
 #define RK3188_GRF_SOC_STATUS	0xac
 
 enum rk3188_plls {
@@ -629,9 +630,6 @@ static void __init rk3188_common_clk_init(struct device_node *np)
 		pr_warn("%s: could not register clock usb480m: %ld\n",
 			__func__, PTR_ERR(clk));
 
-	rockchip_clk_register_plls(rk3188_pll_clks,
-				   ARRAY_SIZE(rk3188_pll_clks),
-				   RK3188_GRF_SOC_STATUS);
 	rockchip_clk_register_branches(common_clk_branches,
 				  ARRAY_SIZE(common_clk_branches));
 	rockchip_clk_protect_critical(rk3188_critical_clocks,
@@ -644,6 +642,9 @@ static void __init rk3188_common_clk_init(struct device_node *np)
 static void __init rk3066a_clk_init(struct device_node *np)
 {
 	rk3188_common_clk_init(np);
+	rockchip_clk_register_plls(rk3188_pll_clks,
+				   ARRAY_SIZE(rk3188_pll_clks),
+				   RK3066_GRF_SOC_STATUS);
 	rockchip_clk_register_branches(rk3066a_clk_branches,
 				  ARRAY_SIZE(rk3066a_clk_branches));
 }
@@ -652,6 +653,9 @@ CLK_OF_DECLARE(rk3066a_cru, "rockchip,rk3066a-cru", rk3066a_clk_init);
 static void __init rk3188a_clk_init(struct device_node *np)
 {
 	rk3188_common_clk_init(np);
+	rockchip_clk_register_plls(rk3188_pll_clks,
+				   ARRAY_SIZE(rk3188_pll_clks),
+				   RK3188_GRF_SOC_STATUS);
 	rockchip_clk_register_branches(rk3188_clk_branches,
 				  ARRAY_SIZE(rk3188_clk_branches));
 }
-- 
2.0.1

  reply	other threads:[~2014-09-12 22:30 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-09-12 22:30 [PATCH v2 0/7] ARM: Rockchip: add cpuclk handling - clock-tree part Heiko Stuebner
2014-09-12 22:30 ` Heiko Stuebner [this message]
2014-09-12 22:30 ` [PATCH v2 2/7] clk: rockchip: fix rk3288 pll status register location Heiko Stuebner
2014-09-12 23:46   ` Doug Anderson
2014-09-12 22:30 ` [PATCH v2 3/7] clk: rockchip: reparent aclk_cpu_pre to the gpll Heiko Stuebner
2014-09-12 22:30 ` [PATCH v2 4/7] clk: rockchip: make tightly bound armclk child-clocks read-only Heiko Stuebner
2014-09-12 23:52   ` Doug Anderson
2014-09-12 22:30 ` [PATCH v2 5/7] clk: rockchip: add new clock-type for the cpuclk Heiko Stuebner
2014-09-15 23:58   ` Doug Anderson
2014-09-16  0:49     ` Doug Anderson
2014-09-16  9:49       ` Karl Palsson
2014-09-16  1:00     ` Kever Yang
2014-09-16  4:37       ` Doug Anderson
2014-09-12 22:30 ` [PATCH v2 6/7] clk: rockchip: add binding id for ARMCLK Heiko Stuebner
2014-09-13  0:10   ` Doug Anderson
2014-09-12 22:30 ` [PATCH v2 7/7] clk: rockchip: switch to using the new cpuclk type for armclk Heiko Stuebner

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