From: heiko@sntech.de (Heiko Stuebner) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 2/8] clk: rockchip: fix rk3066 pll status register location Date: Thu, 18 Sep 2014 00:12:48 +0200 [thread overview] Message-ID: <1410991974-12235-3-git-send-email-heiko@sntech.de> (raw) In-Reply-To: <1410991974-12235-1-git-send-email-heiko@sntech.de> The register providing the pll lock status is at a different address on the rk3066. The error became apparent while working on cpufreq support for the rockchip SoCs. Signed-off-by: Heiko Stuebner <heiko@sntech.de> --- drivers/clk/rockchip/clk-rk3188.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c index 0147614..1c5e644 100644 --- a/drivers/clk/rockchip/clk-rk3188.c +++ b/drivers/clk/rockchip/clk-rk3188.c @@ -19,6 +19,7 @@ #include <dt-bindings/clock/rk3188-cru-common.h> #include "clk.h" +#define RK3066_GRF_SOC_STATUS 0x15c #define RK3188_GRF_SOC_STATUS 0xac enum rk3188_plls { @@ -629,9 +630,6 @@ static void __init rk3188_common_clk_init(struct device_node *np) pr_warn("%s: could not register clock usb480m: %ld\n", __func__, PTR_ERR(clk)); - rockchip_clk_register_plls(rk3188_pll_clks, - ARRAY_SIZE(rk3188_pll_clks), - RK3188_GRF_SOC_STATUS); rockchip_clk_register_branches(common_clk_branches, ARRAY_SIZE(common_clk_branches)); rockchip_clk_protect_critical(rk3188_critical_clocks, @@ -644,6 +642,9 @@ static void __init rk3188_common_clk_init(struct device_node *np) static void __init rk3066a_clk_init(struct device_node *np) { rk3188_common_clk_init(np); + rockchip_clk_register_plls(rk3188_pll_clks, + ARRAY_SIZE(rk3188_pll_clks), + RK3066_GRF_SOC_STATUS); rockchip_clk_register_branches(rk3066a_clk_branches, ARRAY_SIZE(rk3066a_clk_branches)); } @@ -652,6 +653,9 @@ CLK_OF_DECLARE(rk3066a_cru, "rockchip,rk3066a-cru", rk3066a_clk_init); static void __init rk3188a_clk_init(struct device_node *np) { rk3188_common_clk_init(np); + rockchip_clk_register_plls(rk3188_pll_clks, + ARRAY_SIZE(rk3188_pll_clks), + RK3188_GRF_SOC_STATUS); rockchip_clk_register_branches(rk3188_clk_branches, ARRAY_SIZE(rk3188_clk_branches)); } -- 2.0.1
next prev parent reply other threads:[~2014-09-17 22:12 UTC|newest] Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top 2014-09-17 22:12 [PATCH v3 0/8] ARM: Rockchip: add cpuclk handling - clock-tree part Heiko Stuebner 2014-09-17 22:12 ` [PATCH v3 1/8] clk: rockchip: change pll rate without a clk-notifier Heiko Stuebner 2014-09-17 22:46 ` Doug Anderson 2014-09-17 23:13 ` Heiko Stübner 2014-09-25 22:50 ` Mike Turquette 2014-09-17 22:12 ` Heiko Stuebner [this message] 2014-09-17 22:12 ` [PATCH v3 3/8] clk: rockchip: fix rk3288 pll status register location Heiko Stuebner 2014-09-17 22:12 ` [PATCH v3 4/8] clk: rockchip: reparent aclk_cpu_pre to the gpll Heiko Stuebner 2014-09-17 22:12 ` [PATCH v3 5/8] clk: rockchip: make tightly bound armclk child-clocks read-only Heiko Stuebner 2014-09-17 22:12 ` [PATCH v3 6/8] clk: rockchip: add new clock-type for the cpuclk Heiko Stuebner 2014-09-22 17:47 ` Doug Anderson 2014-09-22 19:21 ` Heiko Stübner 2014-09-22 19:33 ` Doug Anderson 2014-09-23 5:25 ` Thomas Abraham 2014-09-23 18:16 ` Doug Anderson 2014-09-17 22:12 ` [PATCH v3 7/8] clk: rockchip: add binding id for ARMCLK Heiko Stuebner 2014-09-22 17:08 ` Doug Anderson 2014-09-17 22:12 ` [PATCH v3 8/8] clk: rockchip: switch to using the new cpuclk type for armclk Heiko Stuebner 2014-09-22 17:51 ` Doug Anderson
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