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From: heiko@sntech.de (Heiko Stuebner)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 3/8] clk: rockchip: fix rk3288 pll status register location
Date: Thu, 18 Sep 2014 00:12:49 +0200	[thread overview]
Message-ID: <1410991974-12235-4-git-send-email-heiko@sntech.de> (raw)
In-Reply-To: <1410991974-12235-1-git-send-email-heiko@sntech.de>

From: Jianqun <jay.xu@rock-chips.com>

In RK3288, APLL lock status bit is in GRF_SOC_STATUS1,
but in RK3188, is GRFSOC_STATUS0.

Signed-off-by: Jianqun <jay.xu@rock-chips.com>

Also name the constant accordingly as GRF_SOC_STATUS1
to prevent confusion.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
---
 drivers/clk/rockchip/clk-rk3288.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
index aa4f4b7..b30e147 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -20,7 +20,7 @@
 #include "clk.h"
 
 #define RK3288_GRF_SOC_CON(x)	(0x244 + x * 4)
-#define RK3288_GRF_SOC_STATUS	0x280
+#define RK3288_GRF_SOC_STATUS1	0x284
 
 enum rk3288_plls {
 	apll, dpll, cpll, gpll, npll,
@@ -713,7 +713,7 @@ static void __init rk3288_clk_init(struct device_node *np)
 
 	rockchip_clk_register_plls(rk3288_pll_clks,
 				   ARRAY_SIZE(rk3288_pll_clks),
-				   RK3288_GRF_SOC_STATUS);
+				   RK3288_GRF_SOC_STATUS1);
 	rockchip_clk_register_branches(rk3288_clk_branches,
 				  ARRAY_SIZE(rk3288_clk_branches));
 	rockchip_clk_protect_critical(rk3288_critical_clocks,
-- 
2.0.1

  parent reply	other threads:[~2014-09-17 22:12 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-09-17 22:12 [PATCH v3 0/8] ARM: Rockchip: add cpuclk handling - clock-tree part Heiko Stuebner
2014-09-17 22:12 ` [PATCH v3 1/8] clk: rockchip: change pll rate without a clk-notifier Heiko Stuebner
2014-09-17 22:46   ` Doug Anderson
2014-09-17 23:13     ` Heiko Stübner
2014-09-25 22:50       ` Mike Turquette
2014-09-17 22:12 ` [PATCH v3 2/8] clk: rockchip: fix rk3066 pll status register location Heiko Stuebner
2014-09-17 22:12 ` Heiko Stuebner [this message]
2014-09-17 22:12 ` [PATCH v3 4/8] clk: rockchip: reparent aclk_cpu_pre to the gpll Heiko Stuebner
2014-09-17 22:12 ` [PATCH v3 5/8] clk: rockchip: make tightly bound armclk child-clocks read-only Heiko Stuebner
2014-09-17 22:12 ` [PATCH v3 6/8] clk: rockchip: add new clock-type for the cpuclk Heiko Stuebner
2014-09-22 17:47   ` Doug Anderson
2014-09-22 19:21     ` Heiko Stübner
2014-09-22 19:33       ` Doug Anderson
2014-09-23  5:25       ` Thomas Abraham
2014-09-23 18:16         ` Doug Anderson
2014-09-17 22:12 ` [PATCH v3 7/8] clk: rockchip: add binding id for ARMCLK Heiko Stuebner
2014-09-22 17:08   ` Doug Anderson
2014-09-17 22:12 ` [PATCH v3 8/8] clk: rockchip: switch to using the new cpuclk type for armclk Heiko Stuebner
2014-09-22 17:51   ` Doug Anderson

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