From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chen-Yu Tsai Date: Wed, 24 Sep 2014 16:01:11 +0800 Subject: [U-Boot] [PATCH v2 08/10] ARM: sun6i: Setup the A31 UART0 muxing In-Reply-To: <1411545673-5591-1-git-send-email-wens@csie.org> References: <1411545673-5591-1-git-send-email-wens@csie.org> Message-ID: <1411545673-5591-9-git-send-email-wens@csie.org> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de From: Maxime Ripard Signed-off-by: Maxime Ripard Signed-off-by: Hans de Goede [wens at csie.org: commit message was "ARM: sunxi: Setup the A31 UART0 muxing"] [wens at csie.org: reorder #ifs by SUN?I] [wens at csie.org: replace magic numbers with GPIO definitions] Signed-off-by: Chen-Yu Tsai --- arch/arm/cpu/armv7/sunxi/board.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c index 95a74c5..b6d63db 100644 --- a/arch/arm/cpu/armv7/sunxi/board.c +++ b/arch/arm/cpu/armv7/sunxi/board.c @@ -58,6 +58,10 @@ int gpio_init(void) sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB19_UART0_TX); sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB20_UART0_RX); sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_SUN6I) + sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH20_UART0_TX); + sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH21_UART0_RX); + sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP); #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_SUN5I) sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART1_TX); sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART1_RX); -- 2.1.0