From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38389) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XXQgy-000313-S9 for qemu-devel@nongnu.org; Fri, 26 Sep 2014 04:15:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XXQgt-0004rr-PK for qemu-devel@nongnu.org; Fri, 26 Sep 2014 04:15:52 -0400 Received: from mail-yh0-x231.google.com ([2607:f8b0:4002:c01::231]:61120) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XXQgt-0004r9-Lj for qemu-devel@nongnu.org; Fri, 26 Sep 2014 04:15:47 -0400 Received: by mail-yh0-f49.google.com with SMTP id z6so3245398yhz.22 for ; Fri, 26 Sep 2014 01:15:42 -0700 (PDT) From: "Edgar E. Iglesias" Date: Fri, 26 Sep 2014 18:08:27 +1000 Message-Id: <1411718914-6608-5-git-send-email-edgar.iglesias@gmail.com> In-Reply-To: <1411718914-6608-1-git-send-email-edgar.iglesias@gmail.com> References: <1411718914-6608-1-git-send-email-edgar.iglesias@gmail.com> Subject: [Qemu-devel] [PATCH v7 04/11] target-arm: Break out exception masking to a separate func List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: rob.herring@linaro.org, peter.crosthwaite@xilinx.com, aggelerf@ethz.ch, serge.fdrv@gmail.com, agraf@suse.de, greg.bellows@linaro.org, pbonzini@redhat.com, alex.bennee@linaro.org, christoffer.dall@linaro.org, rth@twiddle.net From: "Edgar E. Iglesias" Reviewed-by: Greg Bellows Signed-off-by: Edgar E. Iglesias --- cpu-exec.c | 5 ++--- target-arm/cpu.h | 15 +++++++++++++++ 2 files changed, 17 insertions(+), 3 deletions(-) diff --git a/cpu-exec.c b/cpu-exec.c index bd93165..d017588 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -596,7 +596,7 @@ int cpu_exec(CPUArchState *env) } #elif defined(TARGET_ARM) if (interrupt_request & CPU_INTERRUPT_FIQ - && !(env->daif & PSTATE_F)) { + && arm_excp_unmasked(cpu, EXCP_FIQ)) { cpu->exception_index = EXCP_FIQ; cc->do_interrupt(cpu); next_tb = 0; @@ -611,8 +611,7 @@ int cpu_exec(CPUArchState *env) We avoid this by disabling interrupts when pc contains a magic address. */ if (interrupt_request & CPU_INTERRUPT_HARD - && !(env->daif & PSTATE_I) - && (!IS_M(env) || env->regs[15] < 0xfffffff0)) { + && arm_excp_unmasked(cpu, EXCP_IRQ)) { cpu->exception_index = EXCP_IRQ; cc->do_interrupt(cpu); next_tb = 0; diff --git a/target-arm/cpu.h b/target-arm/cpu.h index e2474d0..a5e8e0d 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -1171,6 +1171,21 @@ bool write_cpustate_to_list(ARMCPU *cpu); # define TARGET_VIRT_ADDR_SPACE_BITS 32 #endif +static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx) +{ + CPUARMState *env = cs->env_ptr; + + switch (excp_idx) { + case EXCP_FIQ: + return !(env->daif & PSTATE_F); + case EXCP_IRQ: + return !(env->daif & PSTATE_I) + && (!IS_M(env) || env->regs[15] < 0xfffffff0); + default: + g_assert_not_reached(); + } +} + static inline CPUARMState *cpu_init(const char *cpu_model) { ARMCPU *cpu = cpu_arm_init(cpu_model); -- 1.9.1