From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754489AbaIZIz6 (ORCPT ); Fri, 26 Sep 2014 04:55:58 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:46812 "EHLO mx08-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754443AbaIZIzy (ORCPT ); Fri, 26 Sep 2014 04:55:54 -0400 From: Gabriel FERNANDEZ To: Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Srinivas Kandagatla , Maxime Coquelin , Patrice Chotard , Russell King , Kishon Vijay Abraham I , Grant Likely Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@stlinux.com, Lee Jones , Gabriel Fernandez , Harsh Gupta Subject: [PATCH v3 6/8] phy: miphy28lp: Add SSC support for PCIE Date: Fri, 26 Sep 2014 10:54:15 +0200 Message-Id: <1411721657-9924-7-git-send-email-gabriel.fernandez@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1411721657-9924-1-git-send-email-gabriel.fernandez@linaro.org> References: <1411721657-9924-1-git-send-email-gabriel.fernandez@linaro.org> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:5.12.52,1.0.28,0.0.0000 definitions=2014-09-26_04:2014-09-26,2014-09-26,1970-01-01 signatures=0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org SSC is the technique of modulating the operating frequency of a signal slightly to spread its radiated emissions over a range of frequencies. This reduction in the maximum emission for a given frequency helps meet radiated emission requirements. These settings are applicable for PCIE with Internal clock. Signed-off-by: Harsh Gupta Signed-off-by: Gabriel Fernandez --- drivers/phy/phy-miphy28lp.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/drivers/phy/phy-miphy28lp.c b/drivers/phy/phy-miphy28lp.c index 7285543..b6574e8 100644 --- a/drivers/phy/phy-miphy28lp.c +++ b/drivers/phy/phy-miphy28lp.c @@ -579,6 +579,35 @@ static void miphy_sata_tune_ssc(struct miphy28lp_phy *miphy_phy) } } +static void miphy_pcie_tune_ssc(struct miphy28lp_phy *miphy_phy) +{ + u8 val; + + /* Compensate Tx impedance to avoid out of range values */ + /* + * Enable the SSC on PLL for all banks + * SSC Modulation @ 31 KHz and 4000 ppm modulation amp + */ + val = readb_relaxed(miphy_phy->base + MIPHY_BOUNDARY_2); + val |= SSC_EN_SW; + writeb_relaxed(val, miphy_phy->base + MIPHY_BOUNDARY_2); + + val = readb_relaxed(miphy_phy->base + MIPHY_BOUNDARY_SEL); + val |= SSC_SEL; + writeb_relaxed(val, miphy_phy->base + MIPHY_BOUNDARY_SEL); + + for (val = 0; val < 2; val++) { + writeb_relaxed(val, miphy_phy->base + MIPHY_CONF); + writeb_relaxed(0x69, miphy_phy->base + MIPHY_PLL_SBR_3); + writeb_relaxed(0x21, miphy_phy->base + MIPHY_PLL_SBR_4); + writeb_relaxed(0x3c, miphy_phy->base + MIPHY_PLL_SBR_2); + writeb_relaxed(0x21, miphy_phy->base + MIPHY_PLL_SBR_4); + writeb_relaxed(0x00, miphy_phy->base + MIPHY_PLL_SBR_1); + writeb_relaxed(0x02, miphy_phy->base + MIPHY_PLL_SBR_1); + writeb_relaxed(0x00, miphy_phy->base + MIPHY_PLL_SBR_1); + } +} + static inline int miphy28lp_configure_sata(struct miphy28lp_phy *miphy_phy) { void __iomem *base = miphy_phy->base; @@ -647,6 +676,9 @@ static inline int miphy28lp_configure_pcie(struct miphy28lp_phy *miphy_phy) if (err) return err; + if (miphy_phy->ssc) + miphy_pcie_tune_ssc(miphy_phy); + return 0; } -- 1.9.1 From mboxrd@z Thu Jan 1 00:00:00 1970 From: gabriel.fernandez@st.com (Gabriel FERNANDEZ) Date: Fri, 26 Sep 2014 10:54:15 +0200 Subject: [PATCH v3 6/8] phy: miphy28lp: Add SSC support for PCIE In-Reply-To: <1411721657-9924-1-git-send-email-gabriel.fernandez@linaro.org> References: <1411721657-9924-1-git-send-email-gabriel.fernandez@linaro.org> Message-ID: <1411721657-9924-7-git-send-email-gabriel.fernandez@linaro.org> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org SSC is the technique of modulating the operating frequency of a signal slightly to spread its radiated emissions over a range of frequencies. This reduction in the maximum emission for a given frequency helps meet radiated emission requirements. These settings are applicable for PCIE with Internal clock. Signed-off-by: Harsh Gupta Signed-off-by: Gabriel Fernandez --- drivers/phy/phy-miphy28lp.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/drivers/phy/phy-miphy28lp.c b/drivers/phy/phy-miphy28lp.c index 7285543..b6574e8 100644 --- a/drivers/phy/phy-miphy28lp.c +++ b/drivers/phy/phy-miphy28lp.c @@ -579,6 +579,35 @@ static void miphy_sata_tune_ssc(struct miphy28lp_phy *miphy_phy) } } +static void miphy_pcie_tune_ssc(struct miphy28lp_phy *miphy_phy) +{ + u8 val; + + /* Compensate Tx impedance to avoid out of range values */ + /* + * Enable the SSC on PLL for all banks + * SSC Modulation @ 31 KHz and 4000 ppm modulation amp + */ + val = readb_relaxed(miphy_phy->base + MIPHY_BOUNDARY_2); + val |= SSC_EN_SW; + writeb_relaxed(val, miphy_phy->base + MIPHY_BOUNDARY_2); + + val = readb_relaxed(miphy_phy->base + MIPHY_BOUNDARY_SEL); + val |= SSC_SEL; + writeb_relaxed(val, miphy_phy->base + MIPHY_BOUNDARY_SEL); + + for (val = 0; val < 2; val++) { + writeb_relaxed(val, miphy_phy->base + MIPHY_CONF); + writeb_relaxed(0x69, miphy_phy->base + MIPHY_PLL_SBR_3); + writeb_relaxed(0x21, miphy_phy->base + MIPHY_PLL_SBR_4); + writeb_relaxed(0x3c, miphy_phy->base + MIPHY_PLL_SBR_2); + writeb_relaxed(0x21, miphy_phy->base + MIPHY_PLL_SBR_4); + writeb_relaxed(0x00, miphy_phy->base + MIPHY_PLL_SBR_1); + writeb_relaxed(0x02, miphy_phy->base + MIPHY_PLL_SBR_1); + writeb_relaxed(0x00, miphy_phy->base + MIPHY_PLL_SBR_1); + } +} + static inline int miphy28lp_configure_sata(struct miphy28lp_phy *miphy_phy) { void __iomem *base = miphy_phy->base; @@ -647,6 +676,9 @@ static inline int miphy28lp_configure_pcie(struct miphy28lp_phy *miphy_phy) if (err) return err; + if (miphy_phy->ssc) + miphy_pcie_tune_ssc(miphy_phy); + return 0; } -- 1.9.1