From mboxrd@z Thu Jan 1 00:00:00 1970 From: Damien Lespiau Subject: [PATCH i-g-t 15/26] rendercopy/skl: Set the URB VS start address to 4 Date: Fri, 26 Sep 2014 15:03:13 +0100 Message-ID: <1411740204-25709-15-git-send-email-damien.lespiau@intel.com> References: <1411740204-25709-1-git-send-email-damien.lespiau@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 45A936E77B for ; Fri, 26 Sep 2014 07:04:35 -0700 (PDT) In-Reply-To: <1411740204-25709-1-git-send-email-damien.lespiau@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org From: "Xiang, Haihao" A value less than 4 might result in GPU hang on simulation Signed-off-by: Xiang, Haihao Signed-off-by: Ben Widawsky Signed-off-by: Damien Lespiau --- lib/rendercopy_gen9.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c index 8621f7f..92265c1 100644 --- a/lib/rendercopy_gen9.c +++ b/lib/rendercopy_gen9.c @@ -558,7 +558,7 @@ gen7_emit_urb(struct intel_batchbuffer *batch) { /* XXX: Min valid values from mesa */ const int vs_entries = 64; const int vs_size = 2; - const int vs_start = 2; + const int vs_start = 4; OUT_BATCH(GEN7_3DSTATE_URB_VS); OUT_BATCH(vs_entries | ((vs_size - 1) << 16) | (vs_start << 25)); -- 1.8.3.1