From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44600) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xz2j4-0004zH-CZ for qemu-devel@nongnu.org; Thu, 11 Dec 2014 07:20:11 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Xz2j3-0007St-6r for qemu-devel@nongnu.org; Thu, 11 Dec 2014 07:20:10 -0500 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:54567) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xz2j3-0006sg-0N for qemu-devel@nongnu.org; Thu, 11 Dec 2014 07:20:09 -0500 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1Xz2iq-00019x-86 for qemu-devel@nongnu.org; Thu, 11 Dec 2014 12:19:56 +0000 From: Peter Maydell Date: Thu, 11 Dec 2014 12:19:39 +0000 Message-Id: <1418300395-4348-18-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1418300395-4348-1-git-send-email-peter.maydell@linaro.org> References: <1418300395-4348-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PULL 17/33] target-arm: make CSSELR banked List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org From: Fabian Aggeler Rename CSSELR (cache size selection register) and add secure instance (AArch32). Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows Reviewed-by: Peter Maydell Message-id: 1416242878-876-16-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell --- target-arm/cpu.h | 10 +++++++++- target-arm/helper.c | 14 +++++++++++--- 2 files changed, 20 insertions(+), 4 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 6559aa8..f06d209 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -177,7 +177,15 @@ typedef struct CPUARMState { /* System control coprocessor (cp15) */ struct { uint32_t c0_cpuid; - uint64_t c0_cssel; /* Cache size selection. */ + union { /* Cache size selection */ + struct { + uint64_t _unused_csselr0; + uint64_t csselr_ns; + uint64_t _unused_csselr1; + uint64_t csselr_s; + }; + uint64_t csselr_el[4]; + }; union { /* System control register. */ struct { uint64_t _unused_sctlr; diff --git a/target-arm/helper.c b/target-arm/helper.c index d43d208..961dd37 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -776,7 +776,14 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri) { ARMCPU *cpu = arm_env_get_cpu(env); - return cpu->ccsidr[env->cp15.c0_cssel]; + + /* Acquire the CSSELR index from the bank corresponding to the CCSIDR + * bank + */ + uint32_t index = A32_BANKED_REG_GET(env, csselr, + ri->secure & ARM_CP_SECSTATE_S); + + return cpu->ccsidr[index]; } static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -903,8 +910,9 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE }, { .name = "CSSELR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0, - .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c0_cssel), - .writefn = csselr_write, .resetvalue = 0 }, + .access = PL1_RW, .writefn = csselr_write, .resetvalue = 0, + .bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s), + offsetof(CPUARMState, cp15.csselr_ns) } }, /* Auxiliary ID register: this actually has an IMPDEF value but for now * just RAZ for all cores: */ -- 1.9.1