From mboxrd@z Thu Jan 1 00:00:00 1970 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Dec 2014 16:29:24 +0100 (CET) Received: from mailapp01.imgtec.com ([195.59.15.196]:38716 "EHLO mailapp01.imgtec.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S27009214AbaLRPNdOdDwA (ORCPT ); Thu, 18 Dec 2014 16:13:33 +0100 Received: from KLMAIL01.kl.imgtec.org (unknown [192.168.5.35]) by Websense Email Security Gateway with ESMTPS id 727296A7CAAA5 for ; Thu, 18 Dec 2014 15:13:24 +0000 (GMT) Received: from LEMAIL01.le.imgtec.org (192.168.152.62) by KLMAIL01.kl.imgtec.org (192.168.5.35) with Microsoft SMTP Server (TLS) id 14.3.195.1; Thu, 18 Dec 2014 15:13:27 +0000 Received: from mchandras-linux.le.imgtec.org (192.168.154.125) by LEMAIL01.le.imgtec.org (192.168.152.62) with Microsoft SMTP Server (TLS) id 14.3.210.2; Thu, 18 Dec 2014 15:13:26 +0000 From: Markos Chandras To: CC: Markos Chandras Subject: [PATCH RFC 62/67] MIPS: asm: mipsregs: Add support for the LLADDR register Date: Thu, 18 Dec 2014 15:10:11 +0000 Message-ID: <1418915416-3196-63-git-send-email-markos.chandras@imgtec.com> X-Mailer: git-send-email 2.2.0 In-Reply-To: <1418915416-3196-1-git-send-email-markos.chandras@imgtec.com> References: <1418915416-3196-1-git-send-email-markos.chandras@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [192.168.154.125] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 44797 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: markos.chandras@imgtec.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips If Config5/LLB is set in the core, then software can write the LLB bit in the LLADDR register. Signed-off-by: Markos Chandras --- arch/mips/include/asm/mipsregs.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 8b27e17c1cad..1746a039a491 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -1085,6 +1085,8 @@ do { \ #define write_c0_config6(val) __write_32bit_c0_register($16, 6, val) #define write_c0_config7(val) __write_32bit_c0_register($16, 7, val) +#define read_c0_lladdr() __read_ulong_c0_register($17, 0) +#define write_c0_lladdr(val) __write_ulong_c0_register($17, 0, val) #define read_c0_maar() __read_ulong_c0_register($17, 1) #define write_c0_maar(val) __write_ulong_c0_register($17, 1, val) #define read_c0_maari() __read_32bit_c0_register($17, 2) -- 2.2.0 From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailapp01.imgtec.com ([195.59.15.196]:38716 "EHLO mailapp01.imgtec.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S27009214AbaLRPNdOdDwA (ORCPT ); Thu, 18 Dec 2014 16:13:33 +0100 Received: from KLMAIL01.kl.imgtec.org (unknown [192.168.5.35]) by Websense Email Security Gateway with ESMTPS id 727296A7CAAA5 for ; Thu, 18 Dec 2014 15:13:24 +0000 (GMT) From: Markos Chandras Subject: [PATCH RFC 62/67] MIPS: asm: mipsregs: Add support for the LLADDR register Date: Thu, 18 Dec 2014 15:10:11 +0000 Message-ID: <1418915416-3196-63-git-send-email-markos.chandras@imgtec.com> In-Reply-To: <1418915416-3196-1-git-send-email-markos.chandras@imgtec.com> References: <1418915416-3196-1-git-send-email-markos.chandras@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain Return-Path: Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-subscribe: List-owner: List-post: List-archive: To: linux-mips@linux-mips.org Cc: Markos Chandras Message-ID: <20141218151011.offar8P2GFnQpECNIvwlbdLxM4Gl2k6-6aEhtC7akdg@z> If Config5/LLB is set in the core, then software can write the LLB bit in the LLADDR register. Signed-off-by: Markos Chandras --- arch/mips/include/asm/mipsregs.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 8b27e17c1cad..1746a039a491 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -1085,6 +1085,8 @@ do { \ #define write_c0_config6(val) __write_32bit_c0_register($16, 6, val) #define write_c0_config7(val) __write_32bit_c0_register($16, 7, val) +#define read_c0_lladdr() __read_ulong_c0_register($17, 0) +#define write_c0_lladdr(val) __write_ulong_c0_register($17, 0, val) #define read_c0_maar() __read_ulong_c0_register($17, 1) #define write_c0_maar(val) __write_ulong_c0_register($17, 1, val) #define read_c0_maari() __read_32bit_c0_register($17, 2) -- 2.2.0