From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34577) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Y1e3y-0000YT-GD for qemu-devel@nongnu.org; Thu, 18 Dec 2014 11:36:39 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Y1e3n-0006cA-JX for qemu-devel@nongnu.org; Thu, 18 Dec 2014 11:36:30 -0500 From: Tom Musta Date: Thu, 18 Dec 2014 10:34:29 -0600 Message-Id: <1418920477-11669-2-git-send-email-tommusta@gmail.com> In-Reply-To: <1418920477-11669-1-git-send-email-tommusta@gmail.com> References: <1418920477-11669-1-git-send-email-tommusta@gmail.com> Subject: [Qemu-devel] [PATCH 1/9] target-ppc: Introduce Instruction Type for Transactional Memory List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: Tom Musta , agraf@suse.de Add a category (PPC2_TM) for the Transactional Memory instructions introduced in Power ISA 2.07. Signed-off-by: Tom Musta --- target-ppc/cpu.h | 4 +++- 1 files changed, 3 insertions(+), 1 deletions(-) diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 068fcb2..3510083 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -2010,6 +2010,8 @@ enum { PPC2_ISA207S = 0x0000000000008000ULL, /* Double precision floating point conversion for signed integer 64 */ PPC2_FP_CVT_S64 = 0x0000000000010000ULL, + /* Transactional Memory (ISA 2.07, Book II) */ + PPC2_TM = 0x0000000000020000ULL, #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \ PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \ @@ -2017,7 +2019,7 @@ enum { PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \ PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \ PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \ - PPC2_FP_CVT_S64) + PPC2_FP_CVT_S64 | PPC2_TM) }; /*****************************************************************************/ -- 1.7.1