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From: Rob Herring <robh@kernel.org>
To: linux-kernel@vger.kernel.org
Cc: Arnd Bergmann <arnd@arndb.de>,
	linux-pci@vger.kernel.org, Bjorn Helgaas <bhelgaas@google.com>,
	Rob Herring <robh@kernel.org>, Tanmay Inamdar <tinamdar@apm.com>,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH 15/16] pci/host: xgene: convert to use generic config accesses
Date: Fri,  9 Jan 2015 20:34:49 -0600	[thread overview]
Message-ID: <1420857290-8373-16-git-send-email-robh@kernel.org> (raw)
In-Reply-To: <1420857290-8373-1-git-send-email-robh@kernel.org>

Convert the xgene host PCI driver to use the generic config access
functions.

Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Tanmay Inamdar <tinamdar@apm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: linux-pci@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
---
 drivers/pci/host/pci-xgene.c | 150 +++----------------------------------------
 1 file changed, 9 insertions(+), 141 deletions(-)

diff --git a/drivers/pci/host/pci-xgene.c b/drivers/pci/host/pci-xgene.c
index b1d0596..ee6a3d3 100644
--- a/drivers/pci/host/pci-xgene.c
+++ b/drivers/pci/host/pci-xgene.c
@@ -74,92 +74,6 @@ static inline u32 pcie_bar_low_val(u32 addr, u32 flags)
 	return (addr & PCI_BASE_ADDRESS_MEM_MASK) | flags;
 }
 
-/* PCIe Configuration Out/In */
-static inline void xgene_pcie_cfg_out32(void __iomem *addr, int offset, u32 val)
-{
-	writel(val, addr + offset);
-}
-
-static inline void xgene_pcie_cfg_out16(void __iomem *addr, int offset, u16 val)
-{
-	u32 val32 = readl(addr + (offset & ~0x3));
-
-	switch (offset & 0x3) {
-	case 2:
-		val32 &= ~0xFFFF0000;
-		val32 |= (u32)val << 16;
-		break;
-	case 0:
-	default:
-		val32 &= ~0xFFFF;
-		val32 |= val;
-		break;
-	}
-	writel(val32, addr + (offset & ~0x3));
-}
-
-static inline void xgene_pcie_cfg_out8(void __iomem *addr, int offset, u8 val)
-{
-	u32 val32 = readl(addr + (offset & ~0x3));
-
-	switch (offset & 0x3) {
-	case 0:
-		val32 &= ~0xFF;
-		val32 |= val;
-		break;
-	case 1:
-		val32 &= ~0xFF00;
-		val32 |= (u32)val << 8;
-		break;
-	case 2:
-		val32 &= ~0xFF0000;
-		val32 |= (u32)val << 16;
-		break;
-	case 3:
-	default:
-		val32 &= ~0xFF000000;
-		val32 |= (u32)val << 24;
-		break;
-	}
-	writel(val32, addr + (offset & ~0x3));
-}
-
-static inline void xgene_pcie_cfg_in32(void __iomem *addr, int offset, u32 *val)
-{
-	*val = readl(addr + offset);
-}
-
-static inline void xgene_pcie_cfg_in16(void __iomem *addr, int offset, u32 *val)
-{
-	*val = readl(addr + (offset & ~0x3));
-
-	switch (offset & 0x3) {
-	case 2:
-		*val >>= 16;
-		break;
-	}
-
-	*val &= 0xFFFF;
-}
-
-static inline void xgene_pcie_cfg_in8(void __iomem *addr, int offset, u32 *val)
-{
-	*val = readl(addr + (offset & ~0x3));
-
-	switch (offset & 0x3) {
-	case 3:
-		*val = *val >> 24;
-		break;
-	case 2:
-		*val = *val >> 16;
-		break;
-	case 1:
-		*val = *val >> 8;
-		break;
-	}
-	*val &= 0xFF;
-}
-
 /*
  * When the address bit [17:16] is 2'b01, the Configuration access will be
  * treated as Type 1 and it will be forwarded to external PCIe device.
@@ -213,69 +127,23 @@ static bool xgene_pcie_hide_rc_bars(struct pci_bus *bus, int offset)
 	return false;
 }
 
-static int xgene_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
-				  int offset, int len, u32 *val)
-{
-	struct xgene_pcie_port *port = bus->sysdata;
-	void __iomem *addr;
-
-	if ((pci_is_root_bus(bus) && devfn != 0) || !port->link_up)
-		return PCIBIOS_DEVICE_NOT_FOUND;
-
-	if (xgene_pcie_hide_rc_bars(bus, offset)) {
-		*val = 0;
-		return PCIBIOS_SUCCESSFUL;
-	}
-
-	xgene_pcie_set_rtdid_reg(bus, devfn);
-	addr = xgene_pcie_get_cfg_base(bus);
-	switch (len) {
-	case 1:
-		xgene_pcie_cfg_in8(addr, offset, val);
-		break;
-	case 2:
-		xgene_pcie_cfg_in16(addr, offset, val);
-		break;
-	default:
-		xgene_pcie_cfg_in32(addr, offset, val);
-		break;
-	}
-
-	return PCIBIOS_SUCCESSFUL;
-}
-
-static int xgene_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
-				   int offset, int len, u32 val)
+static int xgene_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
+			      int offset)
 {
 	struct xgene_pcie_port *port = bus->sysdata;
-	void __iomem *addr;
 
-	if ((pci_is_root_bus(bus) && devfn != 0) || !port->link_up)
-		return PCIBIOS_DEVICE_NOT_FOUND;
-
-	if (xgene_pcie_hide_rc_bars(bus, offset))
-		return PCIBIOS_SUCCESSFUL;
+	if ((pci_is_root_bus(bus) && devfn != 0) || !port->link_up ||
+	    xgene_pcie_hide_rc_bars(bus, offset))
+		return NULL;
 
 	xgene_pcie_set_rtdid_reg(bus, devfn);
-	addr = xgene_pcie_get_cfg_base(bus);
-	switch (len) {
-	case 1:
-		xgene_pcie_cfg_out8(addr, offset, (u8)val);
-		break;
-	case 2:
-		xgene_pcie_cfg_out16(addr, offset, (u16)val);
-		break;
-	default:
-		xgene_pcie_cfg_out32(addr, offset, val);
-		break;
-	}
-
-	return PCIBIOS_SUCCESSFUL;
+	return xgene_pcie_get_cfg_base(bus);
 }
 
 static struct pci_ops xgene_pcie_ops = {
-	.read = xgene_pcie_read_config,
-	.write = xgene_pcie_write_config
+	.map_bus = xgene_pcie_map_bus,
+	.read = pci_generic_config_read32,
+	.write = pci_generic_config_write32,
 };
 
 static u64 xgene_pcie_set_ib_mask(void __iomem *csr_base, u32 addr,
-- 
2.1.0


WARNING: multiple messages have this Message-ID (diff)
From: robh@kernel.org (Rob Herring)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 15/16] pci/host: xgene: convert to use generic config accesses
Date: Fri,  9 Jan 2015 20:34:49 -0600	[thread overview]
Message-ID: <1420857290-8373-16-git-send-email-robh@kernel.org> (raw)
In-Reply-To: <1420857290-8373-1-git-send-email-robh@kernel.org>

Convert the xgene host PCI driver to use the generic config access
functions.

Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Tanmay Inamdar <tinamdar@apm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: linux-pci at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
---
 drivers/pci/host/pci-xgene.c | 150 +++----------------------------------------
 1 file changed, 9 insertions(+), 141 deletions(-)

diff --git a/drivers/pci/host/pci-xgene.c b/drivers/pci/host/pci-xgene.c
index b1d0596..ee6a3d3 100644
--- a/drivers/pci/host/pci-xgene.c
+++ b/drivers/pci/host/pci-xgene.c
@@ -74,92 +74,6 @@ static inline u32 pcie_bar_low_val(u32 addr, u32 flags)
 	return (addr & PCI_BASE_ADDRESS_MEM_MASK) | flags;
 }
 
-/* PCIe Configuration Out/In */
-static inline void xgene_pcie_cfg_out32(void __iomem *addr, int offset, u32 val)
-{
-	writel(val, addr + offset);
-}
-
-static inline void xgene_pcie_cfg_out16(void __iomem *addr, int offset, u16 val)
-{
-	u32 val32 = readl(addr + (offset & ~0x3));
-
-	switch (offset & 0x3) {
-	case 2:
-		val32 &= ~0xFFFF0000;
-		val32 |= (u32)val << 16;
-		break;
-	case 0:
-	default:
-		val32 &= ~0xFFFF;
-		val32 |= val;
-		break;
-	}
-	writel(val32, addr + (offset & ~0x3));
-}
-
-static inline void xgene_pcie_cfg_out8(void __iomem *addr, int offset, u8 val)
-{
-	u32 val32 = readl(addr + (offset & ~0x3));
-
-	switch (offset & 0x3) {
-	case 0:
-		val32 &= ~0xFF;
-		val32 |= val;
-		break;
-	case 1:
-		val32 &= ~0xFF00;
-		val32 |= (u32)val << 8;
-		break;
-	case 2:
-		val32 &= ~0xFF0000;
-		val32 |= (u32)val << 16;
-		break;
-	case 3:
-	default:
-		val32 &= ~0xFF000000;
-		val32 |= (u32)val << 24;
-		break;
-	}
-	writel(val32, addr + (offset & ~0x3));
-}
-
-static inline void xgene_pcie_cfg_in32(void __iomem *addr, int offset, u32 *val)
-{
-	*val = readl(addr + offset);
-}
-
-static inline void xgene_pcie_cfg_in16(void __iomem *addr, int offset, u32 *val)
-{
-	*val = readl(addr + (offset & ~0x3));
-
-	switch (offset & 0x3) {
-	case 2:
-		*val >>= 16;
-		break;
-	}
-
-	*val &= 0xFFFF;
-}
-
-static inline void xgene_pcie_cfg_in8(void __iomem *addr, int offset, u32 *val)
-{
-	*val = readl(addr + (offset & ~0x3));
-
-	switch (offset & 0x3) {
-	case 3:
-		*val = *val >> 24;
-		break;
-	case 2:
-		*val = *val >> 16;
-		break;
-	case 1:
-		*val = *val >> 8;
-		break;
-	}
-	*val &= 0xFF;
-}
-
 /*
  * When the address bit [17:16] is 2'b01, the Configuration access will be
  * treated as Type 1 and it will be forwarded to external PCIe device.
@@ -213,69 +127,23 @@ static bool xgene_pcie_hide_rc_bars(struct pci_bus *bus, int offset)
 	return false;
 }
 
-static int xgene_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
-				  int offset, int len, u32 *val)
-{
-	struct xgene_pcie_port *port = bus->sysdata;
-	void __iomem *addr;
-
-	if ((pci_is_root_bus(bus) && devfn != 0) || !port->link_up)
-		return PCIBIOS_DEVICE_NOT_FOUND;
-
-	if (xgene_pcie_hide_rc_bars(bus, offset)) {
-		*val = 0;
-		return PCIBIOS_SUCCESSFUL;
-	}
-
-	xgene_pcie_set_rtdid_reg(bus, devfn);
-	addr = xgene_pcie_get_cfg_base(bus);
-	switch (len) {
-	case 1:
-		xgene_pcie_cfg_in8(addr, offset, val);
-		break;
-	case 2:
-		xgene_pcie_cfg_in16(addr, offset, val);
-		break;
-	default:
-		xgene_pcie_cfg_in32(addr, offset, val);
-		break;
-	}
-
-	return PCIBIOS_SUCCESSFUL;
-}
-
-static int xgene_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
-				   int offset, int len, u32 val)
+static int xgene_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
+			      int offset)
 {
 	struct xgene_pcie_port *port = bus->sysdata;
-	void __iomem *addr;
 
-	if ((pci_is_root_bus(bus) && devfn != 0) || !port->link_up)
-		return PCIBIOS_DEVICE_NOT_FOUND;
-
-	if (xgene_pcie_hide_rc_bars(bus, offset))
-		return PCIBIOS_SUCCESSFUL;
+	if ((pci_is_root_bus(bus) && devfn != 0) || !port->link_up ||
+	    xgene_pcie_hide_rc_bars(bus, offset))
+		return NULL;
 
 	xgene_pcie_set_rtdid_reg(bus, devfn);
-	addr = xgene_pcie_get_cfg_base(bus);
-	switch (len) {
-	case 1:
-		xgene_pcie_cfg_out8(addr, offset, (u8)val);
-		break;
-	case 2:
-		xgene_pcie_cfg_out16(addr, offset, (u16)val);
-		break;
-	default:
-		xgene_pcie_cfg_out32(addr, offset, val);
-		break;
-	}
-
-	return PCIBIOS_SUCCESSFUL;
+	return xgene_pcie_get_cfg_base(bus);
 }
 
 static struct pci_ops xgene_pcie_ops = {
-	.read = xgene_pcie_read_config,
-	.write = xgene_pcie_write_config
+	.map_bus = xgene_pcie_map_bus,
+	.read = pci_generic_config_read32,
+	.write = pci_generic_config_write32,
 };
 
 static u64 xgene_pcie_set_ib_mask(void __iomem *csr_base, u32 addr,
-- 
2.1.0

  parent reply	other threads:[~2015-01-10  2:36 UTC|newest]

Thread overview: 74+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-01-10  2:34 [PATCH 00/16] PCI generic configuration space accessors Rob Herring
2015-01-10  2:34 ` Rob Herring
2015-01-10  2:34 ` Rob Herring
2015-01-10  2:34 ` Rob Herring
2015-01-10  2:34 ` Rob Herring
2015-01-10  2:34 ` [PATCH 01/16] frv: add struct pci_ops member names to initialization Rob Herring
2015-01-10  2:34 ` [PATCH 02/16] mips: " Rob Herring
2015-01-10  2:34 ` [PATCH 03/16] mn10300: " Rob Herring
2015-01-10  2:34 ` [PATCH 04/16] powerpc: " Rob Herring
2015-01-10  2:34   ` Rob Herring
2015-01-10  2:34 ` [PATCH 05/16] pci: introduce common pci config space accessors Rob Herring
2015-01-12 10:01   ` Thierry Reding
2015-01-12 10:04     ` Thierry Reding
2015-01-10  2:34 ` [PATCH 06/16] ARM: cns3xxx: convert PCI to use generic config accesses Rob Herring
2015-01-10  2:34   ` Rob Herring
2015-01-29  6:16   ` Krzysztof Hałasa
2015-01-29  6:16     ` Krzysztof Hałasa
2015-01-29 14:35     ` Bjorn Helgaas
2015-01-29 14:35       ` Bjorn Helgaas
2015-01-10  2:34 ` [PATCH 07/16] ARM: integrator: " Rob Herring
2015-01-10  2:34   ` Rob Herring
2015-01-10 21:40   ` Linus Walleij
2015-01-10 21:40     ` Linus Walleij
2015-01-10 21:40     ` Linus Walleij
2015-01-10 21:53     ` Arnd Bergmann
2015-01-10 21:53       ` Arnd Bergmann
2015-01-10 21:53       ` Arnd Bergmann
2015-01-12  0:05       ` Linus Walleij
2015-01-12  0:05         ` Linus Walleij
2015-01-12  0:05         ` Linus Walleij
2015-01-22 20:33         ` Bjorn Helgaas
2015-01-22 20:33           ` Bjorn Helgaas
2015-01-22 20:33           ` Bjorn Helgaas
2015-01-26 18:22           ` Bjorn Helgaas
2015-01-26 18:22             ` Bjorn Helgaas
2015-01-26 18:22             ` Bjorn Helgaas
2015-01-26 23:22             ` Linus Walleij
2015-01-26 23:22               ` Linus Walleij
2015-01-26 23:22               ` Linus Walleij
2015-01-10  2:34 ` [PATCH 08/16] ARM: sa1100: " Rob Herring
2015-01-10  2:34   ` Rob Herring
2015-01-10  2:34 ` [PATCH 09/16] ARM: ks8695: " Rob Herring
2015-01-10  2:34   ` Rob Herring
2015-01-12 12:38   ` Greg Ungerer
2015-01-12 12:38     ` Greg Ungerer
2015-01-10  2:34 ` [PATCH 10/16] powerpc: fsl_pci: " Rob Herring
2015-01-10  2:34   ` Rob Herring
2015-01-10  2:34 ` [PATCH 11/16] powerpc: powermac: " Rob Herring
2015-01-10  2:34   ` Rob Herring
2015-01-10  2:34 ` [PATCH 12/16] pci/host: generic: convert " Rob Herring
2015-01-10  2:34   ` Rob Herring
2015-01-12 17:51   ` Will Deacon
2015-01-12 17:51     ` Will Deacon
2015-01-12 17:51     ` Will Deacon
2015-01-10  2:34 ` [PATCH 13/16] pci/host: rcar-gen2: " Rob Herring
2015-01-10  2:34   ` Rob Herring
2015-01-12  9:25   ` Geert Uytterhoeven
2015-01-12  9:25     ` Geert Uytterhoeven
2015-01-10  2:34 ` [PATCH 14/16] pci/host: tegra: " Rob Herring
2015-01-12 10:07   ` Thierry Reding
2015-01-10  2:34 ` Rob Herring [this message]
2015-01-10  2:34   ` [PATCH 15/16] pci/host: xgene: " Rob Herring
2015-01-10  2:34 ` [PATCH 16/16] pci/host: xilinx: " Rob Herring
2015-01-10  2:34   ` Rob Herring
2015-01-22 21:03 ` [PATCH 00/16] PCI generic configuration space accessors Bjorn Helgaas
2015-01-22 21:03   ` Bjorn Helgaas
2015-01-22 21:03   ` Bjorn Helgaas
2015-01-22 21:03   ` Bjorn Helgaas
2015-01-22 21:03   ` Bjorn Helgaas
2015-01-22 23:47   ` Rob Herring
2015-01-22 23:47     ` Rob Herring
2015-01-22 23:47     ` Rob Herring
2015-01-22 23:47     ` Rob Herring
2015-01-22 23:47     ` Rob Herring

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