From mboxrd@z Thu Jan 1 00:00:00 1970 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 16 Jan 2015 11:51:27 +0100 (CET) Received: from mailapp01.imgtec.com ([195.59.15.196]:27376 "EHLO mailapp01.imgtec.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S27009732AbbAPKv0SJI7e (ORCPT ); Fri, 16 Jan 2015 11:51:26 +0100 Received: from KLMAIL01.kl.imgtec.org (unknown [192.168.5.35]) by Websense Email Security Gateway with ESMTPS id 99E547C9DC635 for ; Fri, 16 Jan 2015 10:51:18 +0000 (GMT) Received: from LEMAIL01.le.imgtec.org (192.168.152.62) by KLMAIL01.kl.imgtec.org (192.168.5.35) with Microsoft SMTP Server (TLS) id 14.3.195.1; Fri, 16 Jan 2015 10:51:20 +0000 Received: from mchandras-linux.le.imgtec.org (192.168.154.96) by LEMAIL01.le.imgtec.org (192.168.152.62) with Microsoft SMTP Server (TLS) id 14.3.210.2; Fri, 16 Jan 2015 10:51:20 +0000 From: Markos Chandras To: CC: Leonid Yegoshin , Markos Chandras Subject: [PATCH RFC v2 01/70] MIPS: Add generic QEMU PRid and cpu type identifiers Date: Fri, 16 Jan 2015 10:48:40 +0000 Message-ID: <1421405389-15512-2-git-send-email-markos.chandras@imgtec.com> X-Mailer: git-send-email 2.2.1 In-Reply-To: <1421405389-15512-1-git-send-email-markos.chandras@imgtec.com> References: <1421405389-15512-1-git-send-email-markos.chandras@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [192.168.154.96] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 45145 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: markos.chandras@imgtec.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips From: Leonid Yegoshin Latest versions of QEMU added support for mips32r6-generic and mips64r6-generic cpu types so add related definitions in preparation of MIPS R6 support. This is also used for QEMU R2 generic cpus. Signed-off-by: Leonid Yegoshin Signed-off-by: Markos Chandras --- arch/mips/include/asm/cpu.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index 33866fce4d63..0b74bbf976e4 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -93,6 +93,7 @@ * These are the PRID's for when 23:16 == PRID_COMP_MIPS */ +#define PRID_IMP_QEMU_GENERIC 0x0000 #define PRID_IMP_4KC 0x8000 #define PRID_IMP_5KC 0x8100 #define PRID_IMP_20KC 0x8200 @@ -312,6 +313,8 @@ enum cpu_type_enum { CPU_LOONGSON3, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2, CPU_CAVIUM_OCTEON3, CPU_XLR, CPU_XLP, + CPU_QEMU_GENERIC, + CPU_LAST }; -- 2.2.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailapp01.imgtec.com ([195.59.15.196]:27376 "EHLO mailapp01.imgtec.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S27009732AbbAPKv0SJI7e (ORCPT ); Fri, 16 Jan 2015 11:51:26 +0100 Received: from KLMAIL01.kl.imgtec.org (unknown [192.168.5.35]) by Websense Email Security Gateway with ESMTPS id 99E547C9DC635 for ; Fri, 16 Jan 2015 10:51:18 +0000 (GMT) From: Markos Chandras Subject: [PATCH RFC v2 01/70] MIPS: Add generic QEMU PRid and cpu type identifiers Date: Fri, 16 Jan 2015 10:48:40 +0000 Message-ID: <1421405389-15512-2-git-send-email-markos.chandras@imgtec.com> In-Reply-To: <1421405389-15512-1-git-send-email-markos.chandras@imgtec.com> References: <1421405389-15512-1-git-send-email-markos.chandras@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain Return-Path: Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-subscribe: List-owner: List-post: List-archive: To: linux-mips@linux-mips.org Cc: Leonid Yegoshin , Markos Chandras Message-ID: <20150116104840.V2754Uk80Xbv2oM0nXjV8lIhbTaW8OKw0a4dSFr_qPA@z> From: Leonid Yegoshin Latest versions of QEMU added support for mips32r6-generic and mips64r6-generic cpu types so add related definitions in preparation of MIPS R6 support. This is also used for QEMU R2 generic cpus. Signed-off-by: Leonid Yegoshin Signed-off-by: Markos Chandras --- arch/mips/include/asm/cpu.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index 33866fce4d63..0b74bbf976e4 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -93,6 +93,7 @@ * These are the PRID's for when 23:16 == PRID_COMP_MIPS */ +#define PRID_IMP_QEMU_GENERIC 0x0000 #define PRID_IMP_4KC 0x8000 #define PRID_IMP_5KC 0x8100 #define PRID_IMP_20KC 0x8200 @@ -312,6 +313,8 @@ enum cpu_type_enum { CPU_LOONGSON3, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2, CPU_CAVIUM_OCTEON3, CPU_XLR, CPU_XLP, + CPU_QEMU_GENERIC, + CPU_LAST }; -- 2.2.1