From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38712) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YEgvP-0005jc-R0 for qemu-devel@nongnu.org; Fri, 23 Jan 2015 11:17:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YEgvJ-00035I-KJ for qemu-devel@nongnu.org; Fri, 23 Jan 2015 11:17:35 -0500 Received: from mail-pd0-f174.google.com ([209.85.192.174]:60061) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YEgvJ-00035C-Eb for qemu-devel@nongnu.org; Fri, 23 Jan 2015 11:17:29 -0500 Received: by mail-pd0-f174.google.com with SMTP id ft15so9342215pdb.5 for ; Fri, 23 Jan 2015 08:17:29 -0800 (PST) From: Greg Bellows Date: Fri, 23 Jan 2015 10:17:13 -0600 Message-Id: <1422029835-4696-3-git-send-email-greg.bellows@linaro.org> In-Reply-To: <1422029835-4696-1-git-send-email-greg.bellows@linaro.org> References: <1422029835-4696-1-git-send-email-greg.bellows@linaro.org> Subject: [Qemu-devel] [PATCH V2 2/4] target-arm: Add extended RVBAR support List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: Greg Bellows Added RVBAR_EL2 and RVBAR_EL3 CP register support. All RVBAR_EL# registers point to the same location and only the highest EL version exists at any one time. Signed-off-by: Greg Bellows Reviewed-by: Peter Maydell --- target-arm/helper.c | 31 +++++++++++++++++++++++++------ 1 file changed, 25 insertions(+), 6 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index c9b1c08..29f3b62 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3053,17 +3053,30 @@ void register_cp_regs_for_features(ARMCPU *cpu) .resetvalue = cpu->mvfr2 }, REGINFO_SENTINEL }; - ARMCPRegInfo rvbar = { - .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64, - .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, - .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar - }; - define_one_arm_cp_reg(cpu, &rvbar); + /* RVBAR_EL1 is only implemented if EL1 is the highest EL */ + if (!arm_feature(env, ARM_FEATURE_EL3) && + !arm_feature(env, ARM_FEATURE_EL2)) { + ARMCPRegInfo rvbar = { + .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, + .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar + }; + define_one_arm_cp_reg(cpu, &rvbar); + } define_arm_cp_regs(cpu, v8_idregs); define_arm_cp_regs(cpu, v8_cp_reginfo); } if (arm_feature(env, ARM_FEATURE_EL2)) { define_arm_cp_regs(cpu, v8_el2_cp_reginfo); + /* RVBAR_EL2 is only implemented if EL2 is the highest EL */ + if (!arm_feature(env, ARM_FEATURE_EL3)) { + ARMCPRegInfo rvbar = { + .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1, + .type = ARM_CP_CONST, .access = PL2_R, .resetvalue = cpu->rvbar + }; + define_one_arm_cp_reg(cpu, &rvbar); + } } else { /* If EL2 is missing but higher ELs are enabled, we need to * register the no_el2 reginfos. @@ -3074,6 +3087,12 @@ void register_cp_regs_for_features(ARMCPU *cpu) } if (arm_feature(env, ARM_FEATURE_EL3)) { define_arm_cp_regs(cpu, el3_cp_reginfo); + ARMCPRegInfo rvbar = { + .name = "RVBAR_EL3", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 1, + .type = ARM_CP_CONST, .access = PL3_R, .resetvalue = cpu->rvbar + }; + define_one_arm_cp_reg(cpu, &rvbar); } if (arm_feature(env, ARM_FEATURE_MPU)) { /* These are the MPU registers prior to PMSAv6. Any new -- 1.8.3.2