From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41183) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YFovk-0005PK-Os for qemu-devel@nongnu.org; Mon, 26 Jan 2015 14:02:41 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YFovc-0001er-0l for qemu-devel@nongnu.org; Mon, 26 Jan 2015 14:02:36 -0500 Received: from mail.uni-paderborn.de ([131.234.142.9]:53267) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YFovb-0001em-Qy for qemu-devel@nongnu.org; Mon, 26 Jan 2015 14:02:27 -0500 From: Bastian Koppelmann Date: Mon, 26 Jan 2015 20:03:15 +0000 Message-Id: <1422302600-21514-5-git-send-email-kbastian@mail.uni-paderborn.de> In-Reply-To: <1422302600-21514-1-git-send-email-kbastian@mail.uni-paderborn.de> References: <1422302600-21514-1-git-send-email-kbastian@mail.uni-paderborn.de> Subject: [Qemu-devel] [PULL 4/9] target-tricore: Fix bugs found by coverity List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org This fixes one bug and one false positive found by coverity. The bug is, that gen_mtcr was missing a mask to check the flag, which resulted in dead code. The false positive is a intentional missing break for a jump and link address insn followed by a jump and link insn. This adds a fall through comment to avoid the false positive in the future. Reported-by: Markus Armbruster Signed-off-by: Bastian Koppelmann --- target-tricore/cpu.h | 1 + target-tricore/translate.c | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target-tricore/cpu.h b/target-tricore/cpu.h index 7555b70..e5409e4 100644 --- a/target-tricore/cpu.h +++ b/target-tricore/cpu.h @@ -238,6 +238,7 @@ struct CPUTriCoreState { #define MASK_LCX_LCXS 0x000f0000 #define MASK_LCX_LCX0 0x0000ffff +#define TRICORE_HFLAG_KUU 0x3 #define TRICORE_HFLAG_UM0 0x00002 /* user mode-0 flag */ #define TRICORE_HFLAG_UM1 0x00001 /* user mode-1 flag */ #define TRICORE_HFLAG_SM 0x00000 /* kernel mode flag */ diff --git a/target-tricore/translate.c b/target-tricore/translate.c index 61518f3..57949fa 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -343,7 +343,7 @@ static inline void gen_mfcr(CPUTriCoreState *env, TCGv ret, int32_t offset) static inline void gen_mtcr(CPUTriCoreState *env, DisasContext *ctx, TCGv r1, int32_t offset) { - if (ctx->hflags & TRICORE_HFLAG_SM) { + if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM) { /* since we're caching PSW make this a special case */ if (offset == 0xfe04) { gen_helper_psw_write(cpu_env, r1); @@ -1647,6 +1647,7 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1, break; case OPC1_32_B_JLA: tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc); + /* fall through */ case OPC1_32_B_JA: gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset)); break; -- 2.2.2