From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758892AbbA2LSL (ORCPT ); Thu, 29 Jan 2015 06:18:11 -0500 Received: from mailapp01.imgtec.com ([195.59.15.196]:64231 "EHLO mailapp01.imgtec.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755471AbbA2LOe (ORCPT ); Thu, 29 Jan 2015 06:14:34 -0500 From: James Hogan To: Ralf Baechle , CC: , James Hogan , Andrew Bresticker , Thomas Gleixner , Jason Cooper Subject: [PATCH 3/9] irqchip: mips-gic: Don't treat FDC IRQ as percpu devid Date: Thu, 29 Jan 2015 11:14:08 +0000 Message-ID: <1422530054-7976-4-git-send-email-james.hogan@imgtec.com> X-Mailer: git-send-email 2.0.5 In-Reply-To: <1422530054-7976-1-git-send-email-james.hogan@imgtec.com> References: <1422530054-7976-1-git-send-email-james.hogan@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [192.168.154.110] Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Treat the Fast Debug Channel (FDC) interrupt the same as the timer and performance counter interrupts. Like them, the FDC IRQ is also per-VPE, and also doesn't use a per-CPU device ID yet. Per-CPU device IDs don't seem to work with IRQF_SHARED which is needed for compatibility with cores which don't route the FDC IRQ through the GIC. For hardware which routes FDC IRQs through the GIC this is something that could be added later. Signed-off-by: James Hogan Cc: Ralf Baechle Cc: Andrew Bresticker Cc: Thomas Gleixner Cc: Jason Cooper Cc: linux-mips@linux-mips.org --- drivers/irqchip/irq-mips-gic.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c index 1f12eaedc9d9..bcfead6e8ae6 100644 --- a/drivers/irqchip/irq-mips-gic.c +++ b/drivers/irqchip/irq-mips-gic.c @@ -591,15 +591,20 @@ static int gic_local_irq_domain_map(struct irq_domain *d, unsigned int virq, * of the MIPS kernel code does not use the percpu IRQ API for * the CP0 timer and performance counter interrupts. */ - if (intr != GIC_LOCAL_INT_TIMER && intr != GIC_LOCAL_INT_PERFCTR) { + switch (intr) { + case GIC_LOCAL_INT_TIMER: + case GIC_LOCAL_INT_PERFCTR: + case GIC_LOCAL_INT_FDC: + irq_set_chip_and_handler(virq, + &gic_all_vpes_local_irq_controller, + handle_percpu_irq); + break; + default: irq_set_chip_and_handler(virq, &gic_local_irq_controller, handle_percpu_devid_irq); irq_set_percpu_devid(virq); - } else { - irq_set_chip_and_handler(virq, - &gic_all_vpes_local_irq_controller, - handle_percpu_irq); + break; } spin_lock_irqsave(&gic_lock, flags); -- 2.0.5 From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailapp01.imgtec.com ([195.59.15.196]:62304 "EHLO mailapp01.imgtec.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S27012166AbbA2LOiPGD6B (ORCPT ); Thu, 29 Jan 2015 12:14:38 +0100 From: James Hogan Subject: [PATCH 3/9] irqchip: mips-gic: Don't treat FDC IRQ as percpu devid Date: Thu, 29 Jan 2015 11:14:08 +0000 Message-ID: <1422530054-7976-4-git-send-email-james.hogan@imgtec.com> In-Reply-To: <1422530054-7976-1-git-send-email-james.hogan@imgtec.com> References: <1422530054-7976-1-git-send-email-james.hogan@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain Return-Path: Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-subscribe: List-owner: List-post: List-archive: To: Ralf Baechle , linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org, James Hogan , Andrew Bresticker , Thomas Gleixner , Jason Cooper Message-ID: <20150129111408.5543YbMZ0FmEcEIkR-XGtGCHRGUhQ4o_NnmZlZK1PWg@z> Treat the Fast Debug Channel (FDC) interrupt the same as the timer and performance counter interrupts. Like them, the FDC IRQ is also per-VPE, and also doesn't use a per-CPU device ID yet. Per-CPU device IDs don't seem to work with IRQF_SHARED which is needed for compatibility with cores which don't route the FDC IRQ through the GIC. For hardware which routes FDC IRQs through the GIC this is something that could be added later. Signed-off-by: James Hogan Cc: Ralf Baechle Cc: Andrew Bresticker Cc: Thomas Gleixner Cc: Jason Cooper Cc: linux-mips@linux-mips.org --- drivers/irqchip/irq-mips-gic.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c index 1f12eaedc9d9..bcfead6e8ae6 100644 --- a/drivers/irqchip/irq-mips-gic.c +++ b/drivers/irqchip/irq-mips-gic.c @@ -591,15 +591,20 @@ static int gic_local_irq_domain_map(struct irq_domain *d, unsigned int virq, * of the MIPS kernel code does not use the percpu IRQ API for * the CP0 timer and performance counter interrupts. */ - if (intr != GIC_LOCAL_INT_TIMER && intr != GIC_LOCAL_INT_PERFCTR) { + switch (intr) { + case GIC_LOCAL_INT_TIMER: + case GIC_LOCAL_INT_PERFCTR: + case GIC_LOCAL_INT_FDC: + irq_set_chip_and_handler(virq, + &gic_all_vpes_local_irq_controller, + handle_percpu_irq); + break; + default: irq_set_chip_and_handler(virq, &gic_local_irq_controller, handle_percpu_devid_irq); irq_set_percpu_devid(virq); - } else { - irq_set_chip_and_handler(virq, - &gic_all_vpes_local_irq_controller, - handle_percpu_irq); + break; } spin_lock_irqsave(&gic_lock, flags); -- 2.0.5