From mboxrd@z Thu Jan 1 00:00:00 1970 From: Julien Grall Subject: [PATCH v2 03/15] xen/arm: vgic-v3: Correctly handle GICD_CTLR Date: Thu, 29 Jan 2015 18:25:38 +0000 Message-ID: <1422555950-31821-4-git-send-email-julien.grall@linaro.org> References: <1422555950-31821-1-git-send-email-julien.grall@linaro.org> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1YGtne-0004b1-3h for xen-devel@lists.xenproject.org; Thu, 29 Jan 2015 18:26:42 +0000 Received: by mail-wg0-f49.google.com with SMTP id k14so23869747wgh.8 for ; Thu, 29 Jan 2015 10:26:40 -0800 (PST) In-Reply-To: <1422555950-31821-1-git-send-email-julien.grall@linaro.org> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: xen-devel@lists.xenproject.org Cc: stefano.stabellini@citrix.com, Vijaya.Kumar@caviumnetworks.com, Julien Grall , tim@xen.org, ian.campbell@citrix.com List-Id: xen-devel@lists.xenproject.org As backward GICv2 compatibility is not supported in the vGICv3 driver, the bit ARE_NS is RAO/WI. Furthermore, when ARE_NS is set, the guest can only modify EnableGrp1A. At same time take the vgic_lock to write into domain.arch.vgic.ctrl. It was already taken during read. Signed-off-by: Julien Grall --- Changes in v2: - Clearly explain that ARE_NS is RAO/WI rather than imply the guest should set it. - Typoes --- xen/arch/arm/vgic-v3.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c index e0a7d5b..9115199 100644 --- a/xen/arch/arm/vgic-v3.c +++ b/xen/arch/arm/vgic-v3.c @@ -45,6 +45,12 @@ #define GICV3_GICR_PIDR2 GICV3_GICD_PIDR2 #define GICV3_GICR_PIDR4 GICV3_GICD_PIDR4 +/* + * GICD_CTLR default value: + * - No GICv2 compatibility => ARE = 1 + */ +#define VGICD_CTLR_DEFAULT (GICD_CTLR_ARE_NS) + static struct vcpu *vgic_v3_irouter_to_vcpu(struct vcpu *v, uint64_t irouter) { irouter &= ~(GICD_IROUTER_SPI_MODE_ANY); @@ -838,8 +844,15 @@ static int vgic_v3_distr_mmio_write(struct vcpu *v, mmio_info_t *info) { case GICD_CTLR: if ( dabt.size != DABT_WORD ) goto bad_width; - /* Ignore all but the enable bit */ - v->domain->arch.vgic.ctlr = (*r) & GICD_CTL_ENABLE; + + vgic_lock(v); + /* Only EnableGrp1A can be changed */ + if ( *r & GICD_CTLR_ENABLE_G1A ) + v->domain->arch.vgic.ctlr |= GICD_CTLR_ENABLE_G1A; + else + v->domain->arch.vgic.ctlr &= ~GICD_CTLR_ENABLE_G1A; + vgic_unlock(v); + return 1; case GICD_TYPER: /* RO -- write ignored */ @@ -1100,6 +1113,8 @@ static int vgic_v3_domain_init(struct domain *d) register_mmio_handler(d, &vgic_rdistr_mmio_handler, d->arch.vgic.rbase[i], d->arch.vgic.rbase_size[i]); + d->arch.vgic.ctlr = VGICD_CTLR_DEFAULT; + return 0; } -- 2.1.4