[Patch v2 0/6] GSBI CRCI Autoconfiguration Support

[Patch v2 0/6] GSBI CRCI Autoconfiguration Support

[Andy Gross]

This patch set adds support for automatic configuration of GSBI DMA CRCI values.

DMA operations require that the ADM CRCI mux values be properly configured in
the TCSR (Top Control and Status Register) block.  During probing of a GSBI
device, the client mode must be declared and this can be used to lookup the
correct TCSR ADM CRCI MUX settings and then program them so that they are
correct before any clients are populated.

These patches add the TCSR as a syscon device and that allows the GSBI to
access and manipulate the ADM CRCI MUX registers to correctly configure the
values based on the GSBI port configuration.

Changes since v1:
  - Fixed various review comments

Andy Gross (6):
  soc: qcom: gsbi: Add support for ADM CRCI muxing
  mfd: qcom,tcsr: Add device tree binding for TCSR
  ARM: DT: apq8064: Add TCSR support
  ARM: DT: ipq8064: Add TCSR support
  ARM: DT: msm8660: Add TCSR support
  ARM: DT: msm8960: Add TCSR support

 .../devicetree/bindings/mfd/qcom,tcsr.txt          |   22 +++
 .../devicetree/bindings/soc/qcom/qcom,gsbi.txt     |   18 ++-
 arch/arm/boot/dts/qcom-apq8064.dtsi                |   17 +++
 arch/arm/boot/dts/qcom-ipq8064.dtsi                |   17 +++
 arch/arm/boot/dts/qcom-msm8660.dtsi                |   11 ++
 arch/arm/boot/dts/qcom-msm8960.dtsi                |   11 ++
 drivers/soc/qcom/Kconfig                           |    1 +
 drivers/soc/qcom/qcom_gsbi.c                       |  153 ++++++++++++++++++++
 8 files changed, 249 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/mfd/qcom,tcsr.txt

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation

[Patch v2 0/6] GSBI CRCI Autoconfiguration Support

[Andy Gross]

This patch set adds support for automatic configuration of GSBI DMA CRCI values.

DMA operations require that the ADM CRCI mux values be properly configured in
the TCSR (Top Control and Status Register) block.  During probing of a GSBI
device, the client mode must be declared and this can be used to lookup the
correct TCSR ADM CRCI MUX settings and then program them so that they are
correct before any clients are populated.

These patches add the TCSR as a syscon device and that allows the GSBI to
access and manipulate the ADM CRCI MUX registers to correctly configure the
values based on the GSBI port configuration.

Changes since v1:
  - Fixed various review comments

Andy Gross (6):
  soc: qcom: gsbi: Add support for ADM CRCI muxing
  mfd: qcom,tcsr: Add device tree binding for TCSR
  ARM: DT: apq8064: Add TCSR support
  ARM: DT: ipq8064: Add TCSR support
  ARM: DT: msm8660: Add TCSR support
  ARM: DT: msm8960: Add TCSR support

 .../devicetree/bindings/mfd/qcom,tcsr.txt          |   22 +++
 .../devicetree/bindings/soc/qcom/qcom,gsbi.txt     |   18 ++-
 arch/arm/boot/dts/qcom-apq8064.dtsi                |   17 +++
 arch/arm/boot/dts/qcom-ipq8064.dtsi                |   17 +++
 arch/arm/boot/dts/qcom-msm8660.dtsi                |   11 ++
 arch/arm/boot/dts/qcom-msm8960.dtsi                |   11 ++
 drivers/soc/qcom/Kconfig                           |    1 +
 drivers/soc/qcom/qcom_gsbi.c                       |  153 ++++++++++++++++++++
 8 files changed, 249 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/mfd/qcom,tcsr.txt

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation

[Patch v2 1/6] soc: qcom: gsbi: Add support for ADM CRCI muxing

[Andy Gross]

This patch adds automatic configuration for the ADM CRCI muxing required to
support DMA operations for GSBI clients.  The GSBI mode and instance determine
the correct TCSR ADM CRCI MUX value that must be programmed so that the DMA
works properly.

Signed-off-by: Andy Gross <agross@codeaurora.org>
---
 .../devicetree/bindings/soc/qcom/qcom,gsbi.txt     |   18 ++-
 drivers/soc/qcom/Kconfig                           |    1 +
 drivers/soc/qcom/qcom_gsbi.c                       |  153 ++++++++++++++++++++
 3 files changed, 171 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt
index 4ce24d4..8fe7b37 100644
--- a/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt
@@ -6,7 +6,7 @@ configuration settings.  The mode setting will govern the input/output mode of
 the 4 GSBI IOs.
 
 Required properties:
-- compatible: must contain "qcom,gsbi-v1.0.0" for APQ8064/IPQ8064
+- compatible:	Should contain "qcom,gsbi-v1.0.0"
 - reg: Address range for GSBI registers
 - clocks: required clock
 - clock-names: must contain "iface" entry
@@ -16,12 +16,16 @@ Required properties:
 Optional properties:
 - qcom,crci : indicates CRCI MUX value for QUP CRCI ports.  Please reference
   dt-bindings/soc/qcom,gsbi.h for valid CRCI mux values.
+- syscon-tcsr: indicates phandle of TCSR syscon node.  Required if child uses
+  dma.
 
 Required properties if child node exists:
 - #address-cells: Must be 1
 - #size-cells: Must be 1
 - ranges: Must be present
 
+Note: Each GSBI should have an alias correctly numbered in "aliases" node.
+
 Properties for children:
 
 A GSBI controller node can contain 0 or more child nodes representing serial
@@ -37,6 +41,10 @@ Example for APQ8064:
 
 #include <dt-bindings/soc/qcom,gsbi.h>
 
+	aliases {
+		gsbi4 = <&gsbi4>;
+	};
+
 	gsbi4@16300000 {
 		compatible = "qcom,gsbi-v1.0.0";
 		reg = <0x16300000 0x100>;
@@ -48,6 +56,8 @@ Example for APQ8064:
 		qcom,mode = <GSBI_PROT_I2C_UART>;
 		qcom,crci = <GSBI_CRCI_QUP>;
 
+		syscon-tcsr = <&tcsr>;
+
 		/* child nodes go under here */
 
 		i2c_qup4: i2c@16380000 {
@@ -76,3 +86,9 @@ Example for APQ8064:
 		};
 	};
 
+	tcsr: syscon@1a400000 {
+		compatible = "qcom,apq8064-tcsr", "syscon";
+		reg = <0x1a400000 0x100>;
+	};
+
+
diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig
index 7bd2c94..460b2db 100644
--- a/drivers/soc/qcom/Kconfig
+++ b/drivers/soc/qcom/Kconfig
@@ -4,6 +4,7 @@
 config QCOM_GSBI
         tristate "QCOM General Serial Bus Interface"
         depends on ARCH_QCOM
+        select MFD_SYSCON
         help
           Say y here to enable GSBI support.  The GSBI provides control
           functions for connecting the underlying serial UART, SPI, and I2C
diff --git a/drivers/soc/qcom/qcom_gsbi.c b/drivers/soc/qcom/qcom_gsbi.c
index 729425d..2208a3d 100644
--- a/drivers/soc/qcom/qcom_gsbi.c
+++ b/drivers/soc/qcom/qcom_gsbi.c
@@ -18,22 +18,129 @@
 #include <linux/of.h>
 #include <linux/of_platform.h>
 #include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
+#include <dt-bindings/soc/qcom,gsbi.h>
 
 #define GSBI_CTRL_REG		0x0000
 #define GSBI_PROTOCOL_SHIFT	4
+#define MAX_GSBI		12
+
+#define TCSR_ADM_CRCI_BASE	0x70
+
+struct crci_config {
+	u32 num_rows;
+	const u32 (*array)[MAX_GSBI];
+};
+
+static const u32 crci_ipq8064[][MAX_GSBI] = {
+	{
+		0x000003, 0x00000c, 0x000030, 0x0000c0,
+		0x000300, 0x000c00, 0x003000, 0x00c000,
+		0x030000, 0x0c0000, 0x300000, 0xc00000
+	},
+	{
+		0x000003, 0x00000c, 0x000030, 0x0000c0,
+		0x000300, 0x000c00, 0x003000, 0x00c000,
+		0x030000, 0x0c0000, 0x300000, 0xc00000
+	},
+};
+
+static const struct crci_config config_ipq8064 = {
+	.num_rows = ARRAY_SIZE(crci_ipq8064),
+	.array = crci_ipq8064,
+};
+
+static const unsigned int crci_apq8064[][MAX_GSBI] = {
+	{
+		0x001800, 0x006000, 0x000030, 0x0000c0,
+		0x000300, 0x000400, 0x000000, 0x000000,
+		0x000000, 0x000000, 0x000000, 0x000000
+	},
+	{
+		0x000000, 0x000000, 0x000000, 0x000000,
+		0x000000, 0x000020, 0x0000c0, 0x000000,
+		0x000000, 0x000000, 0x000000, 0x000000
+	},
+};
+
+static const struct crci_config config_apq8064 = {
+	.num_rows = ARRAY_SIZE(crci_apq8064),
+	.array = crci_apq8064,
+};
+
+static const unsigned int crci_msm8960[][MAX_GSBI] = {
+	{
+		0x000003, 0x00000c, 0x000030, 0x0000c0,
+		0x000300, 0x000400, 0x000000, 0x000000,
+		0x000000, 0x000000, 0x000000, 0x000000
+	},
+	{
+		0x000000, 0x000000, 0x000000, 0x000000,
+		0x000000, 0x000020, 0x0000c0, 0x000300,
+		0x001800, 0x006000, 0x000000, 0x000000
+	},
+};
+
+static const struct crci_config config_msm8960 = {
+	.num_rows = ARRAY_SIZE(crci_msm8960),
+	.array = crci_msm8960,
+};
+
+static const unsigned int crci_msm8660[][MAX_GSBI] = {
+	{	/* ADM 0 - B */
+		0x000003, 0x00000c, 0x000030, 0x0000c0,
+		0x000300, 0x000c00, 0x003000, 0x00c000,
+		0x030000, 0x0c0000, 0x300000, 0xc00000
+	},
+	{	/* ADM 0 - B */
+		0x000003, 0x00000c, 0x000030, 0x0000c0,
+		0x000300, 0x000c00, 0x003000, 0x00c000,
+		0x030000, 0x0c0000, 0x300000, 0xc00000
+	},
+	{	/* ADM 1 - A */
+		0x000003, 0x00000c, 0x000030, 0x0000c0,
+		0x000300, 0x000c00, 0x003000, 0x00c000,
+		0x030000, 0x0c0000, 0x300000, 0xc00000
+	},
+	{	/* ADM 1 - B */
+		0x000003, 0x00000c, 0x000030, 0x0000c0,
+		0x000300, 0x000c00, 0x003000, 0x00c000,
+		0x030000, 0x0c0000, 0x300000, 0xc00000
+	},
+};
+
+static const struct crci_config config_msm8660 = {
+	.num_rows = ARRAY_SIZE(crci_msm8660),
+	.array = crci_msm8660,
+};
 
 struct gsbi_info {
 	struct clk *hclk;
 	u32 mode;
 	u32 crci;
+	struct regmap *tcsr;
+};
+
+static const struct of_device_id tcsr_dt_match[] = {
+	{ .compatible = "qcom,tcsr-ipq8064", .data = &config_ipq8064},
+	{ .compatible = "qcom,tcsr-apq8064", .data = &config_apq8064},
+	{ .compatible = "qcom,tcsr-msm8960", .data = &config_msm8960},
+	{ .compatible = "qcom,tcsr-msm8660", .data = &config_msm8660},
+	{ },
 };
 
 static int gsbi_probe(struct platform_device *pdev)
 {
 	struct device_node *node = pdev->dev.of_node;
+	struct device_node *tcsr_node;
+	const struct of_device_id *match;
 	struct resource *res;
 	void __iomem *base;
 	struct gsbi_info *gsbi;
+	int i, gsbi_num;
+	u32 mask;
+	const struct crci_config *config = NULL;
 
 	gsbi = devm_kzalloc(&pdev->dev, sizeof(*gsbi), GFP_KERNEL);
 
@@ -45,6 +152,33 @@ static int gsbi_probe(struct platform_device *pdev)
 	if (IS_ERR(base))
 		return PTR_ERR(base);
 
+	/* get the tcsr node and setup the config and regmap */
+	gsbi->tcsr = syscon_regmap_lookup_by_phandle(node, "syscon-tcsr");
+
+	if (!IS_ERR(gsbi->tcsr)) {
+		tcsr_node = of_parse_phandle(node, "syscon-tcsr", 0);
+		if (tcsr_node) {
+			match = of_match_node(tcsr_dt_match, tcsr_node);
+			if (match)
+				config = match->data;
+			else
+				dev_warn(&pdev->dev, "no matching TCSR\n");
+
+			of_node_put(tcsr_node);
+		}
+	}
+
+	gsbi_num = of_alias_get_id(node, "gsbi");
+	if (gsbi_num < 0) {
+		dev_err(&pdev->dev, "missing alias\n");
+		return -EINVAL;
+	}
+
+	if (!gsbi_num || gsbi_num > MAX_GSBI) {
+		dev_err(&pdev->dev, "invalid gsbi number\n");
+		return -EINVAL;
+	}
+
 	if (of_property_read_u32(node, "qcom,mode", &gsbi->mode)) {
 		dev_err(&pdev->dev, "missing mode configuration\n");
 		return -EINVAL;
@@ -64,6 +198,25 @@ static int gsbi_probe(struct platform_device *pdev)
 	writel_relaxed((gsbi->mode << GSBI_PROTOCOL_SHIFT) | gsbi->crci,
 				base + GSBI_CTRL_REG);
 
+	/*
+	 * modify tcsr to reflect mode and ADM CRCI mux
+	 * Each gsbi contains a pair of bits, one for RX and one for TX
+	 * SPI mode requires both bits cleared, otherwise they are set
+	 */
+	if (config) {
+		for (i = 0; i < config->num_rows; i++) {
+			mask = config->array[i][gsbi_num - 1];
+
+			if (gsbi->mode == GSBI_PROT_SPI)
+				regmap_update_bits(gsbi->tcsr,
+					TCSR_ADM_CRCI_BASE + 4 * i, mask, 0);
+			else
+				regmap_update_bits(gsbi->tcsr,
+					TCSR_ADM_CRCI_BASE + 4 * i, mask, mask);
+
+		}
+	}
+
 	/* make sure the gsbi control write is not reordered */
 	wmb();
 
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation

[Patch v2 1/6] soc: qcom: gsbi: Add support for ADM CRCI muxing

[Andy Gross]

This patch adds automatic configuration for the ADM CRCI muxing required to
support DMA operations for GSBI clients.  The GSBI mode and instance determine
the correct TCSR ADM CRCI MUX value that must be programmed so that the DMA
works properly.

Signed-off-by: Andy Gross <agross@codeaurora.org>
---
 .../devicetree/bindings/soc/qcom/qcom,gsbi.txt     |   18 ++-
 drivers/soc/qcom/Kconfig                           |    1 +
 drivers/soc/qcom/qcom_gsbi.c                       |  153 ++++++++++++++++++++
 3 files changed, 171 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt
index 4ce24d4..8fe7b37 100644
--- a/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt
@@ -6,7 +6,7 @@ configuration settings.  The mode setting will govern the input/output mode of
 the 4 GSBI IOs.
 
 Required properties:
-- compatible: must contain "qcom,gsbi-v1.0.0" for APQ8064/IPQ8064
+- compatible:	Should contain "qcom,gsbi-v1.0.0"
 - reg: Address range for GSBI registers
 - clocks: required clock
 - clock-names: must contain "iface" entry
@@ -16,12 +16,16 @@ Required properties:
 Optional properties:
 - qcom,crci : indicates CRCI MUX value for QUP CRCI ports.  Please reference
   dt-bindings/soc/qcom,gsbi.h for valid CRCI mux values.
+- syscon-tcsr: indicates phandle of TCSR syscon node.  Required if child uses
+  dma.
 
 Required properties if child node exists:
 - #address-cells: Must be 1
 - #size-cells: Must be 1
 - ranges: Must be present
 
+Note: Each GSBI should have an alias correctly numbered in "aliases" node.
+
 Properties for children:
 
 A GSBI controller node can contain 0 or more child nodes representing serial
@@ -37,6 +41,10 @@ Example for APQ8064:
 
 #include <dt-bindings/soc/qcom,gsbi.h>
 
+	aliases {
+		gsbi4 = <&gsbi4>;
+	};
+
 	gsbi4@16300000 {
 		compatible = "qcom,gsbi-v1.0.0";
 		reg = <0x16300000 0x100>;
@@ -48,6 +56,8 @@ Example for APQ8064:
 		qcom,mode = <GSBI_PROT_I2C_UART>;
 		qcom,crci = <GSBI_CRCI_QUP>;
 
+		syscon-tcsr = <&tcsr>;
+
 		/* child nodes go under here */
 
 		i2c_qup4: i2c@16380000 {
@@ -76,3 +86,9 @@ Example for APQ8064:
 		};
 	};
 
+	tcsr: syscon@1a400000 {
+		compatible = "qcom,apq8064-tcsr", "syscon";
+		reg = <0x1a400000 0x100>;
+	};
+
+
diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig
index 7bd2c94..460b2db 100644
--- a/drivers/soc/qcom/Kconfig
+++ b/drivers/soc/qcom/Kconfig
@@ -4,6 +4,7 @@
 config QCOM_GSBI
         tristate "QCOM General Serial Bus Interface"
         depends on ARCH_QCOM
+        select MFD_SYSCON
         help
           Say y here to enable GSBI support.  The GSBI provides control
           functions for connecting the underlying serial UART, SPI, and I2C
diff --git a/drivers/soc/qcom/qcom_gsbi.c b/drivers/soc/qcom/qcom_gsbi.c
index 729425d..2208a3d 100644
--- a/drivers/soc/qcom/qcom_gsbi.c
+++ b/drivers/soc/qcom/qcom_gsbi.c
@@ -18,22 +18,129 @@
 #include <linux/of.h>
 #include <linux/of_platform.h>
 #include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
+#include <dt-bindings/soc/qcom,gsbi.h>
 
 #define GSBI_CTRL_REG		0x0000
 #define GSBI_PROTOCOL_SHIFT	4
+#define MAX_GSBI		12
+
+#define TCSR_ADM_CRCI_BASE	0x70
+
+struct crci_config {
+	u32 num_rows;
+	const u32 (*array)[MAX_GSBI];
+};
+
+static const u32 crci_ipq8064[][MAX_GSBI] = {
+	{
+		0x000003, 0x00000c, 0x000030, 0x0000c0,
+		0x000300, 0x000c00, 0x003000, 0x00c000,
+		0x030000, 0x0c0000, 0x300000, 0xc00000
+	},
+	{
+		0x000003, 0x00000c, 0x000030, 0x0000c0,
+		0x000300, 0x000c00, 0x003000, 0x00c000,
+		0x030000, 0x0c0000, 0x300000, 0xc00000
+	},
+};
+
+static const struct crci_config config_ipq8064 = {
+	.num_rows = ARRAY_SIZE(crci_ipq8064),
+	.array = crci_ipq8064,
+};
+
+static const unsigned int crci_apq8064[][MAX_GSBI] = {
+	{
+		0x001800, 0x006000, 0x000030, 0x0000c0,
+		0x000300, 0x000400, 0x000000, 0x000000,
+		0x000000, 0x000000, 0x000000, 0x000000
+	},
+	{
+		0x000000, 0x000000, 0x000000, 0x000000,
+		0x000000, 0x000020, 0x0000c0, 0x000000,
+		0x000000, 0x000000, 0x000000, 0x000000
+	},
+};
+
+static const struct crci_config config_apq8064 = {
+	.num_rows = ARRAY_SIZE(crci_apq8064),
+	.array = crci_apq8064,
+};
+
+static const unsigned int crci_msm8960[][MAX_GSBI] = {
+	{
+		0x000003, 0x00000c, 0x000030, 0x0000c0,
+		0x000300, 0x000400, 0x000000, 0x000000,
+		0x000000, 0x000000, 0x000000, 0x000000
+	},
+	{
+		0x000000, 0x000000, 0x000000, 0x000000,
+		0x000000, 0x000020, 0x0000c0, 0x000300,
+		0x001800, 0x006000, 0x000000, 0x000000
+	},
+};
+
+static const struct crci_config config_msm8960 = {
+	.num_rows = ARRAY_SIZE(crci_msm8960),
+	.array = crci_msm8960,
+};
+
+static const unsigned int crci_msm8660[][MAX_GSBI] = {
+	{	/* ADM 0 - B */
+		0x000003, 0x00000c, 0x000030, 0x0000c0,
+		0x000300, 0x000c00, 0x003000, 0x00c000,
+		0x030000, 0x0c0000, 0x300000, 0xc00000
+	},
+	{	/* ADM 0 - B */
+		0x000003, 0x00000c, 0x000030, 0x0000c0,
+		0x000300, 0x000c00, 0x003000, 0x00c000,
+		0x030000, 0x0c0000, 0x300000, 0xc00000
+	},
+	{	/* ADM 1 - A */
+		0x000003, 0x00000c, 0x000030, 0x0000c0,
+		0x000300, 0x000c00, 0x003000, 0x00c000,
+		0x030000, 0x0c0000, 0x300000, 0xc00000
+	},
+	{	/* ADM 1 - B */
+		0x000003, 0x00000c, 0x000030, 0x0000c0,
+		0x000300, 0x000c00, 0x003000, 0x00c000,
+		0x030000, 0x0c0000, 0x300000, 0xc00000
+	},
+};
+
+static const struct crci_config config_msm8660 = {
+	.num_rows = ARRAY_SIZE(crci_msm8660),
+	.array = crci_msm8660,
+};
 
 struct gsbi_info {
 	struct clk *hclk;
 	u32 mode;
 	u32 crci;
+	struct regmap *tcsr;
+};
+
+static const struct of_device_id tcsr_dt_match[] = {
+	{ .compatible = "qcom,tcsr-ipq8064", .data = &config_ipq8064},
+	{ .compatible = "qcom,tcsr-apq8064", .data = &config_apq8064},
+	{ .compatible = "qcom,tcsr-msm8960", .data = &config_msm8960},
+	{ .compatible = "qcom,tcsr-msm8660", .data = &config_msm8660},
+	{ },
 };
 
 static int gsbi_probe(struct platform_device *pdev)
 {
 	struct device_node *node = pdev->dev.of_node;
+	struct device_node *tcsr_node;
+	const struct of_device_id *match;
 	struct resource *res;
 	void __iomem *base;
 	struct gsbi_info *gsbi;
+	int i, gsbi_num;
+	u32 mask;
+	const struct crci_config *config = NULL;
 
 	gsbi = devm_kzalloc(&pdev->dev, sizeof(*gsbi), GFP_KERNEL);
 
@@ -45,6 +152,33 @@ static int gsbi_probe(struct platform_device *pdev)
 	if (IS_ERR(base))
 		return PTR_ERR(base);
 
+	/* get the tcsr node and setup the config and regmap */
+	gsbi->tcsr = syscon_regmap_lookup_by_phandle(node, "syscon-tcsr");
+
+	if (!IS_ERR(gsbi->tcsr)) {
+		tcsr_node = of_parse_phandle(node, "syscon-tcsr", 0);
+		if (tcsr_node) {
+			match = of_match_node(tcsr_dt_match, tcsr_node);
+			if (match)
+				config = match->data;
+			else
+				dev_warn(&pdev->dev, "no matching TCSR\n");
+
+			of_node_put(tcsr_node);
+		}
+	}
+
+	gsbi_num = of_alias_get_id(node, "gsbi");
+	if (gsbi_num < 0) {
+		dev_err(&pdev->dev, "missing alias\n");
+		return -EINVAL;
+	}
+
+	if (!gsbi_num || gsbi_num > MAX_GSBI) {
+		dev_err(&pdev->dev, "invalid gsbi number\n");
+		return -EINVAL;
+	}
+
 	if (of_property_read_u32(node, "qcom,mode", &gsbi->mode)) {
 		dev_err(&pdev->dev, "missing mode configuration\n");
 		return -EINVAL;
@@ -64,6 +198,25 @@ static int gsbi_probe(struct platform_device *pdev)
 	writel_relaxed((gsbi->mode << GSBI_PROTOCOL_SHIFT) | gsbi->crci,
 				base + GSBI_CTRL_REG);
 
+	/*
+	 * modify tcsr to reflect mode and ADM CRCI mux
+	 * Each gsbi contains a pair of bits, one for RX and one for TX
+	 * SPI mode requires both bits cleared, otherwise they are set
+	 */
+	if (config) {
+		for (i = 0; i < config->num_rows; i++) {
+			mask = config->array[i][gsbi_num - 1];
+
+			if (gsbi->mode == GSBI_PROT_SPI)
+				regmap_update_bits(gsbi->tcsr,
+					TCSR_ADM_CRCI_BASE + 4 * i, mask, 0);
+			else
+				regmap_update_bits(gsbi->tcsr,
+					TCSR_ADM_CRCI_BASE + 4 * i, mask, mask);
+
+		}
+	}
+
 	/* make sure the gsbi control write is not reordered */
 	wmb();
 
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation

[Patch v2 1/6] soc: qcom: gsbi: Add support for ADM CRCI muxing

[Andy Gross]

This patch adds automatic configuration for the ADM CRCI muxing required to
support DMA operations for GSBI clients.  The GSBI mode and instance determine
the correct TCSR ADM CRCI MUX value that must be programmed so that the DMA
works properly.

Signed-off-by: Andy Gross <agross@codeaurora.org>
---
 .../devicetree/bindings/soc/qcom/qcom,gsbi.txt     |   18 ++-
 drivers/soc/qcom/Kconfig                           |    1 +
 drivers/soc/qcom/qcom_gsbi.c                       |  153 ++++++++++++++++++++
 3 files changed, 171 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt
index 4ce24d4..8fe7b37 100644
--- a/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt
@@ -6,7 +6,7 @@ configuration settings.  The mode setting will govern the input/output mode of
 the 4 GSBI IOs.
 
 Required properties:
-- compatible: must contain "qcom,gsbi-v1.0.0" for APQ8064/IPQ8064
+- compatible:	Should contain "qcom,gsbi-v1.0.0"
 - reg: Address range for GSBI registers
 - clocks: required clock
 - clock-names: must contain "iface" entry
@@ -16,12 +16,16 @@ Required properties:
 Optional properties:
 - qcom,crci : indicates CRCI MUX value for QUP CRCI ports.  Please reference
   dt-bindings/soc/qcom,gsbi.h for valid CRCI mux values.
+- syscon-tcsr: indicates phandle of TCSR syscon node.  Required if child uses
+  dma.
 
 Required properties if child node exists:
 - #address-cells: Must be 1
 - #size-cells: Must be 1
 - ranges: Must be present
 
+Note: Each GSBI should have an alias correctly numbered in "aliases" node.
+
 Properties for children:
 
 A GSBI controller node can contain 0 or more child nodes representing serial
@@ -37,6 +41,10 @@ Example for APQ8064:
 
 #include <dt-bindings/soc/qcom,gsbi.h>
 
+	aliases {
+		gsbi4 = <&gsbi4>;
+	};
+
 	gsbi4 at 16300000 {
 		compatible = "qcom,gsbi-v1.0.0";
 		reg = <0x16300000 0x100>;
@@ -48,6 +56,8 @@ Example for APQ8064:
 		qcom,mode = <GSBI_PROT_I2C_UART>;
 		qcom,crci = <GSBI_CRCI_QUP>;
 
+		syscon-tcsr = <&tcsr>;
+
 		/* child nodes go under here */
 
 		i2c_qup4: i2c at 16380000 {
@@ -76,3 +86,9 @@ Example for APQ8064:
 		};
 	};
 
+	tcsr: syscon at 1a400000 {
+		compatible = "qcom,apq8064-tcsr", "syscon";
+		reg = <0x1a400000 0x100>;
+	};
+
+
diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig
index 7bd2c94..460b2db 100644
--- a/drivers/soc/qcom/Kconfig
+++ b/drivers/soc/qcom/Kconfig
@@ -4,6 +4,7 @@
 config QCOM_GSBI
         tristate "QCOM General Serial Bus Interface"
         depends on ARCH_QCOM
+        select MFD_SYSCON
         help
           Say y here to enable GSBI support.  The GSBI provides control
           functions for connecting the underlying serial UART, SPI, and I2C
diff --git a/drivers/soc/qcom/qcom_gsbi.c b/drivers/soc/qcom/qcom_gsbi.c
index 729425d..2208a3d 100644
--- a/drivers/soc/qcom/qcom_gsbi.c
+++ b/drivers/soc/qcom/qcom_gsbi.c
@@ -18,22 +18,129 @@
 #include <linux/of.h>
 #include <linux/of_platform.h>
 #include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
+#include <dt-bindings/soc/qcom,gsbi.h>
 
 #define GSBI_CTRL_REG		0x0000
 #define GSBI_PROTOCOL_SHIFT	4
+#define MAX_GSBI		12
+
+#define TCSR_ADM_CRCI_BASE	0x70
+
+struct crci_config {
+	u32 num_rows;
+	const u32 (*array)[MAX_GSBI];
+};
+
+static const u32 crci_ipq8064[][MAX_GSBI] = {
+	{
+		0x000003, 0x00000c, 0x000030, 0x0000c0,
+		0x000300, 0x000c00, 0x003000, 0x00c000,
+		0x030000, 0x0c0000, 0x300000, 0xc00000
+	},
+	{
+		0x000003, 0x00000c, 0x000030, 0x0000c0,
+		0x000300, 0x000c00, 0x003000, 0x00c000,
+		0x030000, 0x0c0000, 0x300000, 0xc00000
+	},
+};
+
+static const struct crci_config config_ipq8064 = {
+	.num_rows = ARRAY_SIZE(crci_ipq8064),
+	.array = crci_ipq8064,
+};
+
+static const unsigned int crci_apq8064[][MAX_GSBI] = {
+	{
+		0x001800, 0x006000, 0x000030, 0x0000c0,
+		0x000300, 0x000400, 0x000000, 0x000000,
+		0x000000, 0x000000, 0x000000, 0x000000
+	},
+	{
+		0x000000, 0x000000, 0x000000, 0x000000,
+		0x000000, 0x000020, 0x0000c0, 0x000000,
+		0x000000, 0x000000, 0x000000, 0x000000
+	},
+};
+
+static const struct crci_config config_apq8064 = {
+	.num_rows = ARRAY_SIZE(crci_apq8064),
+	.array = crci_apq8064,
+};
+
+static const unsigned int crci_msm8960[][MAX_GSBI] = {
+	{
+		0x000003, 0x00000c, 0x000030, 0x0000c0,
+		0x000300, 0x000400, 0x000000, 0x000000,
+		0x000000, 0x000000, 0x000000, 0x000000
+	},
+	{
+		0x000000, 0x000000, 0x000000, 0x000000,
+		0x000000, 0x000020, 0x0000c0, 0x000300,
+		0x001800, 0x006000, 0x000000, 0x000000
+	},
+};
+
+static const struct crci_config config_msm8960 = {
+	.num_rows = ARRAY_SIZE(crci_msm8960),
+	.array = crci_msm8960,
+};
+
+static const unsigned int crci_msm8660[][MAX_GSBI] = {
+	{	/* ADM 0 - B */
+		0x000003, 0x00000c, 0x000030, 0x0000c0,
+		0x000300, 0x000c00, 0x003000, 0x00c000,
+		0x030000, 0x0c0000, 0x300000, 0xc00000
+	},
+	{	/* ADM 0 - B */
+		0x000003, 0x00000c, 0x000030, 0x0000c0,
+		0x000300, 0x000c00, 0x003000, 0x00c000,
+		0x030000, 0x0c0000, 0x300000, 0xc00000
+	},
+	{	/* ADM 1 - A */
+		0x000003, 0x00000c, 0x000030, 0x0000c0,
+		0x000300, 0x000c00, 0x003000, 0x00c000,
+		0x030000, 0x0c0000, 0x300000, 0xc00000
+	},
+	{	/* ADM 1 - B */
+		0x000003, 0x00000c, 0x000030, 0x0000c0,
+		0x000300, 0x000c00, 0x003000, 0x00c000,
+		0x030000, 0x0c0000, 0x300000, 0xc00000
+	},
+};
+
+static const struct crci_config config_msm8660 = {
+	.num_rows = ARRAY_SIZE(crci_msm8660),
+	.array = crci_msm8660,
+};
 
 struct gsbi_info {
 	struct clk *hclk;
 	u32 mode;
 	u32 crci;
+	struct regmap *tcsr;
+};
+
+static const struct of_device_id tcsr_dt_match[] = {
+	{ .compatible = "qcom,tcsr-ipq8064", .data = &config_ipq8064},
+	{ .compatible = "qcom,tcsr-apq8064", .data = &config_apq8064},
+	{ .compatible = "qcom,tcsr-msm8960", .data = &config_msm8960},
+	{ .compatible = "qcom,tcsr-msm8660", .data = &config_msm8660},
+	{ },
 };
 
 static int gsbi_probe(struct platform_device *pdev)
 {
 	struct device_node *node = pdev->dev.of_node;
+	struct device_node *tcsr_node;
+	const struct of_device_id *match;
 	struct resource *res;
 	void __iomem *base;
 	struct gsbi_info *gsbi;
+	int i, gsbi_num;
+	u32 mask;
+	const struct crci_config *config = NULL;
 
 	gsbi = devm_kzalloc(&pdev->dev, sizeof(*gsbi), GFP_KERNEL);
 
@@ -45,6 +152,33 @@ static int gsbi_probe(struct platform_device *pdev)
 	if (IS_ERR(base))
 		return PTR_ERR(base);
 
+	/* get the tcsr node and setup the config and regmap */
+	gsbi->tcsr = syscon_regmap_lookup_by_phandle(node, "syscon-tcsr");
+
+	if (!IS_ERR(gsbi->tcsr)) {
+		tcsr_node = of_parse_phandle(node, "syscon-tcsr", 0);
+		if (tcsr_node) {
+			match = of_match_node(tcsr_dt_match, tcsr_node);
+			if (match)
+				config = match->data;
+			else
+				dev_warn(&pdev->dev, "no matching TCSR\n");
+
+			of_node_put(tcsr_node);
+		}
+	}
+
+	gsbi_num = of_alias_get_id(node, "gsbi");
+	if (gsbi_num < 0) {
+		dev_err(&pdev->dev, "missing alias\n");
+		return -EINVAL;
+	}
+
+	if (!gsbi_num || gsbi_num > MAX_GSBI) {
+		dev_err(&pdev->dev, "invalid gsbi number\n");
+		return -EINVAL;
+	}
+
 	if (of_property_read_u32(node, "qcom,mode", &gsbi->mode)) {
 		dev_err(&pdev->dev, "missing mode configuration\n");
 		return -EINVAL;
@@ -64,6 +198,25 @@ static int gsbi_probe(struct platform_device *pdev)
 	writel_relaxed((gsbi->mode << GSBI_PROTOCOL_SHIFT) | gsbi->crci,
 				base + GSBI_CTRL_REG);
 
+	/*
+	 * modify tcsr to reflect mode and ADM CRCI mux
+	 * Each gsbi contains a pair of bits, one for RX and one for TX
+	 * SPI mode requires both bits cleared, otherwise they are set
+	 */
+	if (config) {
+		for (i = 0; i < config->num_rows; i++) {
+			mask = config->array[i][gsbi_num - 1];
+
+			if (gsbi->mode == GSBI_PROT_SPI)
+				regmap_update_bits(gsbi->tcsr,
+					TCSR_ADM_CRCI_BASE + 4 * i, mask, 0);
+			else
+				regmap_update_bits(gsbi->tcsr,
+					TCSR_ADM_CRCI_BASE + 4 * i, mask, mask);
+
+		}
+	}
+
 	/* make sure the gsbi control write is not reordered */
 	wmb();
 
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation

[Patch v2 2/6] mfd: qcom,tcsr: Add device tree binding for TCSR

[Andy Gross]

This patch adds the device tree binding for the Qualcomm Top Control and
Status Register device.  The TCSR is comprised of a set of registers that
provide various control and status functions for attached peripherals.

Signed-off-by: Andy Gross <agross@codeaurora.org>
---
 .../devicetree/bindings/mfd/qcom,tcsr.txt          |   22 ++++++++++++++++++++
 1 file changed, 22 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mfd/qcom,tcsr.txt

diff --git a/Documentation/devicetree/bindings/mfd/qcom,tcsr.txt b/Documentation/devicetree/bindings/mfd/qcom,tcsr.txt
new file mode 100644
index 0000000..e90519d
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/qcom,tcsr.txt
@@ -0,0 +1,22 @@
+QCOM Top Control and Status Register
+
+Qualcomm devices have a set of registers that provide various control and status
+functions for their peripherals.  This node is intended to allow access to these
+registers via syscon.
+
+Required properties:
+- compatible:	Should contain:
+		"qcom,tcsr-ipq8064", "syscon" for IPQ8064
+		"qcom,tcsr-apq8064", "syscon" for APQ8064
+		"qcom,tcsr-msm8660", "syscon" for MSM8660
+		"qcom,tcsr-msm8960", "syscon" for MSM8960
+		"qcom,tcsr-msm8974", "syscon" for MSM8974
+		"qcom,tcsr-apq8084", "syscon" for APQ8084
+		"qcom,tcsr-msm8916", "syscon" for MSM8916
+- reg: Address range for TCSR registers
+
+Example:
+	tcsr: syscon@1a400000 {
+		compatible = "qcom,tcsr-msm8960", "syscon";
+		reg = <0x1a400000 0x100>;
+	};
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation

[Patch v2 2/6] mfd: qcom,tcsr: Add device tree binding for TCSR

[Andy Gross]

This patch adds the device tree binding for the Qualcomm Top Control and
Status Register device.  The TCSR is comprised of a set of registers that
provide various control and status functions for attached peripherals.

Signed-off-by: Andy Gross <agross@codeaurora.org>
---
 .../devicetree/bindings/mfd/qcom,tcsr.txt          |   22 ++++++++++++++++++++
 1 file changed, 22 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mfd/qcom,tcsr.txt

diff --git a/Documentation/devicetree/bindings/mfd/qcom,tcsr.txt b/Documentation/devicetree/bindings/mfd/qcom,tcsr.txt
new file mode 100644
index 0000000..e90519d
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/qcom,tcsr.txt
@@ -0,0 +1,22 @@
+QCOM Top Control and Status Register
+
+Qualcomm devices have a set of registers that provide various control and status
+functions for their peripherals.  This node is intended to allow access to these
+registers via syscon.
+
+Required properties:
+- compatible:	Should contain:
+		"qcom,tcsr-ipq8064", "syscon" for IPQ8064
+		"qcom,tcsr-apq8064", "syscon" for APQ8064
+		"qcom,tcsr-msm8660", "syscon" for MSM8660
+		"qcom,tcsr-msm8960", "syscon" for MSM8960
+		"qcom,tcsr-msm8974", "syscon" for MSM8974
+		"qcom,tcsr-apq8084", "syscon" for APQ8084
+		"qcom,tcsr-msm8916", "syscon" for MSM8916
+- reg: Address range for TCSR registers
+
+Example:
+	tcsr: syscon@1a400000 {
+		compatible = "qcom,tcsr-msm8960", "syscon";
+		reg = <0x1a400000 0x100>;
+	};
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation

[Patch v2 2/6] mfd: qcom,tcsr: Add device tree binding for TCSR

[Andy Gross]

This patch adds the device tree binding for the Qualcomm Top Control and
Status Register device.  The TCSR is comprised of a set of registers that
provide various control and status functions for attached peripherals.

Signed-off-by: Andy Gross <agross@codeaurora.org>
---
 .../devicetree/bindings/mfd/qcom,tcsr.txt          |   22 ++++++++++++++++++++
 1 file changed, 22 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mfd/qcom,tcsr.txt

diff --git a/Documentation/devicetree/bindings/mfd/qcom,tcsr.txt b/Documentation/devicetree/bindings/mfd/qcom,tcsr.txt
new file mode 100644
index 0000000..e90519d
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/qcom,tcsr.txt
@@ -0,0 +1,22 @@
+QCOM Top Control and Status Register
+
+Qualcomm devices have a set of registers that provide various control and status
+functions for their peripherals.  This node is intended to allow access to these
+registers via syscon.
+
+Required properties:
+- compatible:	Should contain:
+		"qcom,tcsr-ipq8064", "syscon" for IPQ8064
+		"qcom,tcsr-apq8064", "syscon" for APQ8064
+		"qcom,tcsr-msm8660", "syscon" for MSM8660
+		"qcom,tcsr-msm8960", "syscon" for MSM8960
+		"qcom,tcsr-msm8974", "syscon" for MSM8974
+		"qcom,tcsr-apq8084", "syscon" for APQ8084
+		"qcom,tcsr-msm8916", "syscon" for MSM8916
+- reg: Address range for TCSR registers
+
+Example:
+	tcsr: syscon at 1a400000 {
+		compatible = "qcom,tcsr-msm8960", "syscon";
+		reg = <0x1a400000 0x100>;
+	};
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation

[Patch v2 3/6] ARM: DT: apq8064: Add TCSR support

[Andy Gross]

This patch adds TCSR support for use by the GSBI to automatically configure ADM
CRCI values based on the GSBI port configuration.

Signed-off-by: Andy Gross <agross@codeaurora.org>
---
 arch/arm/boot/dts/qcom-apq8064.dtsi |   17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index b3154c0..720fa2e 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -11,6 +11,12 @@
 	compatible = "qcom,apq8064";
 	interrupt-parent = <&intc>;
 
+	aliases {
+		gsbi1 = &gsbi1;
+		gsbi2 = &gsbi2;
+		gsbi7 = &gsbi7;
+	};
+
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -173,6 +179,8 @@
 			#size-cells = <1>;
 			ranges;
 
+			syscon-tcsr = <&tcsr>;
+
 			i2c1: i2c@12460000 {
 				compatible = "qcom,i2c-qup-v1.1.1";
 				reg = <0x12460000 0x1000>;
@@ -194,6 +202,8 @@
 			#size-cells = <1>;
 			ranges;
 
+			syscon-tcsr = <&tcsr>;
+
 			i2c2: i2c@124a0000 {
 				compatible = "qcom,i2c-qup-v1.1.1";
 				reg = <0x124a0000 0x1000>;
@@ -215,6 +225,8 @@
 			#size-cells = <1>;
 			ranges;
 
+			syscon-tcsr = <&tcsr>;
+
 			serial@16640000 {
 				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 				reg = <0x16640000 0x1000>,
@@ -349,5 +361,10 @@
 				pinctrl-0 = <&sdc4_gpios>;
 			};
 		};
+
+		tcsr: syscon@1a400000 {
+			compatible = "qcom,tcsr-apq8064", "syscon";
+			reg = <0x1a400000 0x100>;
+		};
 	};
 };
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation

[Patch v2 3/6] ARM: DT: apq8064: Add TCSR support

[Andy Gross]

This patch adds TCSR support for use by the GSBI to automatically configure ADM
CRCI values based on the GSBI port configuration.

Signed-off-by: Andy Gross <agross@codeaurora.org>
---
 arch/arm/boot/dts/qcom-apq8064.dtsi |   17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index b3154c0..720fa2e 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -11,6 +11,12 @@
 	compatible = "qcom,apq8064";
 	interrupt-parent = <&intc>;
 
+	aliases {
+		gsbi1 = &gsbi1;
+		gsbi2 = &gsbi2;
+		gsbi7 = &gsbi7;
+	};
+
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -173,6 +179,8 @@
 			#size-cells = <1>;
 			ranges;
 
+			syscon-tcsr = <&tcsr>;
+
 			i2c1: i2c at 12460000 {
 				compatible = "qcom,i2c-qup-v1.1.1";
 				reg = <0x12460000 0x1000>;
@@ -194,6 +202,8 @@
 			#size-cells = <1>;
 			ranges;
 
+			syscon-tcsr = <&tcsr>;
+
 			i2c2: i2c at 124a0000 {
 				compatible = "qcom,i2c-qup-v1.1.1";
 				reg = <0x124a0000 0x1000>;
@@ -215,6 +225,8 @@
 			#size-cells = <1>;
 			ranges;
 
+			syscon-tcsr = <&tcsr>;
+
 			serial at 16640000 {
 				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 				reg = <0x16640000 0x1000>,
@@ -349,5 +361,10 @@
 				pinctrl-0 = <&sdc4_gpios>;
 			};
 		};
+
+		tcsr: syscon at 1a400000 {
+			compatible = "qcom,tcsr-apq8064", "syscon";
+			reg = <0x1a400000 0x100>;
+		};
 	};
 };
-- 
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hosted by The Linux Foundation

[Patch v2 4/6] ARM: DT: ipq8064: Add TCSR support

[Andy Gross]

This patch adds TCSR support for use by the GSBI to automatically configure ADM
CRCI values based on the GSBI port configuration.

Signed-off-by: Andy Gross <agross@codeaurora.org>
---
 arch/arm/boot/dts/qcom-ipq8064.dtsi |   17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 63b2146..8939d31 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -9,6 +9,12 @@
 	compatible = "qcom,ipq8064";
 	interrupt-parent = <&intc>;
 
+	aliases {
+		gsbi2 = &gsbi2;
+		gsbi4 = &gsbi4;
+		gsbi5 = &gsbi5;
+	};
+
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -128,6 +134,8 @@
 			ranges;
 			status = "disabled";
 
+			syscon-tcsr = <&tcsr>;
+
 			serial@12490000 {
 				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 				reg = <0x12490000 0x1000>,
@@ -163,6 +171,8 @@
 			ranges;
 			status = "disabled";
 
+			syscon-tcsr = <&tcsr>;
+
 			serial@16340000 {
 				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 				reg = <0x16340000 0x1000>,
@@ -197,6 +207,8 @@
 			ranges;
 			status = "disabled";
 
+			syscon-tcsr = <&tcsr>;
+
 			serial@1a240000 {
 				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 				reg = <0x1a240000 0x1000>,
@@ -279,5 +291,10 @@
 			#clock-cells = <1>;
 			#reset-cells = <1>;
 		};
+
+		tcsr: syscon@1a400000 {
+			compatible = "qcom,tcsr-ipq8064", "syscon";
+			reg = <0x1a400000 0x100>;
+		};
 	};
 };
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation

[Patch v2 4/6] ARM: DT: ipq8064: Add TCSR support

[Andy Gross]

This patch adds TCSR support for use by the GSBI to automatically configure ADM
CRCI values based on the GSBI port configuration.

Signed-off-by: Andy Gross <agross@codeaurora.org>
---
 arch/arm/boot/dts/qcom-ipq8064.dtsi |   17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 63b2146..8939d31 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -9,6 +9,12 @@
 	compatible = "qcom,ipq8064";
 	interrupt-parent = <&intc>;
 
+	aliases {
+		gsbi2 = &gsbi2;
+		gsbi4 = &gsbi4;
+		gsbi5 = &gsbi5;
+	};
+
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -128,6 +134,8 @@
 			ranges;
 			status = "disabled";
 
+			syscon-tcsr = <&tcsr>;
+
 			serial at 12490000 {
 				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 				reg = <0x12490000 0x1000>,
@@ -163,6 +171,8 @@
 			ranges;
 			status = "disabled";
 
+			syscon-tcsr = <&tcsr>;
+
 			serial at 16340000 {
 				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 				reg = <0x16340000 0x1000>,
@@ -197,6 +207,8 @@
 			ranges;
 			status = "disabled";
 
+			syscon-tcsr = <&tcsr>;
+
 			serial at 1a240000 {
 				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 				reg = <0x1a240000 0x1000>,
@@ -279,5 +291,10 @@
 			#clock-cells = <1>;
 			#reset-cells = <1>;
 		};
+
+		tcsr: syscon at 1a400000 {
+			compatible = "qcom,tcsr-ipq8064", "syscon";
+			reg = <0x1a400000 0x100>;
+		};
 	};
 };
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation

[Patch v2 5/6] ARM: DT: msm8660: Add TCSR support

[Andy Gross]

This patch adds TCSR support for use by the GSBI to automatically configure ADM
CRCI values based on the GSBI port configuration.

Signed-off-by: Andy Gross <agross@codeaurora.org>
---
 arch/arm/boot/dts/qcom-msm8660.dtsi |   11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi
index 0affd61..0a41fd3 100644
--- a/arch/arm/boot/dts/qcom-msm8660.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8660.dtsi
@@ -11,6 +11,10 @@
 	compatible = "qcom,msm8660";
 	interrupt-parent = <&intc>;
 
+	aliases {
+		gsbi12 = &gsbi12;
+	};
+
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -89,6 +93,8 @@
 			#size-cells = <1>;
 			ranges;
 
+			syscon-tcsr = <&tcsr>;
+
 			serial@19c40000 {
 				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 				reg = <0x19c40000 0x1000>,
@@ -196,6 +202,11 @@
 				vmmc-supply = <&vsdcc_fixed>;
 			};
 		};
+
+		tcsr: syscon@1a400000 {
+			compatible = "qcom,tcsr-msm8660", "syscon";
+			reg = <0x1a400000 0x100>;
+		};
 	};
 
 };
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation

[Patch v2 5/6] ARM: DT: msm8660: Add TCSR support

[Andy Gross]

This patch adds TCSR support for use by the GSBI to automatically configure ADM
CRCI values based on the GSBI port configuration.

Signed-off-by: Andy Gross <agross@codeaurora.org>
---
 arch/arm/boot/dts/qcom-msm8660.dtsi |   11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi
index 0affd61..0a41fd3 100644
--- a/arch/arm/boot/dts/qcom-msm8660.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8660.dtsi
@@ -11,6 +11,10 @@
 	compatible = "qcom,msm8660";
 	interrupt-parent = <&intc>;
 
+	aliases {
+		gsbi12 = &gsbi12;
+	};
+
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -89,6 +93,8 @@
 			#size-cells = <1>;
 			ranges;
 
+			syscon-tcsr = <&tcsr>;
+
 			serial at 19c40000 {
 				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 				reg = <0x19c40000 0x1000>,
@@ -196,6 +202,11 @@
 				vmmc-supply = <&vsdcc_fixed>;
 			};
 		};
+
+		tcsr: syscon at 1a400000 {
+			compatible = "qcom,tcsr-msm8660", "syscon";
+			reg = <0x1a400000 0x100>;
+		};
 	};
 
 };
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation

[Patch v2 6/6] ARM: DT: msm8960: Add TCSR support

[Andy Gross]

This patch adds TCSR support for use by the GSBI to automatically configure ADM
CRCI values based on the GSBI port configuration.

Signed-off-by: Andy Gross <agross@codeaurora.org>
---
 arch/arm/boot/dts/qcom-msm8960.dtsi |   11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi
index e1b0d5c..078b4fb 100644
--- a/arch/arm/boot/dts/qcom-msm8960.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8960.dtsi
@@ -11,6 +11,10 @@
 	compatible = "qcom,msm8960";
 	interrupt-parent = <&intc>;
 
+	aliases {
+		gsbi5 = &gsbi5;
+	};
+
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -129,6 +133,8 @@
 			#size-cells = <1>;
 			ranges;
 
+			syscon-tcsr = <&tcsr>;
+
 			serial@16440000 {
 				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 				reg = <0x16440000 0x1000>,
@@ -238,5 +244,10 @@
 				vmmc-supply = <&vsdcc_fixed>;
 			};
 		};
+
+		tcsr: syscon@1a400000 {
+			compatible = "qcom,tcsr-msm8960", "syscon";
+			reg = <0x1a400000 0x100>;
+		};
 	};
 };
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation

[Patch v2 6/6] ARM: DT: msm8960: Add TCSR support

[Andy Gross]

This patch adds TCSR support for use by the GSBI to automatically configure ADM
CRCI values based on the GSBI port configuration.

Signed-off-by: Andy Gross <agross@codeaurora.org>
---
 arch/arm/boot/dts/qcom-msm8960.dtsi |   11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi
index e1b0d5c..078b4fb 100644
--- a/arch/arm/boot/dts/qcom-msm8960.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8960.dtsi
@@ -11,6 +11,10 @@
 	compatible = "qcom,msm8960";
 	interrupt-parent = <&intc>;
 
+	aliases {
+		gsbi5 = &gsbi5;
+	};
+
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -129,6 +133,8 @@
 			#size-cells = <1>;
 			ranges;
 
+			syscon-tcsr = <&tcsr>;
+
 			serial at 16440000 {
 				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 				reg = <0x16440000 0x1000>,
@@ -238,5 +244,10 @@
 				vmmc-supply = <&vsdcc_fixed>;
 			};
 		};
+
+		tcsr: syscon at 1a400000 {
+			compatible = "qcom,tcsr-msm8960", "syscon";
+			reg = <0x1a400000 0x100>;
+		};
 	};
 };
-- 
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hosted by The Linux Foundation

Re: [Patch v2 1/6] soc: qcom: gsbi: Add support for ADM CRCI muxing

[Kumar Gala]

On Jan 30, 2015, at 12:25 AM, Andy Gross <agross@codeaurora.org> wrote:

> This patch adds automatic configuration for the ADM CRCI muxing required to
> support DMA operations for GSBI clients.  The GSBI mode and instance determine
> the correct TCSR ADM CRCI MUX value that must be programmed so that the DMA
> works properly.
> 
> Signed-off-by: Andy Gross <agross@codeaurora.org>
> ---
> .../devicetree/bindings/soc/qcom/qcom,gsbi.txt     |   18 ++-
> drivers/soc/qcom/Kconfig                           |    1 +
> drivers/soc/qcom/qcom_gsbi.c                       |  153 ++++++++++++++++++++
> 3 files changed, 171 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt
> index 4ce24d4..8fe7b37 100644
> --- a/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt
> +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt
> @@ -6,7 +6,7 @@ configuration settings.  The mode setting will govern the input/output mode of
> the 4 GSBI IOs.
> 
> Required properties:
> -- compatible: must contain "qcom,gsbi-v1.0.0" for APQ8064/IPQ8064
> +- compatible:	Should contain "qcom,gsbi-v1.0.0"
> - reg: Address range for GSBI registers
> - clocks: required clock
> - clock-names: must contain "iface" entry
> @@ -16,12 +16,16 @@ Required properties:
> Optional properties:
> - qcom,crci : indicates CRCI MUX value for QUP CRCI ports.  Please reference
>   dt-bindings/soc/qcom,gsbi.h for valid CRCI mux values.
> +- syscon-tcsr: indicates phandle of TCSR syscon node.  Required if child uses
> +  dma.
> 
> Required properties if child node exists:
> - #address-cells: Must be 1
> - #size-cells: Must be 1
> - ranges: Must be present
> 
> +Note: Each GSBI should have an alias correctly numbered in "aliases" node.
> +
> Properties for children:
> 
> A GSBI controller node can contain 0 or more child nodes representing serial
> @@ -37,6 +41,10 @@ Example for APQ8064:
> 
> #include <dt-bindings/soc/qcom,gsbi.h>
> 
> +	aliases {
> +		gsbi4 = <&gsbi4>;
> +	};

You appear to be using the alias name to determine a index number for the gsbi, if that is the case, than you should probably just add a cell-index node to the gsbi’s for this purpose.

> +
> 	gsbi4@16300000 {
> 		compatible = "qcom,gsbi-v1.0.0";
> 		reg = <0x16300000 0x100>;
> @@ -48,6 +56,8 @@ Example for APQ8064:
> 		qcom,mode = <GSBI_PROT_I2C_UART>;
> 		qcom,crci = <GSBI_CRCI_QUP>;
> 
> +		syscon-tcsr = <&tcsr>;
> +
> 		/* child nodes go under here */
> 
> 		i2c_qup4: i2c@16380000 {
> @@ -76,3 +86,9 @@ Example for APQ8064:
> 		};
> 	};
> 
> +	tcsr: syscon@1a400000 {
> +		compatible = "qcom,apq8064-tcsr", "syscon";
> +		reg = <0x1a400000 0x100>;
> +	};
> +
> +

- k

-- 
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The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[Patch v2 1/6] soc: qcom: gsbi: Add support for ADM CRCI muxing

[Kumar Gala]

On Jan 30, 2015, at 12:25 AM, Andy Gross <agross@codeaurora.org> wrote:

> This patch adds automatic configuration for the ADM CRCI muxing required to
> support DMA operations for GSBI clients.  The GSBI mode and instance determine
> the correct TCSR ADM CRCI MUX value that must be programmed so that the DMA
> works properly.
> 
> Signed-off-by: Andy Gross <agross@codeaurora.org>
> ---
> .../devicetree/bindings/soc/qcom/qcom,gsbi.txt     |   18 ++-
> drivers/soc/qcom/Kconfig                           |    1 +
> drivers/soc/qcom/qcom_gsbi.c                       |  153 ++++++++++++++++++++
> 3 files changed, 171 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt
> index 4ce24d4..8fe7b37 100644
> --- a/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt
> +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt
> @@ -6,7 +6,7 @@ configuration settings.  The mode setting will govern the input/output mode of
> the 4 GSBI IOs.
> 
> Required properties:
> -- compatible: must contain "qcom,gsbi-v1.0.0" for APQ8064/IPQ8064
> +- compatible:	Should contain "qcom,gsbi-v1.0.0"
> - reg: Address range for GSBI registers
> - clocks: required clock
> - clock-names: must contain "iface" entry
> @@ -16,12 +16,16 @@ Required properties:
> Optional properties:
> - qcom,crci : indicates CRCI MUX value for QUP CRCI ports.  Please reference
>   dt-bindings/soc/qcom,gsbi.h for valid CRCI mux values.
> +- syscon-tcsr: indicates phandle of TCSR syscon node.  Required if child uses
> +  dma.
> 
> Required properties if child node exists:
> - #address-cells: Must be 1
> - #size-cells: Must be 1
> - ranges: Must be present
> 
> +Note: Each GSBI should have an alias correctly numbered in "aliases" node.
> +
> Properties for children:
> 
> A GSBI controller node can contain 0 or more child nodes representing serial
> @@ -37,6 +41,10 @@ Example for APQ8064:
> 
> #include <dt-bindings/soc/qcom,gsbi.h>
> 
> +	aliases {
> +		gsbi4 = <&gsbi4>;
> +	};

You appear to be using the alias name to determine a index number for the gsbi, if that is the case, than you should probably just add a cell-index node to the gsbi?s for this purpose.

> +
> 	gsbi4 at 16300000 {
> 		compatible = "qcom,gsbi-v1.0.0";
> 		reg = <0x16300000 0x100>;
> @@ -48,6 +56,8 @@ Example for APQ8064:
> 		qcom,mode = <GSBI_PROT_I2C_UART>;
> 		qcom,crci = <GSBI_CRCI_QUP>;
> 
> +		syscon-tcsr = <&tcsr>;
> +
> 		/* child nodes go under here */
> 
> 		i2c_qup4: i2c at 16380000 {
> @@ -76,3 +86,9 @@ Example for APQ8064:
> 		};
> 	};
> 
> +	tcsr: syscon at 1a400000 {
> +		compatible = "qcom,apq8064-tcsr", "syscon";
> +		reg = <0x1a400000 0x100>;
> +	};
> +
> +

- k

-- 
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [Patch v2 1/6] soc: qcom: gsbi: Add support for ADM CRCI muxing

[Stephen Boyd]

On 01/30/15 08:32, Kumar Gala wrote:
> On Jan 30, 2015, at 12:25 AM, Andy Gross <agross-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> wrote:
>
>> Required properties if child node exists:
>> - #address-cells: Must be 1
>> - #size-cells: Must be 1
>> - ranges: Must be present
>>
>> +Note: Each GSBI should have an alias correctly numbered in "aliases" node.
>> +
>> Properties for children:
>>
>> A GSBI controller node can contain 0 or more child nodes representing serial
>> @@ -37,6 +41,10 @@ Example for APQ8064:
>>
>> #include <dt-bindings/soc/qcom,gsbi.h>
>>
>> +	aliases {
>> +		gsbi4 = <&gsbi4>;
>> +	};
> You appear to be using the alias name to determine a index number for the gsbi, if that is the case, than you should probably just add a cell-index node to the gsbi’s for this purpose.
>

I thought cell-index was "deprecated" and referred more to things like
enumerating all the devices on a bus by assigning them a unique ID.
Aliases, on the other hand, allow us to enumerate a subset of devices
that share the same bus with other devices of different types. For
example, how would I know that a device is gsbi1 vs serial1 if they both
used cell-index and they both had the same parent node?

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Re: [Patch v2 1/6] soc: qcom: gsbi: Add support for ADM CRCI muxing

[Stephen Boyd]

On 01/30/15 08:32, Kumar Gala wrote:
> On Jan 30, 2015, at 12:25 AM, Andy Gross <agross@codeaurora.org> wrote:
>
>> Required properties if child node exists:
>> - #address-cells: Must be 1
>> - #size-cells: Must be 1
>> - ranges: Must be present
>>
>> +Note: Each GSBI should have an alias correctly numbered in "aliases" node.
>> +
>> Properties for children:
>>
>> A GSBI controller node can contain 0 or more child nodes representing serial
>> @@ -37,6 +41,10 @@ Example for APQ8064:
>>
>> #include <dt-bindings/soc/qcom,gsbi.h>
>>
>> +	aliases {
>> +		gsbi4 = <&gsbi4>;
>> +	};
> You appear to be using the alias name to determine a index number for the gsbi, if that is the case, than you should probably just add a cell-index node to the gsbi’s for this purpose.
>

I thought cell-index was "deprecated" and referred more to things like
enumerating all the devices on a bus by assigning them a unique ID.
Aliases, on the other hand, allow us to enumerate a subset of devices
that share the same bus with other devices of different types. For
example, how would I know that a device is gsbi1 vs serial1 if they both
used cell-index and they both had the same parent node?

-- 
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a Linux Foundation Collaborative Project

[Patch v2 1/6] soc: qcom: gsbi: Add support for ADM CRCI muxing

[Stephen Boyd]

On 01/30/15 08:32, Kumar Gala wrote:
> On Jan 30, 2015, at 12:25 AM, Andy Gross <agross@codeaurora.org> wrote:
>
>> Required properties if child node exists:
>> - #address-cells: Must be 1
>> - #size-cells: Must be 1
>> - ranges: Must be present
>>
>> +Note: Each GSBI should have an alias correctly numbered in "aliases" node.
>> +
>> Properties for children:
>>
>> A GSBI controller node can contain 0 or more child nodes representing serial
>> @@ -37,6 +41,10 @@ Example for APQ8064:
>>
>> #include <dt-bindings/soc/qcom,gsbi.h>
>>
>> +	aliases {
>> +		gsbi4 = <&gsbi4>;
>> +	};
> You appear to be using the alias name to determine a index number for the gsbi, if that is the case, than you should probably just add a cell-index node to the gsbi?s for this purpose.
>

I thought cell-index was "deprecated" and referred more to things like
enumerating all the devices on a bus by assigning them a unique ID.
Aliases, on the other hand, allow us to enumerate a subset of devices
that share the same bus with other devices of different types. For
example, how would I know that a device is gsbi1 vs serial1 if they both
used cell-index and they both had the same parent node?

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Re: [Patch v2 1/6] soc: qcom: gsbi: Add support for ADM CRCI muxing

[Kumar Gala]

On Jan 30, 2015, at 3:37 PM, Stephen Boyd <sboyd@codeaurora.org> wrote:

> On 01/30/15 08:32, Kumar Gala wrote:
>> On Jan 30, 2015, at 12:25 AM, Andy Gross <agross@codeaurora.org> wrote:
>> 
>>> Required properties if child node exists:
>>> - #address-cells: Must be 1
>>> - #size-cells: Must be 1
>>> - ranges: Must be present
>>> 
>>> +Note: Each GSBI should have an alias correctly numbered in "aliases" node.
>>> +
>>> Properties for children:
>>> 
>>> A GSBI controller node can contain 0 or more child nodes representing serial
>>> @@ -37,6 +41,10 @@ Example for APQ8064:
>>> 
>>> #include <dt-bindings/soc/qcom,gsbi.h>
>>> 
>>> +	aliases {
>>> +		gsbi4 = <&gsbi4>;
>>> +	};
>> You appear to be using the alias name to determine a index number for the gsbi, if that is the case, than you should probably just add a cell-index node to the gsbi’s for this purpose.
>> 
> 
> I thought cell-index was "deprecated" and referred more to things like
> enumerating all the devices on a bus by assigning them a unique ID.
> Aliases, on the other hand, allow us to enumerate a subset of devices
> that share the same bus with other devices of different types. For
> example, how would I know that a device is gsbi1 vs serial1 if they both
> used cell-index and they both had the same parent node?

I think the problem was cell-index was never well understood and abused.  For the example you are giving you wouldn’t use cell-index because you are talking about things that would have different compatibles.  For what it appears we really are enumerating the GSBI hardware to match some programming interface convention.  If that is the case than I think cell-index is proper.

- k

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[Patch v2 1/6] soc: qcom: gsbi: Add support for ADM CRCI muxing

[Kumar Gala]

On Jan 30, 2015, at 3:37 PM, Stephen Boyd <sboyd@codeaurora.org> wrote:

> On 01/30/15 08:32, Kumar Gala wrote:
>> On Jan 30, 2015, at 12:25 AM, Andy Gross <agross@codeaurora.org> wrote:
>> 
>>> Required properties if child node exists:
>>> - #address-cells: Must be 1
>>> - #size-cells: Must be 1
>>> - ranges: Must be present
>>> 
>>> +Note: Each GSBI should have an alias correctly numbered in "aliases" node.
>>> +
>>> Properties for children:
>>> 
>>> A GSBI controller node can contain 0 or more child nodes representing serial
>>> @@ -37,6 +41,10 @@ Example for APQ8064:
>>> 
>>> #include <dt-bindings/soc/qcom,gsbi.h>
>>> 
>>> +	aliases {
>>> +		gsbi4 = <&gsbi4>;
>>> +	};
>> You appear to be using the alias name to determine a index number for the gsbi, if that is the case, than you should probably just add a cell-index node to the gsbi?s for this purpose.
>> 
> 
> I thought cell-index was "deprecated" and referred more to things like
> enumerating all the devices on a bus by assigning them a unique ID.
> Aliases, on the other hand, allow us to enumerate a subset of devices
> that share the same bus with other devices of different types. For
> example, how would I know that a device is gsbi1 vs serial1 if they both
> used cell-index and they both had the same parent node?

I think the problem was cell-index was never well understood and abused.  For the example you are giving you wouldn?t use cell-index because you are talking about things that would have different compatibles.  For what it appears we really are enumerating the GSBI hardware to match some programming interface convention.  If that is the case than I think cell-index is proper.

- k

-- 
Qualcomm Innovation Center, Inc.
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a Linux Foundation Collaborative Project

Re: [Patch v2 1/6] soc: qcom: gsbi: Add support for ADM CRCI muxing

[Stephen Boyd]

On 01/30/15 13:48, Kumar Gala wrote:
> On Jan 30, 2015, at 3:37 PM, Stephen Boyd <sboyd@codeaurora.org> wrote:
>
>> On 01/30/15 08:32, Kumar Gala wrote:
>>> On Jan 30, 2015, at 12:25 AM, Andy Gross <agross@codeaurora.org> wrote:
>>>
>>>> Required properties if child node exists:
>>>> - #address-cells: Must be 1
>>>> - #size-cells: Must be 1
>>>> - ranges: Must be present
>>>>
>>>> +Note: Each GSBI should have an alias correctly numbered in "aliases" node.
>>>> +
>>>> Properties for children:
>>>>
>>>> A GSBI controller node can contain 0 or more child nodes representing serial
>>>> @@ -37,6 +41,10 @@ Example for APQ8064:
>>>>
>>>> #include <dt-bindings/soc/qcom,gsbi.h>
>>>>
>>>> +	aliases {
>>>> +		gsbi4 = <&gsbi4>;
>>>> +	};
>>> You appear to be using the alias name to determine a index number for the gsbi, if that is the case, than you should probably just add a cell-index node to the gsbi’s for this purpose.
>>>
>> I thought cell-index was "deprecated" and referred more to things like
>> enumerating all the devices on a bus by assigning them a unique ID.
>> Aliases, on the other hand, allow us to enumerate a subset of devices
>> that share the same bus with other devices of different types. For
>> example, how would I know that a device is gsbi1 vs serial1 if they both
>> used cell-index and they both had the same parent node?
> I think the problem was cell-index was never well understood and abused.  For the example you are giving you wouldn’t use cell-index because you are talking about things that would have different compatibles.  For what it appears we really are enumerating the GSBI hardware to match some programming interface convention.  If that is the case than I think cell-index is proper.

Can you please explain when cell-index should be used and when aliases
should be used? I'm confused because I recall this message from Rob
Herring[1] where it's indicated that cell-index is pretty much
deprecated. I'm also interested to find out what cell means in
cell-index. Does it have any relation to *-cells properties?

[1] https://lkml.org/lkml/2012/11/10/102

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[Patch v2 1/6] soc: qcom: gsbi: Add support for ADM CRCI muxing

[Stephen Boyd]

On 01/30/15 13:48, Kumar Gala wrote:
> On Jan 30, 2015, at 3:37 PM, Stephen Boyd <sboyd@codeaurora.org> wrote:
>
>> On 01/30/15 08:32, Kumar Gala wrote:
>>> On Jan 30, 2015, at 12:25 AM, Andy Gross <agross@codeaurora.org> wrote:
>>>
>>>> Required properties if child node exists:
>>>> - #address-cells: Must be 1
>>>> - #size-cells: Must be 1
>>>> - ranges: Must be present
>>>>
>>>> +Note: Each GSBI should have an alias correctly numbered in "aliases" node.
>>>> +
>>>> Properties for children:
>>>>
>>>> A GSBI controller node can contain 0 or more child nodes representing serial
>>>> @@ -37,6 +41,10 @@ Example for APQ8064:
>>>>
>>>> #include <dt-bindings/soc/qcom,gsbi.h>
>>>>
>>>> +	aliases {
>>>> +		gsbi4 = <&gsbi4>;
>>>> +	};
>>> You appear to be using the alias name to determine a index number for the gsbi, if that is the case, than you should probably just add a cell-index node to the gsbi?s for this purpose.
>>>
>> I thought cell-index was "deprecated" and referred more to things like
>> enumerating all the devices on a bus by assigning them a unique ID.
>> Aliases, on the other hand, allow us to enumerate a subset of devices
>> that share the same bus with other devices of different types. For
>> example, how would I know that a device is gsbi1 vs serial1 if they both
>> used cell-index and they both had the same parent node?
> I think the problem was cell-index was never well understood and abused.  For the example you are giving you wouldn?t use cell-index because you are talking about things that would have different compatibles.  For what it appears we really are enumerating the GSBI hardware to match some programming interface convention.  If that is the case than I think cell-index is proper.

Can you please explain when cell-index should be used and when aliases
should be used? I'm confused because I recall this message from Rob
Herring[1] where it's indicated that cell-index is pretty much
deprecated. I'm also interested to find out what cell means in
cell-index. Does it have any relation to *-cells properties?

[1] https://lkml.org/lkml/2012/11/10/102

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project