* [PATCH 1/4] fsl: add EPU FSM configuration for deep sleep
@ 2015-01-30 12:22 ` Chenhui Zhao
0 siblings, 0 replies; 8+ messages in thread
From: Chenhui Zhao @ 2015-01-30 12:22 UTC (permalink / raw)
To: linux-kernel, kernel, linux-arm-kernel; +Cc: leoli, Jason.Jin
T104x, T1024 and LS1021 of Freescale have a Finite State Machine (FSM)
to control the hardware precedure in deep sleep. Software will start
the FSM to enter deep sleep after finishing prepare work.
Then, when receiving a wakeup event, the FSM will restore the SoC to
work.
This driver configures and clears the FSM registers for deep sleep. Note
that the sequence of clearing the FSM registers does matter, should follow
the sequence mentioned in the reference manual.
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
---
drivers/platform/Kconfig | 2 +
drivers/platform/Makefile | 1 +
drivers/platform/fsl/Kconfig | 11 ++
drivers/platform/fsl/Makefile | 5 +
drivers/platform/fsl/sleep_fsm.c | 263 +++++++++++++++++++++++++++++++++++++++
drivers/platform/fsl/sleep_fsm.h | 104 ++++++++++++++++
6 files changed, 386 insertions(+)
create mode 100644 drivers/platform/fsl/Kconfig
create mode 100644 drivers/platform/fsl/Makefile
create mode 100644 drivers/platform/fsl/sleep_fsm.c
create mode 100644 drivers/platform/fsl/sleep_fsm.h
diff --git a/drivers/platform/Kconfig b/drivers/platform/Kconfig
index 09fde58..85e3c95 100644
--- a/drivers/platform/Kconfig
+++ b/drivers/platform/Kconfig
@@ -6,3 +6,5 @@ source "drivers/platform/goldfish/Kconfig"
endif
source "drivers/platform/chrome/Kconfig"
+
+source "drivers/platform/fsl/Kconfig"
diff --git a/drivers/platform/Makefile b/drivers/platform/Makefile
index 3656b7b..37c6f72 100644
--- a/drivers/platform/Makefile
+++ b/drivers/platform/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_X86) += x86/
obj-$(CONFIG_OLPC) += olpc/
obj-$(CONFIG_GOLDFISH) += goldfish/
obj-$(CONFIG_CHROME_PLATFORMS) += chrome/
+obj-$(CONFIG_FSL_SOC) += fsl/
diff --git a/drivers/platform/fsl/Kconfig b/drivers/platform/fsl/Kconfig
new file mode 100644
index 0000000..a1ea46e
--- /dev/null
+++ b/drivers/platform/fsl/Kconfig
@@ -0,0 +1,11 @@
+#
+# Freescale Specific Power Management Drivers
+#
+
+config FSL_SLEEP_FSM
+ bool
+ help
+ This driver configures a hardware FSM (Finite State Machine) used in deep sleep.
+ The FSM finishes clean-ups at the last stage of entering deep sleep, and also
+ wakes up system when a wake up event happens. So far, T104x, T1024 and LS1021
+ need this.
diff --git a/drivers/platform/fsl/Makefile b/drivers/platform/fsl/Makefile
new file mode 100644
index 0000000..d99ca0e
--- /dev/null
+++ b/drivers/platform/fsl/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for linux/drivers/platform/fsl
+# Freescale Specific Power Management Drivers
+#
+obj-$(CONFIG_FSL_SLEEP_FSM) += sleep_fsm.o
diff --git a/drivers/platform/fsl/sleep_fsm.c b/drivers/platform/fsl/sleep_fsm.c
new file mode 100644
index 0000000..0a0480a
--- /dev/null
+++ b/drivers/platform/fsl/sleep_fsm.c
@@ -0,0 +1,263 @@
+/*
+ * Freescale deep sleep FSM (finite-state machine) configuration
+ *
+ * Copyright 2014-2015 Freescale Semiconductor Inc.
+ *
+ * Author: Hongbo Zhang <hongbo.zhang@freescale.com>
+ * Chenhui Zhao <chenhui.zhao@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/types.h>
+
+#include "sleep_fsm.h"
+/*
+ * These values are from chip's reference manual. For example,
+ * the values for T1040 can be found in "8.4.3.8 Programming
+ * supporting deep sleep mode" of Chapter 8 "Run Control and
+ * Power Management (RCPM)".
+ * The default value can be applied to T104x, T1024 and LS1021.
+ */
+struct fsm_reg_vals epu_default_val[] = {
+ /* EPGCR (Event Processor Global Control Register) */
+ {EPGCR, 0},
+ /* EPECR (Event Processor Event Control Registers) */
+ {EPECR0 + EPECR_STRIDE * 0, 0},
+ {EPECR0 + EPECR_STRIDE * 1, 0},
+ {EPECR0 + EPECR_STRIDE * 2, 0xF0004004},
+ {EPECR0 + EPECR_STRIDE * 3, 0x80000084},
+ {EPECR0 + EPECR_STRIDE * 4, 0x20000084},
+ {EPECR0 + EPECR_STRIDE * 5, 0x08000004},
+ {EPECR0 + EPECR_STRIDE * 6, 0x80000084},
+ {EPECR0 + EPECR_STRIDE * 7, 0x80000084},
+ {EPECR0 + EPECR_STRIDE * 8, 0x60000084},
+ {EPECR0 + EPECR_STRIDE * 9, 0x08000084},
+ {EPECR0 + EPECR_STRIDE * 10, 0x42000084},
+ {EPECR0 + EPECR_STRIDE * 11, 0x90000084},
+ {EPECR0 + EPECR_STRIDE * 12, 0x80000084},
+ {EPECR0 + EPECR_STRIDE * 13, 0x08000084},
+ {EPECR0 + EPECR_STRIDE * 14, 0x02000084},
+ {EPECR0 + EPECR_STRIDE * 15, 0x00000004},
+ /*
+ * EPEVTCR (Event Processor EVT Pin Control Registers)
+ * SCU8 triger EVT2, and SCU11 triger EVT9
+ */
+ {EPEVTCR0 + EPEVTCR_STRIDE * 0, 0},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 1, 0},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 2, 0x80000001},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 3, 0},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 4, 0},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 5, 0},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 6, 0},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 7, 0},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 8, 0},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 9, 0xB0000001},
+ /* EPCMPR (Event Processor Counter Compare Registers) */
+ {EPCMPR0 + EPCMPR_STRIDE * 0, 0},
+ {EPCMPR0 + EPCMPR_STRIDE * 1, 0},
+ {EPCMPR0 + EPCMPR_STRIDE * 2, 0x000000FF},
+ {EPCMPR0 + EPCMPR_STRIDE * 3, 0},
+ {EPCMPR0 + EPCMPR_STRIDE * 4, 0x000000FF},
+ {EPCMPR0 + EPCMPR_STRIDE * 5, 0x00000020},
+ {EPCMPR0 + EPCMPR_STRIDE * 6, 0},
+ {EPCMPR0 + EPCMPR_STRIDE * 7, 0},
+ {EPCMPR0 + EPCMPR_STRIDE * 8, 0x000000FF},
+ {EPCMPR0 + EPCMPR_STRIDE * 9, 0x000000FF},
+ {EPCMPR0 + EPCMPR_STRIDE * 10, 0x000000FF},
+ {EPCMPR0 + EPCMPR_STRIDE * 11, 0x000000FF},
+ {EPCMPR0 + EPCMPR_STRIDE * 12, 0x000000FF},
+ {EPCMPR0 + EPCMPR_STRIDE * 13, 0},
+ {EPCMPR0 + EPCMPR_STRIDE * 14, 0x000000FF},
+ {EPCMPR0 + EPCMPR_STRIDE * 15, 0x000000FF},
+ /* EPCCR (Event Processor Counter Control Registers) */
+ {EPCCR0 + EPCCR_STRIDE * 0, 0},
+ {EPCCR0 + EPCCR_STRIDE * 1, 0},
+ {EPCCR0 + EPCCR_STRIDE * 2, 0x92840000},
+ {EPCCR0 + EPCCR_STRIDE * 3, 0},
+ {EPCCR0 + EPCCR_STRIDE * 4, 0x92840000},
+ {EPCCR0 + EPCCR_STRIDE * 5, 0x92840000},
+ {EPCCR0 + EPCCR_STRIDE * 6, 0},
+ {EPCCR0 + EPCCR_STRIDE * 7, 0},
+ {EPCCR0 + EPCCR_STRIDE * 8, 0x92840000},
+ {EPCCR0 + EPCCR_STRIDE * 9, 0x92840000},
+ {EPCCR0 + EPCCR_STRIDE * 10, 0x92840000},
+ {EPCCR0 + EPCCR_STRIDE * 11, 0x92840000},
+ {EPCCR0 + EPCCR_STRIDE * 12, 0x92840000},
+ {EPCCR0 + EPCCR_STRIDE * 13, 0},
+ {EPCCR0 + EPCCR_STRIDE * 14, 0x92840000},
+ {EPCCR0 + EPCCR_STRIDE * 15, 0x92840000},
+ /* EPSMCR (Event Processor SCU Mux Control Registers) */
+ {EPSMCR0 + EPSMCR_STRIDE * 0, 0},
+ {EPSMCR0 + EPSMCR_STRIDE * 1, 0},
+ {EPSMCR0 + EPSMCR_STRIDE * 2, 0x6C700000},
+ {EPSMCR0 + EPSMCR_STRIDE * 3, 0x2F000000},
+ {EPSMCR0 + EPSMCR_STRIDE * 4, 0x002F0000},
+ {EPSMCR0 + EPSMCR_STRIDE * 5, 0x00002E00},
+ {EPSMCR0 + EPSMCR_STRIDE * 6, 0x7C000000},
+ {EPSMCR0 + EPSMCR_STRIDE * 7, 0x30000000},
+ {EPSMCR0 + EPSMCR_STRIDE * 8, 0x64300000},
+ {EPSMCR0 + EPSMCR_STRIDE * 9, 0x00003000},
+ {EPSMCR0 + EPSMCR_STRIDE * 10, 0x65000030},
+ {EPSMCR0 + EPSMCR_STRIDE * 11, 0x31740000},
+ {EPSMCR0 + EPSMCR_STRIDE * 12, 0x7F000000},
+ {EPSMCR0 + EPSMCR_STRIDE * 13, 0x00003100},
+ {EPSMCR0 + EPSMCR_STRIDE * 14, 0x00000031},
+ {EPSMCR0 + EPSMCR_STRIDE * 15, 0x76000000},
+ /* EPACR (Event Processor Action Control Registers) */
+ {EPACR0 + EPACR_STRIDE * 0, 0},
+ {EPACR0 + EPACR_STRIDE * 1, 0},
+ {EPACR0 + EPACR_STRIDE * 2, 0},
+ {EPACR0 + EPACR_STRIDE * 3, 0x00000080},
+ {EPACR0 + EPACR_STRIDE * 4, 0},
+ {EPACR0 + EPACR_STRIDE * 5, 0x00000040},
+ {EPACR0 + EPACR_STRIDE * 6, 0},
+ {EPACR0 + EPACR_STRIDE * 7, 0},
+ {EPACR0 + EPACR_STRIDE * 8, 0},
+ {EPACR0 + EPACR_STRIDE * 9, 0x0000001C},
+ {EPACR0 + EPACR_STRIDE * 10, 0x00000020},
+ {EPACR0 + EPACR_STRIDE * 11, 0},
+ {EPACR0 + EPACR_STRIDE * 12, 0x00000003},
+ {EPACR0 + EPACR_STRIDE * 13, 0x06000000},
+ {EPACR0 + EPACR_STRIDE * 14, 0x04000000},
+ {EPACR0 + EPACR_STRIDE * 15, 0x02000000},
+ /* EPIMCR (Event Processor Input Mux Control Registers) */
+ {EPIMCR0 + EPIMCR_STRIDE * 0, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 1, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 2, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 3, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 4, 0x44000000},
+ {EPIMCR0 + EPIMCR_STRIDE * 5, 0x40000000},
+ {EPIMCR0 + EPIMCR_STRIDE * 6, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 7, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 8, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 9, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 10, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 11, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 12, 0x44000000},
+ {EPIMCR0 + EPIMCR_STRIDE * 13, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 14, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 15, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 16, 0x6A000000},
+ {EPIMCR0 + EPIMCR_STRIDE * 17, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 18, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 19, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 20, 0x48000000},
+ {EPIMCR0 + EPIMCR_STRIDE * 21, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 22, 0x6C000000},
+ {EPIMCR0 + EPIMCR_STRIDE * 23, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 24, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 25, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 26, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 27, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 28, 0x76000000},
+ {EPIMCR0 + EPIMCR_STRIDE * 29, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 30, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 31, 0x76000000},
+ /* EPXTRIGCR (Event Processor Crosstrigger Control Register) */
+ {EPXTRIGCR, 0x0000FFDF},
+ /* end */
+ {FSM_END_FLAG, 0},
+};
+
+struct fsm_reg_vals npc_default_val[] = {
+ /* NPC triggered Memory-Mapped Access Registers */
+ {NCR, 0x80000000},
+ {MCCR1, 0},
+ {MCSR1, 0},
+ {MMAR1LO, 0},
+ {MMAR1HI, 0},
+ {MMDR1, 0},
+ {MCSR2, 0},
+ {MMAR2LO, 0},
+ {MMAR2HI, 0},
+ {MMDR2, 0},
+ {MCSR3, 0x80000000},
+ {MMAR3LO, 0x000E2130},
+ {MMAR3HI, 0x00030000},
+ {MMDR3, 0x00020000},
+ /* end */
+ {FSM_END_FLAG, 0},
+};
+
+static void fsl_fsm_setup(void __iomem *base, struct fsm_reg_vals *val)
+{
+ struct fsm_reg_vals *data = val;
+
+ BUG_ON(!base || !data);
+ while (data->offset != FSM_END_FLAG) {
+ iowrite32be(data->value, base + data->offset);
+ data++;
+ }
+}
+
+/**
+ * fsl_epu_setup - Configure EPU registers
+ * @epu_base: the base address of EPU registers
+ */
+void fsl_epu_setup(void __iomem *epu_base)
+{
+ fsl_fsm_setup(epu_base, epu_default_val);
+}
+
+/**
+ * fsl_npc_setup - Configure NPC registers
+ * @npc_base: the base address of NPC registers
+ */
+void fsl_npc_setup(void __iomem *npc_base)
+{
+ fsl_fsm_setup(npc_base, npc_default_val);
+}
+
+/**
+ * fsl_epu_clean - Clear EPU registers
+ * @epu_base: the base address of EPU registers
+ */
+void fsl_epu_clean(void __iomem *epu_base)
+{
+ u32 offset;
+
+ /* follow the exact sequence to clear the registers */
+ /* Clear EPACRn */
+ for (offset = EPACR0; offset <= EPACR15; offset += EPACR_STRIDE)
+ iowrite32be(0, epu_base + offset);
+
+ /* Clear EPEVTCRn */
+ for (offset = EPEVTCR0; offset <= EPEVTCR9; offset += EPEVTCR_STRIDE)
+ iowrite32be(0, epu_base + offset);
+
+ /* Clear EPGCR */
+ iowrite32be(0, epu_base + EPGCR);
+
+ /* Clear EPSMCRn */
+ for (offset = EPSMCR0; offset <= EPSMCR15; offset += EPSMCR_STRIDE)
+ iowrite32be(0, epu_base + offset);
+
+ /* Clear EPCCRn */
+ for (offset = EPCCR0; offset <= EPCCR31; offset += EPCCR_STRIDE)
+ iowrite32be(0, epu_base + offset);
+
+ /* Clear EPCMPRn */
+ for (offset = EPCMPR0; offset <= EPCMPR31; offset += EPCMPR_STRIDE)
+ iowrite32be(0, epu_base + offset);
+
+ /* Clear EPCTRn */
+ for (offset = EPCTR0; offset <= EPCTR31; offset += EPCTR_STRIDE)
+ iowrite32be(0, epu_base + offset);
+
+ /* Clear EPIMCRn */
+ for (offset = EPIMCR0; offset <= EPIMCR31; offset += EPIMCR_STRIDE)
+ iowrite32be(0, epu_base + offset);
+
+ /* Clear EPXTRIGCRn */
+ iowrite32be(0, epu_base + EPXTRIGCR);
+
+ /* Clear EPECRn */
+ for (offset = EPECR0; offset <= EPECR15; offset += EPECR_STRIDE)
+ iowrite32be(0, epu_base + offset);
+}
diff --git a/drivers/platform/fsl/sleep_fsm.h b/drivers/platform/fsl/sleep_fsm.h
new file mode 100644
index 0000000..88b60f6
--- /dev/null
+++ b/drivers/platform/fsl/sleep_fsm.h
@@ -0,0 +1,104 @@
+/*
+ * Freescale deep sleep FSM (finite-state machine) configuration
+ *
+ * Copyright 2014-2015 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#ifndef _FSL_SLEEP_FSM_H
+#define _FSL_SLEEP_FSM_H
+
+#define FSL_STRIDE_4B 4
+#define FSL_STRIDE_8B 8
+
+/* End flag */
+#define FSM_END_FLAG 0xFFFFFFFFUL
+
+/* Block offsets */
+#define RCPM_BLOCK_OFFSET 0x00022000
+#define EPU_BLOCK_OFFSET 0x00000000
+#define NPC_BLOCK_OFFSET 0x00001000
+
+/* EPGCR (Event Processor Global Control Register) */
+#define EPGCR 0x000
+
+/* EPEVTCR0-9 (Event Processor EVT Pin Control Registers) */
+#define EPEVTCR0 0x050
+#define EPEVTCR9 0x074
+#define EPEVTCR_STRIDE FSL_STRIDE_4B
+
+/* EPXTRIGCR (Event Processor Crosstrigger Control Register) */
+#define EPXTRIGCR 0x090
+
+/* EPIMCR0-31 (Event Processor Input Mux Control Registers) */
+#define EPIMCR0 0x100
+#define EPIMCR31 0x17C
+#define EPIMCR_STRIDE FSL_STRIDE_4B
+
+/* EPSMCR0-15 (Event Processor SCU Mux Control Registers) */
+#define EPSMCR0 0x200
+#define EPSMCR15 0x278
+#define EPSMCR_STRIDE FSL_STRIDE_8B
+
+/* EPECR0-15 (Event Processor Event Control Registers) */
+#define EPECR0 0x300
+#define EPECR15 0x33C
+#define EPECR_STRIDE FSL_STRIDE_4B
+
+/* EPACR0-15 (Event Processor Action Control Registers) */
+#define EPACR0 0x400
+#define EPACR15 0x43C
+#define EPACR_STRIDE FSL_STRIDE_4B
+
+/* EPCCRi0-15 (Event Processor Counter Control Registers) */
+#define EPCCR0 0x800
+#define EPCCR15 0x83C
+#define EPCCR31 0x87C
+#define EPCCR_STRIDE FSL_STRIDE_4B
+
+/* EPCMPR0-15 (Event Processor Counter Compare Registers) */
+#define EPCMPR0 0x900
+#define EPCMPR15 0x93C
+#define EPCMPR31 0x97C
+#define EPCMPR_STRIDE FSL_STRIDE_4B
+
+/* EPCTR0-31 (Event Processor Counter Register) */
+#define EPCTR0 0xA00
+#define EPCTR31 0xA7C
+#define EPCTR_STRIDE FSL_STRIDE_4B
+
+/* NPC triggered Memory-Mapped Access Registers */
+#define NCR 0x000
+#define MCCR1 0x0CC
+#define MCSR1 0x0D0
+#define MMAR1LO 0x0D4
+#define MMAR1HI 0x0D8
+#define MMDR1 0x0DC
+#define MCSR2 0x0E0
+#define MMAR2LO 0x0E4
+#define MMAR2HI 0x0E8
+#define MMDR2 0x0EC
+#define MCSR3 0x0F0
+#define MMAR3LO 0x0F4
+#define MMAR3HI 0x0F8
+#define MMDR3 0x0FC
+
+/* RCPM Core State Action Control Register 0 */
+#define CSTTACR0 0xB00
+
+/* RCPM Core Group 1 Configuration Register 0 */
+#define CG1CR0 0x31C
+
+struct fsm_reg_vals {
+ u32 offset;
+ u32 value;
+};
+
+void fsl_epu_setup(void __iomem *epu_base);
+void fsl_npc_setup(void __iomem *npc_base);
+void fsl_epu_clean(void __iomem *epu_base);
+
+#endif /* _FSL_SLEEP_FSM_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 1/4] fsl: add EPU FSM configuration for deep sleep
@ 2015-01-30 12:22 ` Chenhui Zhao
0 siblings, 0 replies; 8+ messages in thread
From: Chenhui Zhao @ 2015-01-30 12:22 UTC (permalink / raw)
To: linux-arm-kernel
T104x, T1024 and LS1021 of Freescale have a Finite State Machine (FSM)
to control the hardware precedure in deep sleep. Software will start
the FSM to enter deep sleep after finishing prepare work.
Then, when receiving a wakeup event, the FSM will restore the SoC to
work.
This driver configures and clears the FSM registers for deep sleep. Note
that the sequence of clearing the FSM registers does matter, should follow
the sequence mentioned in the reference manual.
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
---
drivers/platform/Kconfig | 2 +
drivers/platform/Makefile | 1 +
drivers/platform/fsl/Kconfig | 11 ++
drivers/platform/fsl/Makefile | 5 +
drivers/platform/fsl/sleep_fsm.c | 263 +++++++++++++++++++++++++++++++++++++++
drivers/platform/fsl/sleep_fsm.h | 104 ++++++++++++++++
6 files changed, 386 insertions(+)
create mode 100644 drivers/platform/fsl/Kconfig
create mode 100644 drivers/platform/fsl/Makefile
create mode 100644 drivers/platform/fsl/sleep_fsm.c
create mode 100644 drivers/platform/fsl/sleep_fsm.h
diff --git a/drivers/platform/Kconfig b/drivers/platform/Kconfig
index 09fde58..85e3c95 100644
--- a/drivers/platform/Kconfig
+++ b/drivers/platform/Kconfig
@@ -6,3 +6,5 @@ source "drivers/platform/goldfish/Kconfig"
endif
source "drivers/platform/chrome/Kconfig"
+
+source "drivers/platform/fsl/Kconfig"
diff --git a/drivers/platform/Makefile b/drivers/platform/Makefile
index 3656b7b..37c6f72 100644
--- a/drivers/platform/Makefile
+++ b/drivers/platform/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_X86) += x86/
obj-$(CONFIG_OLPC) += olpc/
obj-$(CONFIG_GOLDFISH) += goldfish/
obj-$(CONFIG_CHROME_PLATFORMS) += chrome/
+obj-$(CONFIG_FSL_SOC) += fsl/
diff --git a/drivers/platform/fsl/Kconfig b/drivers/platform/fsl/Kconfig
new file mode 100644
index 0000000..a1ea46e
--- /dev/null
+++ b/drivers/platform/fsl/Kconfig
@@ -0,0 +1,11 @@
+#
+# Freescale Specific Power Management Drivers
+#
+
+config FSL_SLEEP_FSM
+ bool
+ help
+ This driver configures a hardware FSM (Finite State Machine) used in deep sleep.
+ The FSM finishes clean-ups at the last stage of entering deep sleep, and also
+ wakes up system when a wake up event happens. So far, T104x, T1024 and LS1021
+ need this.
diff --git a/drivers/platform/fsl/Makefile b/drivers/platform/fsl/Makefile
new file mode 100644
index 0000000..d99ca0e
--- /dev/null
+++ b/drivers/platform/fsl/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for linux/drivers/platform/fsl
+# Freescale Specific Power Management Drivers
+#
+obj-$(CONFIG_FSL_SLEEP_FSM) += sleep_fsm.o
diff --git a/drivers/platform/fsl/sleep_fsm.c b/drivers/platform/fsl/sleep_fsm.c
new file mode 100644
index 0000000..0a0480a
--- /dev/null
+++ b/drivers/platform/fsl/sleep_fsm.c
@@ -0,0 +1,263 @@
+/*
+ * Freescale deep sleep FSM (finite-state machine) configuration
+ *
+ * Copyright 2014-2015 Freescale Semiconductor Inc.
+ *
+ * Author: Hongbo Zhang <hongbo.zhang@freescale.com>
+ * Chenhui Zhao <chenhui.zhao@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/types.h>
+
+#include "sleep_fsm.h"
+/*
+ * These values are from chip's reference manual. For example,
+ * the values for T1040 can be found in "8.4.3.8 Programming
+ * supporting deep sleep mode" of Chapter 8 "Run Control and
+ * Power Management (RCPM)".
+ * The default value can be applied to T104x, T1024 and LS1021.
+ */
+struct fsm_reg_vals epu_default_val[] = {
+ /* EPGCR (Event Processor Global Control Register) */
+ {EPGCR, 0},
+ /* EPECR (Event Processor Event Control Registers) */
+ {EPECR0 + EPECR_STRIDE * 0, 0},
+ {EPECR0 + EPECR_STRIDE * 1, 0},
+ {EPECR0 + EPECR_STRIDE * 2, 0xF0004004},
+ {EPECR0 + EPECR_STRIDE * 3, 0x80000084},
+ {EPECR0 + EPECR_STRIDE * 4, 0x20000084},
+ {EPECR0 + EPECR_STRIDE * 5, 0x08000004},
+ {EPECR0 + EPECR_STRIDE * 6, 0x80000084},
+ {EPECR0 + EPECR_STRIDE * 7, 0x80000084},
+ {EPECR0 + EPECR_STRIDE * 8, 0x60000084},
+ {EPECR0 + EPECR_STRIDE * 9, 0x08000084},
+ {EPECR0 + EPECR_STRIDE * 10, 0x42000084},
+ {EPECR0 + EPECR_STRIDE * 11, 0x90000084},
+ {EPECR0 + EPECR_STRIDE * 12, 0x80000084},
+ {EPECR0 + EPECR_STRIDE * 13, 0x08000084},
+ {EPECR0 + EPECR_STRIDE * 14, 0x02000084},
+ {EPECR0 + EPECR_STRIDE * 15, 0x00000004},
+ /*
+ * EPEVTCR (Event Processor EVT Pin Control Registers)
+ * SCU8 triger EVT2, and SCU11 triger EVT9
+ */
+ {EPEVTCR0 + EPEVTCR_STRIDE * 0, 0},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 1, 0},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 2, 0x80000001},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 3, 0},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 4, 0},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 5, 0},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 6, 0},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 7, 0},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 8, 0},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 9, 0xB0000001},
+ /* EPCMPR (Event Processor Counter Compare Registers) */
+ {EPCMPR0 + EPCMPR_STRIDE * 0, 0},
+ {EPCMPR0 + EPCMPR_STRIDE * 1, 0},
+ {EPCMPR0 + EPCMPR_STRIDE * 2, 0x000000FF},
+ {EPCMPR0 + EPCMPR_STRIDE * 3, 0},
+ {EPCMPR0 + EPCMPR_STRIDE * 4, 0x000000FF},
+ {EPCMPR0 + EPCMPR_STRIDE * 5, 0x00000020},
+ {EPCMPR0 + EPCMPR_STRIDE * 6, 0},
+ {EPCMPR0 + EPCMPR_STRIDE * 7, 0},
+ {EPCMPR0 + EPCMPR_STRIDE * 8, 0x000000FF},
+ {EPCMPR0 + EPCMPR_STRIDE * 9, 0x000000FF},
+ {EPCMPR0 + EPCMPR_STRIDE * 10, 0x000000FF},
+ {EPCMPR0 + EPCMPR_STRIDE * 11, 0x000000FF},
+ {EPCMPR0 + EPCMPR_STRIDE * 12, 0x000000FF},
+ {EPCMPR0 + EPCMPR_STRIDE * 13, 0},
+ {EPCMPR0 + EPCMPR_STRIDE * 14, 0x000000FF},
+ {EPCMPR0 + EPCMPR_STRIDE * 15, 0x000000FF},
+ /* EPCCR (Event Processor Counter Control Registers) */
+ {EPCCR0 + EPCCR_STRIDE * 0, 0},
+ {EPCCR0 + EPCCR_STRIDE * 1, 0},
+ {EPCCR0 + EPCCR_STRIDE * 2, 0x92840000},
+ {EPCCR0 + EPCCR_STRIDE * 3, 0},
+ {EPCCR0 + EPCCR_STRIDE * 4, 0x92840000},
+ {EPCCR0 + EPCCR_STRIDE * 5, 0x92840000},
+ {EPCCR0 + EPCCR_STRIDE * 6, 0},
+ {EPCCR0 + EPCCR_STRIDE * 7, 0},
+ {EPCCR0 + EPCCR_STRIDE * 8, 0x92840000},
+ {EPCCR0 + EPCCR_STRIDE * 9, 0x92840000},
+ {EPCCR0 + EPCCR_STRIDE * 10, 0x92840000},
+ {EPCCR0 + EPCCR_STRIDE * 11, 0x92840000},
+ {EPCCR0 + EPCCR_STRIDE * 12, 0x92840000},
+ {EPCCR0 + EPCCR_STRIDE * 13, 0},
+ {EPCCR0 + EPCCR_STRIDE * 14, 0x92840000},
+ {EPCCR0 + EPCCR_STRIDE * 15, 0x92840000},
+ /* EPSMCR (Event Processor SCU Mux Control Registers) */
+ {EPSMCR0 + EPSMCR_STRIDE * 0, 0},
+ {EPSMCR0 + EPSMCR_STRIDE * 1, 0},
+ {EPSMCR0 + EPSMCR_STRIDE * 2, 0x6C700000},
+ {EPSMCR0 + EPSMCR_STRIDE * 3, 0x2F000000},
+ {EPSMCR0 + EPSMCR_STRIDE * 4, 0x002F0000},
+ {EPSMCR0 + EPSMCR_STRIDE * 5, 0x00002E00},
+ {EPSMCR0 + EPSMCR_STRIDE * 6, 0x7C000000},
+ {EPSMCR0 + EPSMCR_STRIDE * 7, 0x30000000},
+ {EPSMCR0 + EPSMCR_STRIDE * 8, 0x64300000},
+ {EPSMCR0 + EPSMCR_STRIDE * 9, 0x00003000},
+ {EPSMCR0 + EPSMCR_STRIDE * 10, 0x65000030},
+ {EPSMCR0 + EPSMCR_STRIDE * 11, 0x31740000},
+ {EPSMCR0 + EPSMCR_STRIDE * 12, 0x7F000000},
+ {EPSMCR0 + EPSMCR_STRIDE * 13, 0x00003100},
+ {EPSMCR0 + EPSMCR_STRIDE * 14, 0x00000031},
+ {EPSMCR0 + EPSMCR_STRIDE * 15, 0x76000000},
+ /* EPACR (Event Processor Action Control Registers) */
+ {EPACR0 + EPACR_STRIDE * 0, 0},
+ {EPACR0 + EPACR_STRIDE * 1, 0},
+ {EPACR0 + EPACR_STRIDE * 2, 0},
+ {EPACR0 + EPACR_STRIDE * 3, 0x00000080},
+ {EPACR0 + EPACR_STRIDE * 4, 0},
+ {EPACR0 + EPACR_STRIDE * 5, 0x00000040},
+ {EPACR0 + EPACR_STRIDE * 6, 0},
+ {EPACR0 + EPACR_STRIDE * 7, 0},
+ {EPACR0 + EPACR_STRIDE * 8, 0},
+ {EPACR0 + EPACR_STRIDE * 9, 0x0000001C},
+ {EPACR0 + EPACR_STRIDE * 10, 0x00000020},
+ {EPACR0 + EPACR_STRIDE * 11, 0},
+ {EPACR0 + EPACR_STRIDE * 12, 0x00000003},
+ {EPACR0 + EPACR_STRIDE * 13, 0x06000000},
+ {EPACR0 + EPACR_STRIDE * 14, 0x04000000},
+ {EPACR0 + EPACR_STRIDE * 15, 0x02000000},
+ /* EPIMCR (Event Processor Input Mux Control Registers) */
+ {EPIMCR0 + EPIMCR_STRIDE * 0, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 1, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 2, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 3, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 4, 0x44000000},
+ {EPIMCR0 + EPIMCR_STRIDE * 5, 0x40000000},
+ {EPIMCR0 + EPIMCR_STRIDE * 6, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 7, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 8, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 9, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 10, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 11, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 12, 0x44000000},
+ {EPIMCR0 + EPIMCR_STRIDE * 13, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 14, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 15, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 16, 0x6A000000},
+ {EPIMCR0 + EPIMCR_STRIDE * 17, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 18, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 19, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 20, 0x48000000},
+ {EPIMCR0 + EPIMCR_STRIDE * 21, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 22, 0x6C000000},
+ {EPIMCR0 + EPIMCR_STRIDE * 23, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 24, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 25, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 26, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 27, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 28, 0x76000000},
+ {EPIMCR0 + EPIMCR_STRIDE * 29, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 30, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 31, 0x76000000},
+ /* EPXTRIGCR (Event Processor Crosstrigger Control Register) */
+ {EPXTRIGCR, 0x0000FFDF},
+ /* end */
+ {FSM_END_FLAG, 0},
+};
+
+struct fsm_reg_vals npc_default_val[] = {
+ /* NPC triggered Memory-Mapped Access Registers */
+ {NCR, 0x80000000},
+ {MCCR1, 0},
+ {MCSR1, 0},
+ {MMAR1LO, 0},
+ {MMAR1HI, 0},
+ {MMDR1, 0},
+ {MCSR2, 0},
+ {MMAR2LO, 0},
+ {MMAR2HI, 0},
+ {MMDR2, 0},
+ {MCSR3, 0x80000000},
+ {MMAR3LO, 0x000E2130},
+ {MMAR3HI, 0x00030000},
+ {MMDR3, 0x00020000},
+ /* end */
+ {FSM_END_FLAG, 0},
+};
+
+static void fsl_fsm_setup(void __iomem *base, struct fsm_reg_vals *val)
+{
+ struct fsm_reg_vals *data = val;
+
+ BUG_ON(!base || !data);
+ while (data->offset != FSM_END_FLAG) {
+ iowrite32be(data->value, base + data->offset);
+ data++;
+ }
+}
+
+/**
+ * fsl_epu_setup - Configure EPU registers
+ * @epu_base: the base address of EPU registers
+ */
+void fsl_epu_setup(void __iomem *epu_base)
+{
+ fsl_fsm_setup(epu_base, epu_default_val);
+}
+
+/**
+ * fsl_npc_setup - Configure NPC registers
+ * @npc_base: the base address of NPC registers
+ */
+void fsl_npc_setup(void __iomem *npc_base)
+{
+ fsl_fsm_setup(npc_base, npc_default_val);
+}
+
+/**
+ * fsl_epu_clean - Clear EPU registers
+ * @epu_base: the base address of EPU registers
+ */
+void fsl_epu_clean(void __iomem *epu_base)
+{
+ u32 offset;
+
+ /* follow the exact sequence to clear the registers */
+ /* Clear EPACRn */
+ for (offset = EPACR0; offset <= EPACR15; offset += EPACR_STRIDE)
+ iowrite32be(0, epu_base + offset);
+
+ /* Clear EPEVTCRn */
+ for (offset = EPEVTCR0; offset <= EPEVTCR9; offset += EPEVTCR_STRIDE)
+ iowrite32be(0, epu_base + offset);
+
+ /* Clear EPGCR */
+ iowrite32be(0, epu_base + EPGCR);
+
+ /* Clear EPSMCRn */
+ for (offset = EPSMCR0; offset <= EPSMCR15; offset += EPSMCR_STRIDE)
+ iowrite32be(0, epu_base + offset);
+
+ /* Clear EPCCRn */
+ for (offset = EPCCR0; offset <= EPCCR31; offset += EPCCR_STRIDE)
+ iowrite32be(0, epu_base + offset);
+
+ /* Clear EPCMPRn */
+ for (offset = EPCMPR0; offset <= EPCMPR31; offset += EPCMPR_STRIDE)
+ iowrite32be(0, epu_base + offset);
+
+ /* Clear EPCTRn */
+ for (offset = EPCTR0; offset <= EPCTR31; offset += EPCTR_STRIDE)
+ iowrite32be(0, epu_base + offset);
+
+ /* Clear EPIMCRn */
+ for (offset = EPIMCR0; offset <= EPIMCR31; offset += EPIMCR_STRIDE)
+ iowrite32be(0, epu_base + offset);
+
+ /* Clear EPXTRIGCRn */
+ iowrite32be(0, epu_base + EPXTRIGCR);
+
+ /* Clear EPECRn */
+ for (offset = EPECR0; offset <= EPECR15; offset += EPECR_STRIDE)
+ iowrite32be(0, epu_base + offset);
+}
diff --git a/drivers/platform/fsl/sleep_fsm.h b/drivers/platform/fsl/sleep_fsm.h
new file mode 100644
index 0000000..88b60f6
--- /dev/null
+++ b/drivers/platform/fsl/sleep_fsm.h
@@ -0,0 +1,104 @@
+/*
+ * Freescale deep sleep FSM (finite-state machine) configuration
+ *
+ * Copyright 2014-2015 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#ifndef _FSL_SLEEP_FSM_H
+#define _FSL_SLEEP_FSM_H
+
+#define FSL_STRIDE_4B 4
+#define FSL_STRIDE_8B 8
+
+/* End flag */
+#define FSM_END_FLAG 0xFFFFFFFFUL
+
+/* Block offsets */
+#define RCPM_BLOCK_OFFSET 0x00022000
+#define EPU_BLOCK_OFFSET 0x00000000
+#define NPC_BLOCK_OFFSET 0x00001000
+
+/* EPGCR (Event Processor Global Control Register) */
+#define EPGCR 0x000
+
+/* EPEVTCR0-9 (Event Processor EVT Pin Control Registers) */
+#define EPEVTCR0 0x050
+#define EPEVTCR9 0x074
+#define EPEVTCR_STRIDE FSL_STRIDE_4B
+
+/* EPXTRIGCR (Event Processor Crosstrigger Control Register) */
+#define EPXTRIGCR 0x090
+
+/* EPIMCR0-31 (Event Processor Input Mux Control Registers) */
+#define EPIMCR0 0x100
+#define EPIMCR31 0x17C
+#define EPIMCR_STRIDE FSL_STRIDE_4B
+
+/* EPSMCR0-15 (Event Processor SCU Mux Control Registers) */
+#define EPSMCR0 0x200
+#define EPSMCR15 0x278
+#define EPSMCR_STRIDE FSL_STRIDE_8B
+
+/* EPECR0-15 (Event Processor Event Control Registers) */
+#define EPECR0 0x300
+#define EPECR15 0x33C
+#define EPECR_STRIDE FSL_STRIDE_4B
+
+/* EPACR0-15 (Event Processor Action Control Registers) */
+#define EPACR0 0x400
+#define EPACR15 0x43C
+#define EPACR_STRIDE FSL_STRIDE_4B
+
+/* EPCCRi0-15 (Event Processor Counter Control Registers) */
+#define EPCCR0 0x800
+#define EPCCR15 0x83C
+#define EPCCR31 0x87C
+#define EPCCR_STRIDE FSL_STRIDE_4B
+
+/* EPCMPR0-15 (Event Processor Counter Compare Registers) */
+#define EPCMPR0 0x900
+#define EPCMPR15 0x93C
+#define EPCMPR31 0x97C
+#define EPCMPR_STRIDE FSL_STRIDE_4B
+
+/* EPCTR0-31 (Event Processor Counter Register) */
+#define EPCTR0 0xA00
+#define EPCTR31 0xA7C
+#define EPCTR_STRIDE FSL_STRIDE_4B
+
+/* NPC triggered Memory-Mapped Access Registers */
+#define NCR 0x000
+#define MCCR1 0x0CC
+#define MCSR1 0x0D0
+#define MMAR1LO 0x0D4
+#define MMAR1HI 0x0D8
+#define MMDR1 0x0DC
+#define MCSR2 0x0E0
+#define MMAR2LO 0x0E4
+#define MMAR2HI 0x0E8
+#define MMDR2 0x0EC
+#define MCSR3 0x0F0
+#define MMAR3LO 0x0F4
+#define MMAR3HI 0x0F8
+#define MMDR3 0x0FC
+
+/* RCPM Core State Action Control Register 0 */
+#define CSTTACR0 0xB00
+
+/* RCPM Core Group 1 Configuration Register 0 */
+#define CG1CR0 0x31C
+
+struct fsm_reg_vals {
+ u32 offset;
+ u32 value;
+};
+
+void fsl_epu_setup(void __iomem *epu_base);
+void fsl_npc_setup(void __iomem *npc_base);
+void fsl_epu_clean(void __iomem *epu_base);
+
+#endif /* _FSL_SLEEP_FSM_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 2/4] arm: ls1021a: add dts nodes required by deep sleep
2015-01-30 12:22 ` Chenhui Zhao
@ 2015-01-30 12:22 ` Chenhui Zhao
-1 siblings, 0 replies; 8+ messages in thread
From: Chenhui Zhao @ 2015-01-30 12:22 UTC (permalink / raw)
To: linux-kernel, kernel, linux-arm-kernel; +Cc: leoli, Jason.Jin
Add RCPM and DCSR nodes.
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
---
arch/arm/boot/dts/ls1021a-qds.dts | 6 +-
arch/arm/boot/dts/ls1021a.dtsi | 117 ++++++++++++++++++++++++++++++++++++++
2 files changed, 122 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/ls1021a-qds.dts
index 9c5e16b..6903f43 100644
--- a/arch/arm/boot/dts/ls1021a-qds.dts
+++ b/arch/arm/boot/dts/ls1021a-qds.dts
@@ -157,7 +157,7 @@
fpga: board-control@3,0 {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "simple-bus";
+ compatible = "fsl,ls1021aqds-fpga", "simple-bus";
reg = <0x3 0x0 0x0000100>;
bank-width = <1>;
device-width = <1>;
@@ -238,3 +238,7 @@
&uart1 {
status = "okay";
};
+
+&rcpm {
+ fsl,deep-sleep;
+};
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index c70bb27..0c51ce0 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -183,6 +183,11 @@
};
};
+ rcpm: rcpm@1ee2000 {
+ compatible = "fsl,ls1021a-rcpm", "fsl,qoriq-rcpm-2.1";
+ reg = <0x0 0x1ee2000 0x0 0x10000>;
+ };
+
dspi0: dspi@2100000 {
compatible = "fsl,vf610-dspi";
#address-cells = <1>;
@@ -406,4 +411,116 @@
dr_mode = "host";
};
};
+
+ dcsr {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,dcsr", "simple-bus";
+ ranges = <0x0 0x0 0x20000000 0x1000000>;
+
+ dcsr-epu@0 {
+ compatible = "fsl,ls1021a-dcsr-epu";
+ reg = <0x0 0x10000>;
+ };
+
+ dcsr-gdi@100000 {
+ compatible = "fsl,ls1021a-dcsr-gdi";
+ reg = <0x100000 0x10000>;
+ };
+
+ dcsr-dddi@120000 {
+ compatible = "fsl,ls1021a-dcsr-dddi";
+ reg = <0x120000 0x10000>;
+ };
+
+ dcsr-dcfg@220000 {
+ compatible = "fsl,ls1021a-dcsr-dcfg";
+ reg = <0x220000 0x1000>;
+ };
+
+ dcsr-clock@221000 {
+ compatible = "fsl,ls1021a-dcsr-clock";
+ reg = <0x221000 0x1000>;
+ };
+
+ dcsr-rcpm@222000 {
+ compatible = "fsl,ls1021a-dcsr-rcpm";
+ reg = <0x222000 0x1000 0x223000 0x1000>;
+ };
+
+ dcsr-ccp@225000 {
+ compatible = "fsl,ls1021a-dcsr-ccp";
+ reg = <0x225000 0x1000>;
+ };
+
+ dcsr-fusectrl@226000 {
+ compatible = "fsl,ls1021a-dcsr-fusectrl";
+ reg = <0x226000 0x1000>;
+ };
+
+ dcsr-dap@300000 {
+ compatible = "fsl,ls1021a-dcsr-dap";
+ reg = <0x300000 0x10000>;
+ };
+
+ dcsr-cstf@350000 {
+ compatible = "fsl,ls1021a-dcsr-cstf";
+ reg = <0x350000 0x1000 0x3a7000 0x1000>;
+ };
+
+ dcsr-a7rom@360000 {
+ compatible = "fsl,ls1021a-dcsr-a7rom";
+ reg = <0x360000 0x10000>;
+ };
+
+ dcsr-a7cpu@370000 {
+ compatible = "fsl,ls1021a-dcsr-a7cpu";
+ reg = <0x370000 0x8000>;
+ };
+
+ dcsr-a7cti@378000 {
+ compatible = "fsl,ls1021a-dcsr-a7cti";
+ reg = <0x378000 0x4000>;
+ };
+
+ dcsr-etm@37c000 {
+ compatible = "fsl,ls1021a-dcsr-etm";
+ reg = <0x37c000 0x1000 0x37d000 0x3000>;
+ };
+
+ dcsr-hugorom@3a0000 {
+ compatible = "fsl,ls1021a-dcsr-hugorom";
+ reg = <0x3a0000 0x1000>;
+ };
+
+ dcsr-etf@3a1000 {
+ compatible = "fsl,ls1021a-dcsr-etf";
+ reg = <0x3a1000 0x1000 0x3a2000 0x1000>;
+ };
+
+ dcsr-etr@3a3000 {
+ compatible = "fsl,ls1021a-dcsr-etr";
+ reg = <0x3a3000 0x1000>;
+ };
+
+ dcsr-cti@3a4000 {
+ compatible = "fsl,ls1021a-dcsr-cti";
+ reg = <0x3a4000 0x1000 0x3a5000 0x1000 0x3a6000 0x1000>;
+ };
+
+ dcsr-atbrepl@3a8000 {
+ compatible = "fsl,ls1021a-dcsr-atbrepl";
+ reg = <0x3a8000 0x1000>;
+ };
+
+ dcsr-tsgen-ctrl@3a9000 {
+ compatible = "fsl,ls1021a-dcsr-tsgen-ctrl";
+ reg = <0x3a9000 0x1000>;
+ };
+
+ dcsr-tsgen-read@3aa000 {
+ compatible = "fsl,ls1021a-dcsr-tsgen-read";
+ reg = <0x3aa000 0x1000>;
+ };
+ };
};
--
1.9.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 2/4] arm: ls1021a: add dts nodes required by deep sleep
@ 2015-01-30 12:22 ` Chenhui Zhao
0 siblings, 0 replies; 8+ messages in thread
From: Chenhui Zhao @ 2015-01-30 12:22 UTC (permalink / raw)
To: linux-arm-kernel
Add RCPM and DCSR nodes.
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
---
arch/arm/boot/dts/ls1021a-qds.dts | 6 +-
arch/arm/boot/dts/ls1021a.dtsi | 117 ++++++++++++++++++++++++++++++++++++++
2 files changed, 122 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/ls1021a-qds.dts
index 9c5e16b..6903f43 100644
--- a/arch/arm/boot/dts/ls1021a-qds.dts
+++ b/arch/arm/boot/dts/ls1021a-qds.dts
@@ -157,7 +157,7 @@
fpga: board-control at 3,0 {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "simple-bus";
+ compatible = "fsl,ls1021aqds-fpga", "simple-bus";
reg = <0x3 0x0 0x0000100>;
bank-width = <1>;
device-width = <1>;
@@ -238,3 +238,7 @@
&uart1 {
status = "okay";
};
+
+&rcpm {
+ fsl,deep-sleep;
+};
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index c70bb27..0c51ce0 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -183,6 +183,11 @@
};
};
+ rcpm: rcpm at 1ee2000 {
+ compatible = "fsl,ls1021a-rcpm", "fsl,qoriq-rcpm-2.1";
+ reg = <0x0 0x1ee2000 0x0 0x10000>;
+ };
+
dspi0: dspi at 2100000 {
compatible = "fsl,vf610-dspi";
#address-cells = <1>;
@@ -406,4 +411,116 @@
dr_mode = "host";
};
};
+
+ dcsr {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,dcsr", "simple-bus";
+ ranges = <0x0 0x0 0x20000000 0x1000000>;
+
+ dcsr-epu at 0 {
+ compatible = "fsl,ls1021a-dcsr-epu";
+ reg = <0x0 0x10000>;
+ };
+
+ dcsr-gdi at 100000 {
+ compatible = "fsl,ls1021a-dcsr-gdi";
+ reg = <0x100000 0x10000>;
+ };
+
+ dcsr-dddi at 120000 {
+ compatible = "fsl,ls1021a-dcsr-dddi";
+ reg = <0x120000 0x10000>;
+ };
+
+ dcsr-dcfg at 220000 {
+ compatible = "fsl,ls1021a-dcsr-dcfg";
+ reg = <0x220000 0x1000>;
+ };
+
+ dcsr-clock at 221000 {
+ compatible = "fsl,ls1021a-dcsr-clock";
+ reg = <0x221000 0x1000>;
+ };
+
+ dcsr-rcpm at 222000 {
+ compatible = "fsl,ls1021a-dcsr-rcpm";
+ reg = <0x222000 0x1000 0x223000 0x1000>;
+ };
+
+ dcsr-ccp at 225000 {
+ compatible = "fsl,ls1021a-dcsr-ccp";
+ reg = <0x225000 0x1000>;
+ };
+
+ dcsr-fusectrl at 226000 {
+ compatible = "fsl,ls1021a-dcsr-fusectrl";
+ reg = <0x226000 0x1000>;
+ };
+
+ dcsr-dap at 300000 {
+ compatible = "fsl,ls1021a-dcsr-dap";
+ reg = <0x300000 0x10000>;
+ };
+
+ dcsr-cstf at 350000 {
+ compatible = "fsl,ls1021a-dcsr-cstf";
+ reg = <0x350000 0x1000 0x3a7000 0x1000>;
+ };
+
+ dcsr-a7rom at 360000 {
+ compatible = "fsl,ls1021a-dcsr-a7rom";
+ reg = <0x360000 0x10000>;
+ };
+
+ dcsr-a7cpu at 370000 {
+ compatible = "fsl,ls1021a-dcsr-a7cpu";
+ reg = <0x370000 0x8000>;
+ };
+
+ dcsr-a7cti at 378000 {
+ compatible = "fsl,ls1021a-dcsr-a7cti";
+ reg = <0x378000 0x4000>;
+ };
+
+ dcsr-etm at 37c000 {
+ compatible = "fsl,ls1021a-dcsr-etm";
+ reg = <0x37c000 0x1000 0x37d000 0x3000>;
+ };
+
+ dcsr-hugorom at 3a0000 {
+ compatible = "fsl,ls1021a-dcsr-hugorom";
+ reg = <0x3a0000 0x1000>;
+ };
+
+ dcsr-etf at 3a1000 {
+ compatible = "fsl,ls1021a-dcsr-etf";
+ reg = <0x3a1000 0x1000 0x3a2000 0x1000>;
+ };
+
+ dcsr-etr at 3a3000 {
+ compatible = "fsl,ls1021a-dcsr-etr";
+ reg = <0x3a3000 0x1000>;
+ };
+
+ dcsr-cti at 3a4000 {
+ compatible = "fsl,ls1021a-dcsr-cti";
+ reg = <0x3a4000 0x1000 0x3a5000 0x1000 0x3a6000 0x1000>;
+ };
+
+ dcsr-atbrepl at 3a8000 {
+ compatible = "fsl,ls1021a-dcsr-atbrepl";
+ reg = <0x3a8000 0x1000>;
+ };
+
+ dcsr-tsgen-ctrl at 3a9000 {
+ compatible = "fsl,ls1021a-dcsr-tsgen-ctrl";
+ reg = <0x3a9000 0x1000>;
+ };
+
+ dcsr-tsgen-read at 3aa000 {
+ compatible = "fsl,ls1021a-dcsr-tsgen-read";
+ reg = <0x3aa000 0x1000>;
+ };
+ };
};
--
1.9.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 3/4] arm: ls1021a: add deep sleep support
2015-01-30 12:22 ` Chenhui Zhao
@ 2015-01-30 12:22 ` Chenhui Zhao
-1 siblings, 0 replies; 8+ messages in thread
From: Chenhui Zhao @ 2015-01-30 12:22 UTC (permalink / raw)
To: linux-kernel, kernel, linux-arm-kernel; +Cc: leoli, Jason.Jin
The ls1021a SoC supports deep sleep feature that can switch off most
parts of the SoC when it is in deep sleep state.
The DDR controller will also be powered off in deep sleep. Therefore,
copy the last stage code to enter deep sleep to SRAM and run it
with disabling MMU and caches.
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
---
arch/arm/mach-imx/Kconfig | 1 +
arch/arm/mach-imx/Makefile | 2 +
arch/arm/mach-imx/pm-ls1.c | 374 ++++++++++++++++++++++++++++++++++++++++++
arch/arm/mach-imx/sleep-ls1.S | 137 ++++++++++++++++
arch/arm/mach-imx/sleep-ls1.h | 19 +++
5 files changed, 533 insertions(+)
create mode 100644 arch/arm/mach-imx/pm-ls1.c
create mode 100644 arch/arm/mach-imx/sleep-ls1.S
create mode 100644 arch/arm/mach-imx/sleep-ls1.h
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index e8627e0..c10acff 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -664,6 +664,7 @@ config SOC_LS1021A
select HAVE_ARM_ARCH_TIMER
select PCI_DOMAINS if PCI
select ZONE_DMA if ARM_LPAE
+ select FSL_SLEEP_FSM if PM
help
This enable support for Freescale LS1021A processor.
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index f5ac685..358adf4 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -101,6 +101,8 @@ obj-$(CONFIG_SOC_IMX6SX) += clk-imx6sx.o mach-imx6sx.o
ifeq ($(CONFIG_SUSPEND),y)
AFLAGS_suspend-imx6.o :=-Wa,-march=armv7-a
obj-$(CONFIG_SOC_IMX6) += suspend-imx6.o
+AFLAGS_sleep-ls1.o :=-Wa,-march=armv7-a
+obj-$(CONFIG_SOC_LS1021A) += pm-ls1.o sleep-ls1.o
endif
obj-$(CONFIG_SOC_IMX6) += pm-imx6.o
diff --git a/arch/arm/mach-imx/pm-ls1.c b/arch/arm/mach-imx/pm-ls1.c
new file mode 100644
index 0000000..4f9ca80
--- /dev/null
+++ b/arch/arm/mach-imx/pm-ls1.c
@@ -0,0 +1,374 @@
+/*
+ * Support deep sleep feature for LS1
+ *
+ * Copyright 2014-2015 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/suspend.h>
+#include <linux/io.h>
+#include <linux/of_platform.h>
+#include <linux/of_address.h>
+#include <linux/cpu_pm.h>
+#include <asm/suspend.h>
+#include <asm/delay.h>
+#include <asm/cp15.h>
+#include <asm/cacheflush.h>
+#include <asm/idmap.h>
+
+#include "common.h"
+#include "sleep-ls1.h"
+
+#define FSL_SLEEP 0x1
+#define FSL_DEEP_SLEEP 0x2
+
+#define DCSR_EPU_EPSMCR15 0x278
+#define DCSR_EPU_EPECR0 0x300
+#define DCSR_RCPM_CG1CR0 0x31c
+#define DCSR_RCPM_CSTTACR0 0xb00
+
+#define CCSR_SCFG_DPSLPCR 0
+#define CCSR_SCFG_DPSLPCR_VAL 0x1
+#define CCSR_SCFG_PMCINTECR 0x160
+#define CCSR_SCFG_PMCINTLECR 0x164
+#define CCSR_SCFG_PMCINTSR 0x168
+#define CCSR_SCFG_SPARECR2 0x504
+#define CCSR_SCFG_SPARECR3 0x508
+
+#define CCSR_DCFG_CRSTSR 0x400
+#define CCSR_DCFG_CRSTSR_VAL 0x00000008
+
+#define CCSR_RCPM_POWMGTCSR 0x130
+#define CCSR_RCPM_POWMGTCSR_LPM20_REQ 0x00100000
+#define CCSR_RCPM_POWMGTCSR_LPM20_ST 0x00000200
+#define CCSR_RCPM_POWMGTCSR_P_LPM20_ST 0x00000100
+#define CCSR_RCPM_CLPCL10SETR 0x1c4
+#define CCSR_RCPM_CLPCL10SETR_C0 0x1
+#define CCSR_RCPM_IPPDEXPCR0 0x140
+#define CCSR_RCPM_IPPDEXPCR1 0x144
+
+#define QIXIS_CTL_SYS 0x5
+#define QIXIS_CTL_SYS_EVTSW_MASK 0x0c
+#define QIXIS_CTL_SYS_EVTSW_IRQ 0x04
+
+#define QIXIS_PWR_CTL2 0x21
+#define QIXIS_PWR_CTL2_PCTL 0x2
+
+#define OCRAM_BASE 0x10000000
+#define OCRAM_SIZE 0x10000 /* 64K */
+/* use the last page of SRAM */
+#define SRAM_CODE_BASE_PHY (OCRAM_BASE + OCRAM_SIZE - PAGE_SIZE)
+
+struct ls1_pm_baseaddr {
+ void __iomem *rcpm;
+ void __iomem *epu;
+ void __iomem *dcsr_rcpm1;
+ void __iomem *scfg;
+ void __iomem *dcfg;
+ void __iomem *fpga;
+ void __iomem *sram;
+};
+
+/* 128 bytes buffer for restoring data broke by DDR training initialization */
+#define DDR_BUF_SIZE 128
+static u8 ddr_buff[DDR_BUF_SIZE] __aligned(64);
+static struct ls1_pm_baseaddr ls1_pm_base;
+/* supported sleep modes by the present platform */
+static unsigned int sleep_modes;
+static suspend_state_t ls1_pm_state;
+
+static inline void ls1_clrsetbits_be32(void __iomem *addr, u32 mask, u32 val)
+{
+ u32 tmp;
+
+ tmp = ioread32be(addr);
+ tmp = (tmp & ~mask) | val;
+ iowrite32be(tmp, addr);
+}
+
+static void __iomem *of_iomap_str(const char *compatible)
+{
+ struct device_node *np;
+ void __iomem *base;
+
+ np = of_find_compatible_node(NULL, NULL, compatible);
+ if (!np) {
+ pr_err("%s: can not find the compatible \"%s\"\n",
+ __func__, compatible);
+ return NULL;
+ }
+
+ base = of_iomap(np, 0);
+ of_node_put(np);
+ if (!base)
+ return NULL;
+
+ return base;
+}
+
+static int ls1_pm_iomap(void)
+{
+ ls1_pm_base.epu = of_iomap_str("fsl,ls1021a-dcsr-epu");
+ ls1_pm_base.scfg = of_iomap_str("fsl,ls1021a-scfg");
+ ls1_pm_base.dcfg = of_iomap_str("fsl,ls1021a-dcfg");
+ ls1_pm_base.fpga = of_iomap_str("fsl,ls1021aqds-fpga");
+ ls1_pm_base.dcsr_rcpm1 = of_iomap_str("fsl,ls1021a-dcsr-rcpm");
+ ls1_pm_base.sram = ioremap(SRAM_CODE_BASE_PHY, PAGE_SIZE);
+ if (!ls1_pm_base.epu || !ls1_pm_base.scfg || !ls1_pm_base.dcfg ||
+ !ls1_pm_base.fpga || !ls1_pm_base.dcsr_rcpm1 || !ls1_pm_base.sram)
+ return -ENOMEM;
+
+ return 0;
+}
+
+static void ls1_pm_uniomap(void)
+{
+ iounmap(ls1_pm_base.epu);
+ iounmap(ls1_pm_base.dcsr_rcpm1);
+ iounmap(ls1_pm_base.scfg);
+ iounmap(ls1_pm_base.dcfg);
+ iounmap(ls1_pm_base.sram);
+ iounmap(ls1_pm_base.fpga);
+}
+
+static void ls1_save_ddr(void __iomem *base)
+{
+ u32 ddr_buff_addr;
+
+ /*
+ * DDR training initialization will break 128 bytes at the beginning
+ * of DDR, therefore, save them so that the bootloader will restore
+ * them. Assume that DDR is mapped to the address space started with
+ * CONFIG_PAGE_OFFSET.
+ */
+ memcpy(ddr_buff, (void *)CONFIG_PAGE_OFFSET, DDR_BUF_SIZE);
+
+ ddr_buff_addr = (u32)__pa(ddr_buff);
+
+ /*
+ * the bootloader will restore the first 128 bytes of DDR from
+ * the location indicated by the register SPARECR3
+ */
+ iowrite32(ddr_buff_addr, base + CCSR_SCFG_SPARECR3);
+}
+
+static void ls1_set_resume_entry(void __iomem *base)
+{
+ u32 resume_addr;
+
+ /* the bootloader will finally jump to this address to resume kernel */
+ resume_addr = (u32)(__pa(ls1_deepsleep_resume));
+
+ /* use the register SPARECR2 to save the return entry */
+ iowrite32(resume_addr, base + CCSR_SCFG_SPARECR2);
+}
+
+static void ls1_copy_sram_code(void)
+{
+ memcpy(ls1_pm_base.sram, ls1_start_fsm, ls1_sram_code_size);
+}
+
+static int ls1_start_deepsleep(unsigned long addr)
+{
+ /* Switch to the identity mapping */
+ setup_mm_for_reboot();
+ v7_exit_coherency_flush(all);
+
+ ls1_do_deepsleep(addr);
+
+ /* never get here */
+ BUG();
+
+ return 0;
+}
+
+static void ls1_fsm_setup(void)
+{
+ /* Request to put cluster 0 in PCL10 state */
+ ls1_clrsetbits_be32(ls1_pm_base.rcpm + CCSR_RCPM_CLPCL10SETR,
+ CCSR_RCPM_CLPCL10SETR_C0,
+ CCSR_RCPM_CLPCL10SETR_C0);
+
+ iowrite32be(0x00001001, ls1_pm_base.dcsr_rcpm1 + DCSR_RCPM_CSTTACR0);
+ iowrite32be(0x00000001, ls1_pm_base.dcsr_rcpm1 + DCSR_RCPM_CG1CR0);
+
+ fsl_epu_setup(ls1_pm_base.epu);
+
+ /*
+ * pull the MCKE signal(EVT4_B pin) low before enabling
+ * deep sleep signals by FPGA
+ */
+ iowrite32be(0x5, ls1_pm_base.epu + DCSR_EPU_EPECR0);
+
+ iowrite32be(0x76300000, ls1_pm_base.epu + DCSR_EPU_EPSMCR15);
+}
+
+static void ls1_board_suspend(void)
+{
+ u32 tmp;
+
+ /* connect the EVENT button to IRQ in FPGA */
+ tmp = ioread8(ls1_pm_base.fpga + QIXIS_CTL_SYS);
+ tmp &= ~QIXIS_CTL_SYS_EVTSW_MASK;
+ tmp |= QIXIS_CTL_SYS_EVTSW_IRQ;
+ iowrite8(tmp, ls1_pm_base.fpga + QIXIS_CTL_SYS);
+
+ /*
+ * enable deep sleep signals in FPGA
+ * Note that the MCKE signal(EVT4_B pin) should be pulled low (invalid)
+ * before enabling deep sleep signals.
+ */
+ tmp = ioread8(ls1_pm_base.fpga + QIXIS_PWR_CTL2);
+ iowrite8(tmp | QIXIS_PWR_CTL2_PCTL,
+ ls1_pm_base.fpga + QIXIS_PWR_CTL2);
+}
+
+static void ls1_board_resume(void)
+{
+ u32 tmp;
+
+ /* disable deep sleep signals in FPGA */
+ tmp = ioread8(ls1_pm_base.fpga + QIXIS_PWR_CTL2);
+ iowrite8(tmp & ~QIXIS_PWR_CTL2_PCTL,
+ ls1_pm_base.fpga + QIXIS_PWR_CTL2);
+
+ tmp = ioread8(ls1_pm_base.fpga + QIXIS_CTL_SYS);
+ tmp &= ~QIXIS_CTL_SYS_EVTSW_MASK;
+ iowrite8(tmp, ls1_pm_base.fpga + QIXIS_CTL_SYS);
+}
+
+static void ls1_enter_deepsleep(void)
+{
+ /* save DDR data */
+ ls1_save_ddr(ls1_pm_base.scfg);
+
+ /* save kernel resume entry */
+ ls1_set_resume_entry(ls1_pm_base.scfg);
+
+ /* setup the registers of the EPU FSM for deep sleep */
+ ls1_fsm_setup();
+
+ ls1_board_suspend();
+
+ /* enable Warm Device Reset */
+ ls1_clrsetbits_be32(ls1_pm_base.scfg + CCSR_SCFG_DPSLPCR,
+ CCSR_SCFG_DPSLPCR_VAL, CCSR_SCFG_DPSLPCR_VAL);
+
+ ls1_clrsetbits_be32(ls1_pm_base.dcfg + CCSR_DCFG_CRSTSR,
+ CCSR_DCFG_CRSTSR_VAL, CCSR_DCFG_CRSTSR_VAL);
+
+ /* copy the last stage code to sram */
+ ls1_copy_sram_code();
+
+ cpu_suspend(SRAM_CODE_BASE_PHY, ls1_start_deepsleep);
+
+ /* disable Warm Device Reset */
+ ls1_clrsetbits_be32(ls1_pm_base.scfg + CCSR_SCFG_DPSLPCR,
+ CCSR_SCFG_DPSLPCR_VAL, 0);
+
+ ls1_board_resume();
+}
+
+static int ls1_suspend_enter(suspend_state_t state)
+{
+ int ret = 0;
+
+ switch (state) {
+ case PM_SUSPEND_STANDBY:
+ flush_cache_louis();
+ ls1_clrsetbits_be32(ls1_pm_base.rcpm + CCSR_RCPM_POWMGTCSR,
+ CCSR_RCPM_POWMGTCSR_LPM20_REQ,
+ CCSR_RCPM_POWMGTCSR_LPM20_REQ);
+
+ cpu_do_idle();
+ break;
+
+ case PM_SUSPEND_MEM:
+ ls1_enter_deepsleep();
+ break;
+
+ default:
+ ret = -EINVAL;
+ }
+
+ return ret;
+}
+
+static int ls1_suspend_valid(suspend_state_t state)
+{
+ if ((state == PM_SUSPEND_STANDBY) && (sleep_modes & FSL_SLEEP))
+ return 1;
+
+ if ((state == PM_SUSPEND_MEM) && (sleep_modes & FSL_DEEP_SLEEP))
+ return 1;
+
+ return 0;
+}
+
+static int ls1_suspend_begin(suspend_state_t state)
+{
+ int ret = 0;
+
+ ls1_pm_state = state;
+
+ if (ls1_pm_state == PM_SUSPEND_MEM)
+ ret = ls1_pm_iomap();
+
+ return ret;
+}
+
+static void ls1_suspend_end(void)
+{
+ if (ls1_pm_state == PM_SUSPEND_MEM)
+ ls1_pm_uniomap();
+}
+
+static const struct platform_suspend_ops ls1_suspend_ops = {
+ .valid = ls1_suspend_valid,
+ .enter = ls1_suspend_enter,
+ .begin = ls1_suspend_begin,
+ .end = ls1_suspend_end,
+};
+
+static const struct of_device_id rcpm_matches[] = {
+ { .compatible = "fsl,ls1021a-rcpm", },
+ {}
+};
+
+static int __init ls1_pm_init(void)
+{
+ struct device_node *np;
+ struct property *prop;
+ void __iomem *base;
+
+ np = of_find_matching_node_and_match(NULL, rcpm_matches, NULL);
+ if (!np) {
+ pr_err("%s: can't find the RCPM node.\n", __func__);
+ return -EINVAL;
+ }
+
+ sleep_modes = FSL_SLEEP;
+ base = of_iomap(np, 0);
+ if (!base) {
+ of_node_put(np);
+ pr_err("%s: failed to map the register set of RCPM node.\n",
+ __func__);
+ return -ENOMEM;
+ }
+ ls1_pm_base.rcpm = base;
+
+ prop = of_find_property(np, "fsl,deep-sleep", NULL);
+ if (prop)
+ sleep_modes |= FSL_DEEP_SLEEP;
+ of_node_put(np);
+
+ suspend_set_ops(&ls1_suspend_ops);
+
+ return 0;
+}
+arch_initcall(ls1_pm_init);
diff --git a/arch/arm/mach-imx/sleep-ls1.S b/arch/arm/mach-imx/sleep-ls1.S
new file mode 100644
index 0000000..2020da6
--- /dev/null
+++ b/arch/arm/mach-imx/sleep-ls1.S
@@ -0,0 +1,137 @@
+/*
+ * Support deep sleep feature for LS1
+ *
+ * Copyright 2014-2015 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <asm/cache.h>
+#include <asm/cp15.h>
+
+#define CCSR_DDR_BASE 0x01080000
+#define CCSR_DDR_SDRAM_CFG_2 0x114
+
+#define CCSR_SCFG_BASE 0x01570000
+#define CCSR_SCFG_HRSTCR 0x1a8
+
+#define DCSR_EPU_BASE 0x20000000
+#define DCSR_EPU_EPGCR 0x0
+#define DCSR_EPU_EPECR0 0x300
+#define DCSR_EPU_EPECR15 0x33c
+
+/* for big endian registers */
+.macro ls1_set_bits, addr, value
+ ldr r4, \addr
+ ldr r5, [r4]
+ ldr r6, \value
+ rev r6, r6
+ orr r5, r5, r6
+ str r5, [r4]
+.endm
+
+/* 1000 loops per round */
+.macro ls1_delay, count
+ mov r0, \count
+11: mov r7, #1000
+12: subs r7, r7, #1
+ bne 12b
+ subs r0, r0, #1
+ bne 11b
+.endm
+
+/*
+ * r0: the physical entry address of SRAM code
+ */
+ .align L1_CACHE_SHIFT
+ .pushsection .idmap.text,"ax"
+ENTRY(ls1_do_deepsleep)
+ /* disable MMU, M bit in SCTLR */
+ mrc p15, 0, r3, c1, c0, 0
+ bic r3, r3, #CR_M
+ mcr p15, 0, r3, c1, c0, 0
+ isb
+
+ /* jump to the code in SRAM using physical address */
+ THUMB( orr r0, r0, #1 )
+ bx r0
+ENDPROC(ls1_do_deepsleep)
+ .popsection
+
+/*
+ * The code will run in SRAM.
+ */
+ .align L1_CACHE_SHIFT
+ENTRY(ls1_start_fsm)
+ /* set HRSTCR */
+ ls1_set_bits ls1_ccsr_scfg_hrstcr_addr, ls1_ccsr_scfg_hrstcr_val
+
+ /* Place DDR controller in self refresh mode */
+ ls1_set_bits ls1_ddr_cfg2_addr, ls1_ddr_cfg2_val
+
+ ls1_delay #2000
+
+ /* Set EVT4_B to lock the signal MCKE down */
+ ldr r4, ls1_dcsr_epu_epecr0
+ ldr r5, ls1_dcsr_epu_epecr0_val
+ rev r5, r5
+ str r5, [r4]
+
+ ls1_delay #2000
+
+ /* Enable all EPU Counters */
+ ls1_set_bits ls1_dcsr_epu_epgcr_addr, ls1_dcsr_epu_epgcr_val
+
+ /* Set SCU15 */
+ ldr r4, ls1_dcsr_epu_epecr15
+ ldr r5, ls1_dcsr_epu_epecr15_val
+ rev r5, r5
+ str r5, [r4]
+
+
+ /* Enter WFI mode, and EPU FSM will start */
+20: wfi
+ b 20b
+
+ls1_ccsr_scfg_hrstcr_addr:
+ .word CCSR_SCFG_BASE + CCSR_SCFG_HRSTCR
+ls1_ccsr_scfg_hrstcr_val:
+ .word 0x80000000
+
+ls1_ddr_cfg2_addr:
+ .word CCSR_DDR_BASE + CCSR_DDR_SDRAM_CFG_2
+ls1_ddr_cfg2_val:
+ .word (1 << 31)
+
+ls1_dcsr_epu_epecr0:
+ .word DCSR_EPU_BASE + DCSR_EPU_EPECR0
+ls1_dcsr_epu_epecr0_val:
+ .word 0
+
+ls1_dcsr_epu_epgcr_addr:
+ .word DCSR_EPU_BASE + DCSR_EPU_EPGCR
+ls1_dcsr_epu_epgcr_val:
+ .word 0x80000000
+
+ls1_dcsr_epu_epecr15:
+ .word DCSR_EPU_BASE + DCSR_EPU_EPECR15
+ls1_dcsr_epu_epecr15_val:
+ .word 0x90000004
+
+ENTRY(ls1_sram_code_size)
+ .word . - ls1_start_fsm
+
+/* the bootloader will jump to here after wakeup from deep sleep */
+ .arm
+ .align L1_CACHE_SHIFT
+ENTRY(ls1_deepsleep_resume)
+ THUMB( adr r6, BSYM(1f) )
+ THUMB( bx r6 )
+ THUMB( .thumb )
+ THUMB(1: )
+ b cpu_resume
diff --git a/arch/arm/mach-imx/sleep-ls1.h b/arch/arm/mach-imx/sleep-ls1.h
new file mode 100644
index 0000000..2d694ac
--- /dev/null
+++ b/arch/arm/mach-imx/sleep-ls1.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright 2014-2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __ARM_SLEEP_LS1_H
+#define __ARM_SLEEP_LS1_H
+
+void ls1_do_deepsleep(unsigned long addr);
+void ls1_start_fsm(void);
+void ls1_deepsleep_resume(void);
+void fsl_epu_setup(void __iomem *epu_base);
+
+extern int ls1_sram_code_size;
+
+#endif
--
1.9.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 3/4] arm: ls1021a: add deep sleep support
@ 2015-01-30 12:22 ` Chenhui Zhao
0 siblings, 0 replies; 8+ messages in thread
From: Chenhui Zhao @ 2015-01-30 12:22 UTC (permalink / raw)
To: linux-arm-kernel
The ls1021a SoC supports deep sleep feature that can switch off most
parts of the SoC when it is in deep sleep state.
The DDR controller will also be powered off in deep sleep. Therefore,
copy the last stage code to enter deep sleep to SRAM and run it
with disabling MMU and caches.
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
---
arch/arm/mach-imx/Kconfig | 1 +
arch/arm/mach-imx/Makefile | 2 +
arch/arm/mach-imx/pm-ls1.c | 374 ++++++++++++++++++++++++++++++++++++++++++
arch/arm/mach-imx/sleep-ls1.S | 137 ++++++++++++++++
arch/arm/mach-imx/sleep-ls1.h | 19 +++
5 files changed, 533 insertions(+)
create mode 100644 arch/arm/mach-imx/pm-ls1.c
create mode 100644 arch/arm/mach-imx/sleep-ls1.S
create mode 100644 arch/arm/mach-imx/sleep-ls1.h
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index e8627e0..c10acff 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -664,6 +664,7 @@ config SOC_LS1021A
select HAVE_ARM_ARCH_TIMER
select PCI_DOMAINS if PCI
select ZONE_DMA if ARM_LPAE
+ select FSL_SLEEP_FSM if PM
help
This enable support for Freescale LS1021A processor.
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index f5ac685..358adf4 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -101,6 +101,8 @@ obj-$(CONFIG_SOC_IMX6SX) += clk-imx6sx.o mach-imx6sx.o
ifeq ($(CONFIG_SUSPEND),y)
AFLAGS_suspend-imx6.o :=-Wa,-march=armv7-a
obj-$(CONFIG_SOC_IMX6) += suspend-imx6.o
+AFLAGS_sleep-ls1.o :=-Wa,-march=armv7-a
+obj-$(CONFIG_SOC_LS1021A) += pm-ls1.o sleep-ls1.o
endif
obj-$(CONFIG_SOC_IMX6) += pm-imx6.o
diff --git a/arch/arm/mach-imx/pm-ls1.c b/arch/arm/mach-imx/pm-ls1.c
new file mode 100644
index 0000000..4f9ca80
--- /dev/null
+++ b/arch/arm/mach-imx/pm-ls1.c
@@ -0,0 +1,374 @@
+/*
+ * Support deep sleep feature for LS1
+ *
+ * Copyright 2014-2015 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/suspend.h>
+#include <linux/io.h>
+#include <linux/of_platform.h>
+#include <linux/of_address.h>
+#include <linux/cpu_pm.h>
+#include <asm/suspend.h>
+#include <asm/delay.h>
+#include <asm/cp15.h>
+#include <asm/cacheflush.h>
+#include <asm/idmap.h>
+
+#include "common.h"
+#include "sleep-ls1.h"
+
+#define FSL_SLEEP 0x1
+#define FSL_DEEP_SLEEP 0x2
+
+#define DCSR_EPU_EPSMCR15 0x278
+#define DCSR_EPU_EPECR0 0x300
+#define DCSR_RCPM_CG1CR0 0x31c
+#define DCSR_RCPM_CSTTACR0 0xb00
+
+#define CCSR_SCFG_DPSLPCR 0
+#define CCSR_SCFG_DPSLPCR_VAL 0x1
+#define CCSR_SCFG_PMCINTECR 0x160
+#define CCSR_SCFG_PMCINTLECR 0x164
+#define CCSR_SCFG_PMCINTSR 0x168
+#define CCSR_SCFG_SPARECR2 0x504
+#define CCSR_SCFG_SPARECR3 0x508
+
+#define CCSR_DCFG_CRSTSR 0x400
+#define CCSR_DCFG_CRSTSR_VAL 0x00000008
+
+#define CCSR_RCPM_POWMGTCSR 0x130
+#define CCSR_RCPM_POWMGTCSR_LPM20_REQ 0x00100000
+#define CCSR_RCPM_POWMGTCSR_LPM20_ST 0x00000200
+#define CCSR_RCPM_POWMGTCSR_P_LPM20_ST 0x00000100
+#define CCSR_RCPM_CLPCL10SETR 0x1c4
+#define CCSR_RCPM_CLPCL10SETR_C0 0x1
+#define CCSR_RCPM_IPPDEXPCR0 0x140
+#define CCSR_RCPM_IPPDEXPCR1 0x144
+
+#define QIXIS_CTL_SYS 0x5
+#define QIXIS_CTL_SYS_EVTSW_MASK 0x0c
+#define QIXIS_CTL_SYS_EVTSW_IRQ 0x04
+
+#define QIXIS_PWR_CTL2 0x21
+#define QIXIS_PWR_CTL2_PCTL 0x2
+
+#define OCRAM_BASE 0x10000000
+#define OCRAM_SIZE 0x10000 /* 64K */
+/* use the last page of SRAM */
+#define SRAM_CODE_BASE_PHY (OCRAM_BASE + OCRAM_SIZE - PAGE_SIZE)
+
+struct ls1_pm_baseaddr {
+ void __iomem *rcpm;
+ void __iomem *epu;
+ void __iomem *dcsr_rcpm1;
+ void __iomem *scfg;
+ void __iomem *dcfg;
+ void __iomem *fpga;
+ void __iomem *sram;
+};
+
+/* 128 bytes buffer for restoring data broke by DDR training initialization */
+#define DDR_BUF_SIZE 128
+static u8 ddr_buff[DDR_BUF_SIZE] __aligned(64);
+static struct ls1_pm_baseaddr ls1_pm_base;
+/* supported sleep modes by the present platform */
+static unsigned int sleep_modes;
+static suspend_state_t ls1_pm_state;
+
+static inline void ls1_clrsetbits_be32(void __iomem *addr, u32 mask, u32 val)
+{
+ u32 tmp;
+
+ tmp = ioread32be(addr);
+ tmp = (tmp & ~mask) | val;
+ iowrite32be(tmp, addr);
+}
+
+static void __iomem *of_iomap_str(const char *compatible)
+{
+ struct device_node *np;
+ void __iomem *base;
+
+ np = of_find_compatible_node(NULL, NULL, compatible);
+ if (!np) {
+ pr_err("%s: can not find the compatible \"%s\"\n",
+ __func__, compatible);
+ return NULL;
+ }
+
+ base = of_iomap(np, 0);
+ of_node_put(np);
+ if (!base)
+ return NULL;
+
+ return base;
+}
+
+static int ls1_pm_iomap(void)
+{
+ ls1_pm_base.epu = of_iomap_str("fsl,ls1021a-dcsr-epu");
+ ls1_pm_base.scfg = of_iomap_str("fsl,ls1021a-scfg");
+ ls1_pm_base.dcfg = of_iomap_str("fsl,ls1021a-dcfg");
+ ls1_pm_base.fpga = of_iomap_str("fsl,ls1021aqds-fpga");
+ ls1_pm_base.dcsr_rcpm1 = of_iomap_str("fsl,ls1021a-dcsr-rcpm");
+ ls1_pm_base.sram = ioremap(SRAM_CODE_BASE_PHY, PAGE_SIZE);
+ if (!ls1_pm_base.epu || !ls1_pm_base.scfg || !ls1_pm_base.dcfg ||
+ !ls1_pm_base.fpga || !ls1_pm_base.dcsr_rcpm1 || !ls1_pm_base.sram)
+ return -ENOMEM;
+
+ return 0;
+}
+
+static void ls1_pm_uniomap(void)
+{
+ iounmap(ls1_pm_base.epu);
+ iounmap(ls1_pm_base.dcsr_rcpm1);
+ iounmap(ls1_pm_base.scfg);
+ iounmap(ls1_pm_base.dcfg);
+ iounmap(ls1_pm_base.sram);
+ iounmap(ls1_pm_base.fpga);
+}
+
+static void ls1_save_ddr(void __iomem *base)
+{
+ u32 ddr_buff_addr;
+
+ /*
+ * DDR training initialization will break 128 bytes at the beginning
+ * of DDR, therefore, save them so that the bootloader will restore
+ * them. Assume that DDR is mapped to the address space started with
+ * CONFIG_PAGE_OFFSET.
+ */
+ memcpy(ddr_buff, (void *)CONFIG_PAGE_OFFSET, DDR_BUF_SIZE);
+
+ ddr_buff_addr = (u32)__pa(ddr_buff);
+
+ /*
+ * the bootloader will restore the first 128 bytes of DDR from
+ * the location indicated by the register SPARECR3
+ */
+ iowrite32(ddr_buff_addr, base + CCSR_SCFG_SPARECR3);
+}
+
+static void ls1_set_resume_entry(void __iomem *base)
+{
+ u32 resume_addr;
+
+ /* the bootloader will finally jump to this address to resume kernel */
+ resume_addr = (u32)(__pa(ls1_deepsleep_resume));
+
+ /* use the register SPARECR2 to save the return entry */
+ iowrite32(resume_addr, base + CCSR_SCFG_SPARECR2);
+}
+
+static void ls1_copy_sram_code(void)
+{
+ memcpy(ls1_pm_base.sram, ls1_start_fsm, ls1_sram_code_size);
+}
+
+static int ls1_start_deepsleep(unsigned long addr)
+{
+ /* Switch to the identity mapping */
+ setup_mm_for_reboot();
+ v7_exit_coherency_flush(all);
+
+ ls1_do_deepsleep(addr);
+
+ /* never get here */
+ BUG();
+
+ return 0;
+}
+
+static void ls1_fsm_setup(void)
+{
+ /* Request to put cluster 0 in PCL10 state */
+ ls1_clrsetbits_be32(ls1_pm_base.rcpm + CCSR_RCPM_CLPCL10SETR,
+ CCSR_RCPM_CLPCL10SETR_C0,
+ CCSR_RCPM_CLPCL10SETR_C0);
+
+ iowrite32be(0x00001001, ls1_pm_base.dcsr_rcpm1 + DCSR_RCPM_CSTTACR0);
+ iowrite32be(0x00000001, ls1_pm_base.dcsr_rcpm1 + DCSR_RCPM_CG1CR0);
+
+ fsl_epu_setup(ls1_pm_base.epu);
+
+ /*
+ * pull the MCKE signal(EVT4_B pin) low before enabling
+ * deep sleep signals by FPGA
+ */
+ iowrite32be(0x5, ls1_pm_base.epu + DCSR_EPU_EPECR0);
+
+ iowrite32be(0x76300000, ls1_pm_base.epu + DCSR_EPU_EPSMCR15);
+}
+
+static void ls1_board_suspend(void)
+{
+ u32 tmp;
+
+ /* connect the EVENT button to IRQ in FPGA */
+ tmp = ioread8(ls1_pm_base.fpga + QIXIS_CTL_SYS);
+ tmp &= ~QIXIS_CTL_SYS_EVTSW_MASK;
+ tmp |= QIXIS_CTL_SYS_EVTSW_IRQ;
+ iowrite8(tmp, ls1_pm_base.fpga + QIXIS_CTL_SYS);
+
+ /*
+ * enable deep sleep signals in FPGA
+ * Note that the MCKE signal(EVT4_B pin) should be pulled low (invalid)
+ * before enabling deep sleep signals.
+ */
+ tmp = ioread8(ls1_pm_base.fpga + QIXIS_PWR_CTL2);
+ iowrite8(tmp | QIXIS_PWR_CTL2_PCTL,
+ ls1_pm_base.fpga + QIXIS_PWR_CTL2);
+}
+
+static void ls1_board_resume(void)
+{
+ u32 tmp;
+
+ /* disable deep sleep signals in FPGA */
+ tmp = ioread8(ls1_pm_base.fpga + QIXIS_PWR_CTL2);
+ iowrite8(tmp & ~QIXIS_PWR_CTL2_PCTL,
+ ls1_pm_base.fpga + QIXIS_PWR_CTL2);
+
+ tmp = ioread8(ls1_pm_base.fpga + QIXIS_CTL_SYS);
+ tmp &= ~QIXIS_CTL_SYS_EVTSW_MASK;
+ iowrite8(tmp, ls1_pm_base.fpga + QIXIS_CTL_SYS);
+}
+
+static void ls1_enter_deepsleep(void)
+{
+ /* save DDR data */
+ ls1_save_ddr(ls1_pm_base.scfg);
+
+ /* save kernel resume entry */
+ ls1_set_resume_entry(ls1_pm_base.scfg);
+
+ /* setup the registers of the EPU FSM for deep sleep */
+ ls1_fsm_setup();
+
+ ls1_board_suspend();
+
+ /* enable Warm Device Reset */
+ ls1_clrsetbits_be32(ls1_pm_base.scfg + CCSR_SCFG_DPSLPCR,
+ CCSR_SCFG_DPSLPCR_VAL, CCSR_SCFG_DPSLPCR_VAL);
+
+ ls1_clrsetbits_be32(ls1_pm_base.dcfg + CCSR_DCFG_CRSTSR,
+ CCSR_DCFG_CRSTSR_VAL, CCSR_DCFG_CRSTSR_VAL);
+
+ /* copy the last stage code to sram */
+ ls1_copy_sram_code();
+
+ cpu_suspend(SRAM_CODE_BASE_PHY, ls1_start_deepsleep);
+
+ /* disable Warm Device Reset */
+ ls1_clrsetbits_be32(ls1_pm_base.scfg + CCSR_SCFG_DPSLPCR,
+ CCSR_SCFG_DPSLPCR_VAL, 0);
+
+ ls1_board_resume();
+}
+
+static int ls1_suspend_enter(suspend_state_t state)
+{
+ int ret = 0;
+
+ switch (state) {
+ case PM_SUSPEND_STANDBY:
+ flush_cache_louis();
+ ls1_clrsetbits_be32(ls1_pm_base.rcpm + CCSR_RCPM_POWMGTCSR,
+ CCSR_RCPM_POWMGTCSR_LPM20_REQ,
+ CCSR_RCPM_POWMGTCSR_LPM20_REQ);
+
+ cpu_do_idle();
+ break;
+
+ case PM_SUSPEND_MEM:
+ ls1_enter_deepsleep();
+ break;
+
+ default:
+ ret = -EINVAL;
+ }
+
+ return ret;
+}
+
+static int ls1_suspend_valid(suspend_state_t state)
+{
+ if ((state == PM_SUSPEND_STANDBY) && (sleep_modes & FSL_SLEEP))
+ return 1;
+
+ if ((state == PM_SUSPEND_MEM) && (sleep_modes & FSL_DEEP_SLEEP))
+ return 1;
+
+ return 0;
+}
+
+static int ls1_suspend_begin(suspend_state_t state)
+{
+ int ret = 0;
+
+ ls1_pm_state = state;
+
+ if (ls1_pm_state == PM_SUSPEND_MEM)
+ ret = ls1_pm_iomap();
+
+ return ret;
+}
+
+static void ls1_suspend_end(void)
+{
+ if (ls1_pm_state == PM_SUSPEND_MEM)
+ ls1_pm_uniomap();
+}
+
+static const struct platform_suspend_ops ls1_suspend_ops = {
+ .valid = ls1_suspend_valid,
+ .enter = ls1_suspend_enter,
+ .begin = ls1_suspend_begin,
+ .end = ls1_suspend_end,
+};
+
+static const struct of_device_id rcpm_matches[] = {
+ { .compatible = "fsl,ls1021a-rcpm", },
+ {}
+};
+
+static int __init ls1_pm_init(void)
+{
+ struct device_node *np;
+ struct property *prop;
+ void __iomem *base;
+
+ np = of_find_matching_node_and_match(NULL, rcpm_matches, NULL);
+ if (!np) {
+ pr_err("%s: can't find the RCPM node.\n", __func__);
+ return -EINVAL;
+ }
+
+ sleep_modes = FSL_SLEEP;
+ base = of_iomap(np, 0);
+ if (!base) {
+ of_node_put(np);
+ pr_err("%s: failed to map the register set of RCPM node.\n",
+ __func__);
+ return -ENOMEM;
+ }
+ ls1_pm_base.rcpm = base;
+
+ prop = of_find_property(np, "fsl,deep-sleep", NULL);
+ if (prop)
+ sleep_modes |= FSL_DEEP_SLEEP;
+ of_node_put(np);
+
+ suspend_set_ops(&ls1_suspend_ops);
+
+ return 0;
+}
+arch_initcall(ls1_pm_init);
diff --git a/arch/arm/mach-imx/sleep-ls1.S b/arch/arm/mach-imx/sleep-ls1.S
new file mode 100644
index 0000000..2020da6
--- /dev/null
+++ b/arch/arm/mach-imx/sleep-ls1.S
@@ -0,0 +1,137 @@
+/*
+ * Support deep sleep feature for LS1
+ *
+ * Copyright 2014-2015 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <asm/cache.h>
+#include <asm/cp15.h>
+
+#define CCSR_DDR_BASE 0x01080000
+#define CCSR_DDR_SDRAM_CFG_2 0x114
+
+#define CCSR_SCFG_BASE 0x01570000
+#define CCSR_SCFG_HRSTCR 0x1a8
+
+#define DCSR_EPU_BASE 0x20000000
+#define DCSR_EPU_EPGCR 0x0
+#define DCSR_EPU_EPECR0 0x300
+#define DCSR_EPU_EPECR15 0x33c
+
+/* for big endian registers */
+.macro ls1_set_bits, addr, value
+ ldr r4, \addr
+ ldr r5, [r4]
+ ldr r6, \value
+ rev r6, r6
+ orr r5, r5, r6
+ str r5, [r4]
+.endm
+
+/* 1000 loops per round */
+.macro ls1_delay, count
+ mov r0, \count
+11: mov r7, #1000
+12: subs r7, r7, #1
+ bne 12b
+ subs r0, r0, #1
+ bne 11b
+.endm
+
+/*
+ * r0: the physical entry address of SRAM code
+ */
+ .align L1_CACHE_SHIFT
+ .pushsection .idmap.text,"ax"
+ENTRY(ls1_do_deepsleep)
+ /* disable MMU, M bit in SCTLR */
+ mrc p15, 0, r3, c1, c0, 0
+ bic r3, r3, #CR_M
+ mcr p15, 0, r3, c1, c0, 0
+ isb
+
+ /* jump to the code in SRAM using physical address */
+ THUMB( orr r0, r0, #1 )
+ bx r0
+ENDPROC(ls1_do_deepsleep)
+ .popsection
+
+/*
+ * The code will run in SRAM.
+ */
+ .align L1_CACHE_SHIFT
+ENTRY(ls1_start_fsm)
+ /* set HRSTCR */
+ ls1_set_bits ls1_ccsr_scfg_hrstcr_addr, ls1_ccsr_scfg_hrstcr_val
+
+ /* Place DDR controller in self refresh mode */
+ ls1_set_bits ls1_ddr_cfg2_addr, ls1_ddr_cfg2_val
+
+ ls1_delay #2000
+
+ /* Set EVT4_B to lock the signal MCKE down */
+ ldr r4, ls1_dcsr_epu_epecr0
+ ldr r5, ls1_dcsr_epu_epecr0_val
+ rev r5, r5
+ str r5, [r4]
+
+ ls1_delay #2000
+
+ /* Enable all EPU Counters */
+ ls1_set_bits ls1_dcsr_epu_epgcr_addr, ls1_dcsr_epu_epgcr_val
+
+ /* Set SCU15 */
+ ldr r4, ls1_dcsr_epu_epecr15
+ ldr r5, ls1_dcsr_epu_epecr15_val
+ rev r5, r5
+ str r5, [r4]
+
+
+ /* Enter WFI mode, and EPU FSM will start */
+20: wfi
+ b 20b
+
+ls1_ccsr_scfg_hrstcr_addr:
+ .word CCSR_SCFG_BASE + CCSR_SCFG_HRSTCR
+ls1_ccsr_scfg_hrstcr_val:
+ .word 0x80000000
+
+ls1_ddr_cfg2_addr:
+ .word CCSR_DDR_BASE + CCSR_DDR_SDRAM_CFG_2
+ls1_ddr_cfg2_val:
+ .word (1 << 31)
+
+ls1_dcsr_epu_epecr0:
+ .word DCSR_EPU_BASE + DCSR_EPU_EPECR0
+ls1_dcsr_epu_epecr0_val:
+ .word 0
+
+ls1_dcsr_epu_epgcr_addr:
+ .word DCSR_EPU_BASE + DCSR_EPU_EPGCR
+ls1_dcsr_epu_epgcr_val:
+ .word 0x80000000
+
+ls1_dcsr_epu_epecr15:
+ .word DCSR_EPU_BASE + DCSR_EPU_EPECR15
+ls1_dcsr_epu_epecr15_val:
+ .word 0x90000004
+
+ENTRY(ls1_sram_code_size)
+ .word . - ls1_start_fsm
+
+/* the bootloader will jump to here after wakeup from deep sleep */
+ .arm
+ .align L1_CACHE_SHIFT
+ENTRY(ls1_deepsleep_resume)
+ THUMB( adr r6, BSYM(1f) )
+ THUMB( bx r6 )
+ THUMB( .thumb )
+ THUMB(1: )
+ b cpu_resume
diff --git a/arch/arm/mach-imx/sleep-ls1.h b/arch/arm/mach-imx/sleep-ls1.h
new file mode 100644
index 0000000..2d694ac
--- /dev/null
+++ b/arch/arm/mach-imx/sleep-ls1.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright 2014-2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __ARM_SLEEP_LS1_H
+#define __ARM_SLEEP_LS1_H
+
+void ls1_do_deepsleep(unsigned long addr);
+void ls1_start_fsm(void);
+void ls1_deepsleep_resume(void);
+void fsl_epu_setup(void __iomem *epu_base);
+
+extern int ls1_sram_code_size;
+
+#endif
--
1.9.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 4/4] arm: ls1021a: set wakeup devices dynamically for sleep/deep sleep
2015-01-30 12:22 ` Chenhui Zhao
@ 2015-01-30 12:22 ` Chenhui Zhao
-1 siblings, 0 replies; 8+ messages in thread
From: Chenhui Zhao @ 2015-01-30 12:22 UTC (permalink / raw)
To: linux-kernel, kernel, linux-arm-kernel; +Cc: leoli, Jason.Jin
If a device works as a wakeup source, it will keep working in the period of
sleep/deep sleep. This patch sets the wakeup devices according to the wakeup
attribute of device.
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
---
arch/arm/boot/dts/ls1021a.dtsi | 2 +
arch/arm/mach-imx/pm-ls1.c | 101 +++++++++++++++++++++++++++++++++++++++++
2 files changed, 103 insertions(+)
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 0c51ce0..64534c0 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -136,6 +136,7 @@
sdhci,auto-cmd12;
big-endian;
bus-width = <4>;
+ sleep = <&rcpm 0x00000080 0x0>;
status = "disabled";
};
@@ -289,6 +290,7 @@
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sysclk>;
clock-names = "ipg";
+ sleep = <&rcpm 0x0 0x40000000>;
status = "disabled";
};
diff --git a/arch/arm/mach-imx/pm-ls1.c b/arch/arm/mach-imx/pm-ls1.c
index 4f9ca80..b11fcb2 100644
--- a/arch/arm/mach-imx/pm-ls1.c
+++ b/arch/arm/mach-imx/pm-ls1.c
@@ -35,6 +35,13 @@
#define CCSR_SCFG_DPSLPCR 0
#define CCSR_SCFG_DPSLPCR_VAL 0x1
#define CCSR_SCFG_PMCINTECR 0x160
+#define CCSR_SCFG_PMCINTECR_LPUART 0x40000000
+#define CCSR_SCFG_PMCINTECR_FTM 0x20000000
+#define CCSR_SCFG_PMCINTECR_GPIO 0x10000000
+#define CCSR_SCFG_PMCINTECR_IRQ0 0x08000000
+#define CCSR_SCFG_PMCINTECR_IRQ1 0x04000000
+#define CCSR_SCFG_PMCINTECR_ETSECRXG0 0x00800000
+#define CCSR_SCFG_PMCINTECR_ETSECRXG1 0x00400000
#define CCSR_SCFG_PMCINTLECR 0x164
#define CCSR_SCFG_PMCINTSR 0x168
#define CCSR_SCFG_SPARECR2 0x504
@@ -50,7 +57,11 @@
#define CCSR_RCPM_CLPCL10SETR 0x1c4
#define CCSR_RCPM_CLPCL10SETR_C0 0x1
#define CCSR_RCPM_IPPDEXPCR0 0x140
+#define CCSR_RCPM_IPPDEXPCR0_ETSEC 0x80000000
+#define CCSR_RCPM_IPPDEXPCR0_GPIO 0x00000040
#define CCSR_RCPM_IPPDEXPCR1 0x144
+#define CCSR_RCPM_IPPDEXPCR1_LPUART 0x40000000
+#define CCSR_RCPM_IPPDEXPCR1_FLEXTIMER 0x20000000
#define QIXIS_CTL_SYS 0x5
#define QIXIS_CTL_SYS_EVTSW_MASK 0x0c
@@ -64,6 +75,10 @@
/* use the last page of SRAM */
#define SRAM_CODE_BASE_PHY (OCRAM_BASE + OCRAM_SIZE - PAGE_SIZE)
+#define SLEEP_ARRAY_SIZE 3
+
+static u32 ippdexpcr0, ippdexpcr1;
+
struct ls1_pm_baseaddr {
void __iomem *rcpm;
void __iomem *epu;
@@ -242,6 +257,49 @@ static void ls1_board_resume(void)
iowrite8(tmp, ls1_pm_base.fpga + QIXIS_CTL_SYS);
}
+static void ls1_setup_pmc_int(void)
+{
+ u32 pmcintecr;
+
+ pmcintecr = 0;
+ if (ippdexpcr0 & CCSR_RCPM_IPPDEXPCR0_ETSEC)
+ pmcintecr |= CCSR_SCFG_PMCINTECR_ETSECRXG0 |
+ CCSR_SCFG_PMCINTECR_ETSECRXG1;
+
+ if (ippdexpcr0 & CCSR_RCPM_IPPDEXPCR0_GPIO)
+ pmcintecr |= CCSR_SCFG_PMCINTECR_GPIO;
+
+ if (ippdexpcr1 & CCSR_RCPM_IPPDEXPCR1_LPUART)
+ pmcintecr |= CCSR_SCFG_PMCINTECR_LPUART;
+
+ if (ippdexpcr1 & CCSR_RCPM_IPPDEXPCR1_FLEXTIMER)
+ pmcintecr |= CCSR_SCFG_PMCINTECR_FTM;
+
+ /* always set external IRQ pins as wakeup source */
+ pmcintecr |= CCSR_SCFG_PMCINTECR_IRQ0 | CCSR_SCFG_PMCINTECR_IRQ1;
+
+ /* enable wakeup interrupt during deep sleep */
+ iowrite32be(pmcintecr, ls1_pm_base.scfg + CCSR_SCFG_PMCINTECR);
+ iowrite32be(0, ls1_pm_base.scfg + CCSR_SCFG_PMCINTLECR);
+ /* clear PMC interrupt status */
+ iowrite32be(0xffffffff, ls1_pm_base.scfg + CCSR_SCFG_PMCINTSR);
+}
+
+static void ls1_clear_pmc_int(void)
+{
+ /* disable wakeup interrupt during deep sleep */
+ iowrite32be(0, ls1_pm_base.scfg + CCSR_SCFG_PMCINTECR);
+ /* clear PMC interrupt status */
+ iowrite32be(0xffffffff, ls1_pm_base.scfg + CCSR_SCFG_PMCINTSR);
+}
+
+/* set IP powerdown exception, make them work during sleep/deep sleep */
+static void ls1_set_powerdown(void)
+{
+ iowrite32be(ippdexpcr0, ls1_pm_base.rcpm + CCSR_RCPM_IPPDEXPCR0);
+ iowrite32be(ippdexpcr1, ls1_pm_base.rcpm + CCSR_RCPM_IPPDEXPCR1);
+}
+
static void ls1_enter_deepsleep(void)
{
/* save DDR data */
@@ -265,8 +323,12 @@ static void ls1_enter_deepsleep(void)
/* copy the last stage code to sram */
ls1_copy_sram_code();
+ ls1_setup_pmc_int();
+
cpu_suspend(SRAM_CODE_BASE_PHY, ls1_start_deepsleep);
+ ls1_clear_pmc_int();
+
/* disable Warm Device Reset */
ls1_clrsetbits_be32(ls1_pm_base.scfg + CCSR_SCFG_DPSLPCR,
CCSR_SCFG_DPSLPCR_VAL, 0);
@@ -274,10 +336,45 @@ static void ls1_enter_deepsleep(void)
ls1_board_resume();
}
+static void ls1_set_power_except(struct device *dev, int on)
+{
+ int ret;
+ u32 value[SLEEP_ARRAY_SIZE];
+
+ /*
+ * Get the values in the "sleep" property. There are three values.
+ * The first points to the RCPM node, the second is the value of
+ * the ippdexpcr0 register, and the third is the value of
+ * the ippdexpcr1 register.
+ */
+ ret = of_property_read_u32_array(dev->of_node, "sleep",
+ value, SLEEP_ARRAY_SIZE);
+ if (ret) {
+ dev_err(dev, "%s: Can not find the \"sleep\" property.\n",
+ __func__);
+ return;
+ }
+
+ ippdexpcr0 |= value[1];
+ ippdexpcr1 |= value[2];
+
+ pr_debug("%s: set %s as a wakeup source", __func__,
+ dev->of_node->full_name);
+}
+
+static void ls1_set_wakeup_device(struct device *dev, void *enable)
+{
+ /* set each device which can act as wakeup source */
+ if (device_may_wakeup(dev))
+ ls1_set_power_except(dev, *((int *)enable));
+}
+
static int ls1_suspend_enter(suspend_state_t state)
{
int ret = 0;
+ ls1_set_powerdown();
+
switch (state) {
case PM_SUSPEND_STANDBY:
flush_cache_louis();
@@ -316,6 +413,10 @@ static int ls1_suspend_begin(suspend_state_t state)
ls1_pm_state = state;
+ ippdexpcr0 = 0;
+ ippdexpcr1 = 0;
+ dpm_for_each_dev(NULL, ls1_set_wakeup_device);
+
if (ls1_pm_state == PM_SUSPEND_MEM)
ret = ls1_pm_iomap();
--
1.9.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 4/4] arm: ls1021a: set wakeup devices dynamically for sleep/deep sleep
@ 2015-01-30 12:22 ` Chenhui Zhao
0 siblings, 0 replies; 8+ messages in thread
From: Chenhui Zhao @ 2015-01-30 12:22 UTC (permalink / raw)
To: linux-arm-kernel
If a device works as a wakeup source, it will keep working in the period of
sleep/deep sleep. This patch sets the wakeup devices according to the wakeup
attribute of device.
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
---
arch/arm/boot/dts/ls1021a.dtsi | 2 +
arch/arm/mach-imx/pm-ls1.c | 101 +++++++++++++++++++++++++++++++++++++++++
2 files changed, 103 insertions(+)
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 0c51ce0..64534c0 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -136,6 +136,7 @@
sdhci,auto-cmd12;
big-endian;
bus-width = <4>;
+ sleep = <&rcpm 0x00000080 0x0>;
status = "disabled";
};
@@ -289,6 +290,7 @@
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sysclk>;
clock-names = "ipg";
+ sleep = <&rcpm 0x0 0x40000000>;
status = "disabled";
};
diff --git a/arch/arm/mach-imx/pm-ls1.c b/arch/arm/mach-imx/pm-ls1.c
index 4f9ca80..b11fcb2 100644
--- a/arch/arm/mach-imx/pm-ls1.c
+++ b/arch/arm/mach-imx/pm-ls1.c
@@ -35,6 +35,13 @@
#define CCSR_SCFG_DPSLPCR 0
#define CCSR_SCFG_DPSLPCR_VAL 0x1
#define CCSR_SCFG_PMCINTECR 0x160
+#define CCSR_SCFG_PMCINTECR_LPUART 0x40000000
+#define CCSR_SCFG_PMCINTECR_FTM 0x20000000
+#define CCSR_SCFG_PMCINTECR_GPIO 0x10000000
+#define CCSR_SCFG_PMCINTECR_IRQ0 0x08000000
+#define CCSR_SCFG_PMCINTECR_IRQ1 0x04000000
+#define CCSR_SCFG_PMCINTECR_ETSECRXG0 0x00800000
+#define CCSR_SCFG_PMCINTECR_ETSECRXG1 0x00400000
#define CCSR_SCFG_PMCINTLECR 0x164
#define CCSR_SCFG_PMCINTSR 0x168
#define CCSR_SCFG_SPARECR2 0x504
@@ -50,7 +57,11 @@
#define CCSR_RCPM_CLPCL10SETR 0x1c4
#define CCSR_RCPM_CLPCL10SETR_C0 0x1
#define CCSR_RCPM_IPPDEXPCR0 0x140
+#define CCSR_RCPM_IPPDEXPCR0_ETSEC 0x80000000
+#define CCSR_RCPM_IPPDEXPCR0_GPIO 0x00000040
#define CCSR_RCPM_IPPDEXPCR1 0x144
+#define CCSR_RCPM_IPPDEXPCR1_LPUART 0x40000000
+#define CCSR_RCPM_IPPDEXPCR1_FLEXTIMER 0x20000000
#define QIXIS_CTL_SYS 0x5
#define QIXIS_CTL_SYS_EVTSW_MASK 0x0c
@@ -64,6 +75,10 @@
/* use the last page of SRAM */
#define SRAM_CODE_BASE_PHY (OCRAM_BASE + OCRAM_SIZE - PAGE_SIZE)
+#define SLEEP_ARRAY_SIZE 3
+
+static u32 ippdexpcr0, ippdexpcr1;
+
struct ls1_pm_baseaddr {
void __iomem *rcpm;
void __iomem *epu;
@@ -242,6 +257,49 @@ static void ls1_board_resume(void)
iowrite8(tmp, ls1_pm_base.fpga + QIXIS_CTL_SYS);
}
+static void ls1_setup_pmc_int(void)
+{
+ u32 pmcintecr;
+
+ pmcintecr = 0;
+ if (ippdexpcr0 & CCSR_RCPM_IPPDEXPCR0_ETSEC)
+ pmcintecr |= CCSR_SCFG_PMCINTECR_ETSECRXG0 |
+ CCSR_SCFG_PMCINTECR_ETSECRXG1;
+
+ if (ippdexpcr0 & CCSR_RCPM_IPPDEXPCR0_GPIO)
+ pmcintecr |= CCSR_SCFG_PMCINTECR_GPIO;
+
+ if (ippdexpcr1 & CCSR_RCPM_IPPDEXPCR1_LPUART)
+ pmcintecr |= CCSR_SCFG_PMCINTECR_LPUART;
+
+ if (ippdexpcr1 & CCSR_RCPM_IPPDEXPCR1_FLEXTIMER)
+ pmcintecr |= CCSR_SCFG_PMCINTECR_FTM;
+
+ /* always set external IRQ pins as wakeup source */
+ pmcintecr |= CCSR_SCFG_PMCINTECR_IRQ0 | CCSR_SCFG_PMCINTECR_IRQ1;
+
+ /* enable wakeup interrupt during deep sleep */
+ iowrite32be(pmcintecr, ls1_pm_base.scfg + CCSR_SCFG_PMCINTECR);
+ iowrite32be(0, ls1_pm_base.scfg + CCSR_SCFG_PMCINTLECR);
+ /* clear PMC interrupt status */
+ iowrite32be(0xffffffff, ls1_pm_base.scfg + CCSR_SCFG_PMCINTSR);
+}
+
+static void ls1_clear_pmc_int(void)
+{
+ /* disable wakeup interrupt during deep sleep */
+ iowrite32be(0, ls1_pm_base.scfg + CCSR_SCFG_PMCINTECR);
+ /* clear PMC interrupt status */
+ iowrite32be(0xffffffff, ls1_pm_base.scfg + CCSR_SCFG_PMCINTSR);
+}
+
+/* set IP powerdown exception, make them work during sleep/deep sleep */
+static void ls1_set_powerdown(void)
+{
+ iowrite32be(ippdexpcr0, ls1_pm_base.rcpm + CCSR_RCPM_IPPDEXPCR0);
+ iowrite32be(ippdexpcr1, ls1_pm_base.rcpm + CCSR_RCPM_IPPDEXPCR1);
+}
+
static void ls1_enter_deepsleep(void)
{
/* save DDR data */
@@ -265,8 +323,12 @@ static void ls1_enter_deepsleep(void)
/* copy the last stage code to sram */
ls1_copy_sram_code();
+ ls1_setup_pmc_int();
+
cpu_suspend(SRAM_CODE_BASE_PHY, ls1_start_deepsleep);
+ ls1_clear_pmc_int();
+
/* disable Warm Device Reset */
ls1_clrsetbits_be32(ls1_pm_base.scfg + CCSR_SCFG_DPSLPCR,
CCSR_SCFG_DPSLPCR_VAL, 0);
@@ -274,10 +336,45 @@ static void ls1_enter_deepsleep(void)
ls1_board_resume();
}
+static void ls1_set_power_except(struct device *dev, int on)
+{
+ int ret;
+ u32 value[SLEEP_ARRAY_SIZE];
+
+ /*
+ * Get the values in the "sleep" property. There are three values.
+ * The first points to the RCPM node, the second is the value of
+ * the ippdexpcr0 register, and the third is the value of
+ * the ippdexpcr1 register.
+ */
+ ret = of_property_read_u32_array(dev->of_node, "sleep",
+ value, SLEEP_ARRAY_SIZE);
+ if (ret) {
+ dev_err(dev, "%s: Can not find the \"sleep\" property.\n",
+ __func__);
+ return;
+ }
+
+ ippdexpcr0 |= value[1];
+ ippdexpcr1 |= value[2];
+
+ pr_debug("%s: set %s as a wakeup source", __func__,
+ dev->of_node->full_name);
+}
+
+static void ls1_set_wakeup_device(struct device *dev, void *enable)
+{
+ /* set each device which can act as wakeup source */
+ if (device_may_wakeup(dev))
+ ls1_set_power_except(dev, *((int *)enable));
+}
+
static int ls1_suspend_enter(suspend_state_t state)
{
int ret = 0;
+ ls1_set_powerdown();
+
switch (state) {
case PM_SUSPEND_STANDBY:
flush_cache_louis();
@@ -316,6 +413,10 @@ static int ls1_suspend_begin(suspend_state_t state)
ls1_pm_state = state;
+ ippdexpcr0 = 0;
+ ippdexpcr1 = 0;
+ dpm_for_each_dev(NULL, ls1_set_wakeup_device);
+
if (ls1_pm_state == PM_SUSPEND_MEM)
ret = ls1_pm_iomap();
--
1.9.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
end of thread, other threads:[~2015-01-30 12:55 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-01-30 12:22 [PATCH 1/4] fsl: add EPU FSM configuration for deep sleep Chenhui Zhao
2015-01-30 12:22 ` Chenhui Zhao
2015-01-30 12:22 ` [PATCH 2/4] arm: ls1021a: add dts nodes required by " Chenhui Zhao
2015-01-30 12:22 ` Chenhui Zhao
2015-01-30 12:22 ` [PATCH 3/4] arm: ls1021a: add deep sleep support Chenhui Zhao
2015-01-30 12:22 ` Chenhui Zhao
2015-01-30 12:22 ` [PATCH 4/4] arm: ls1021a: set wakeup devices dynamically for sleep/deep sleep Chenhui Zhao
2015-01-30 12:22 ` Chenhui Zhao
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