From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1161446AbbBDPbS (ORCPT ); Wed, 4 Feb 2015 10:31:18 -0500 Received: from mailapp01.imgtec.com ([195.59.15.196]:25560 "EHLO mailapp01.imgtec.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S966513AbbBDPWk (ORCPT ); Wed, 4 Feb 2015 10:22:40 -0500 From: Zubair Lutfullah Kakakhel To: CC: , , , , , , , , , , , , Subject: [PATCH_V2 18/34] MIPS: clk: move jz4740 UDC auto suspend functions to jz4740-cgu Date: Wed, 4 Feb 2015 15:21:47 +0000 Message-ID: <1423063323-19419-19-git-send-email-Zubair.Kakakhel@imgtec.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1423063323-19419-1-git-send-email-Zubair.Kakakhel@imgtec.com> References: <1423063323-19419-1-git-send-email-Zubair.Kakakhel@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [192.168.154.89] Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Paul Burton The jz4740-cgu driver already has access to the CGU, so it makes sense to move the few remaining accesses to the CGU from arch/mips/jz4740 there too. Move the jz4740_clock_udc_{dis,en}able_auto_suspend functions there for such consistency. Signed-off-by: Paul Burton Cc: Lars-Peter Clausen Cc: Mike Turquette --- arch/mips/jz4740/clock.c | 13 ------------- drivers/clk/jz47xx/jz4740-cgu.c | 20 ++++++++++++++++++++ 2 files changed, 20 insertions(+), 13 deletions(-) diff --git a/arch/mips/jz4740/clock.c b/arch/mips/jz4740/clock.c index 90b44d7..2a10829 100644 --- a/arch/mips/jz4740/clock.c +++ b/arch/mips/jz4740/clock.c @@ -33,7 +33,6 @@ #define JZ_CLOCK_GATE_UART0 BIT(0) #define JZ_CLOCK_GATE_TCU BIT(1) -#define JZ_CLOCK_GATE_UDC BIT(11) #define JZ_CLOCK_GATE_DMAC BIT(12) #define JZ_CLOCK_PLL_STABLE BIT(10) @@ -64,18 +63,6 @@ static void jz_clk_reg_clear_bits(int reg, uint32_t mask) writel(val, jz_clock_base + reg); } -void jz4740_clock_udc_disable_auto_suspend(void) -{ - jz_clk_reg_clear_bits(JZ_REG_CLOCK_GATE, JZ_CLOCK_GATE_UDC); -} -EXPORT_SYMBOL_GPL(jz4740_clock_udc_disable_auto_suspend); - -void jz4740_clock_udc_enable_auto_suspend(void) -{ - jz_clk_reg_set_bits(JZ_REG_CLOCK_GATE, JZ_CLOCK_GATE_UDC); -} -EXPORT_SYMBOL_GPL(jz4740_clock_udc_enable_auto_suspend); - void jz4740_clock_suspend(void) { jz_clk_reg_set_bits(JZ_REG_CLOCK_GATE, diff --git a/drivers/clk/jz47xx/jz4740-cgu.c b/drivers/clk/jz47xx/jz4740-cgu.c index ef559e7..46b6c1a 100644 --- a/drivers/clk/jz47xx/jz4740-cgu.c +++ b/drivers/clk/jz47xx/jz4740-cgu.c @@ -27,6 +27,7 @@ #define CGU_REG_CPCCR 0x00 #define CGU_REG_LCR 0x04 #define CGU_REG_CPPCR 0x10 +#define CGU_REG_CLKGR 0x20 #define CGU_REG_I2SCDR 0x60 #define CGU_REG_LPCDR 0x64 #define CGU_REG_MSCCDR 0x68 @@ -47,6 +48,9 @@ /* bits within the LCR register */ #define LCR_SLEEP (1 << 0) +/* bits within the CLKGR register */ +#define CLKGR_UDC (1 << 11) + static struct jz47xx_cgu *cgu; static const s8 pll_od_encoding[4] = { @@ -239,3 +243,19 @@ void jz4740_clock_set_wait_mode(enum jz4740_wait_mode mode) writel(lcr, cgu->base + CGU_REG_LCR); } + +void jz4740_clock_udc_disable_auto_suspend(void) +{ + uint32_t clkgr = readl(cgu->base + CGU_REG_CLKGR); + clkgr &= ~CLKGR_UDC; + writel(clkgr, cgu->base + CGU_REG_CLKGR); +} +EXPORT_SYMBOL_GPL(jz4740_clock_udc_disable_auto_suspend); + +void jz4740_clock_udc_enable_auto_suspend(void) +{ + uint32_t clkgr = readl(cgu->base + CGU_REG_CLKGR); + clkgr |= CLKGR_UDC; + writel(clkgr, cgu->base + CGU_REG_CLKGR); +} +EXPORT_SYMBOL_GPL(jz4740_clock_udc_enable_auto_suspend); -- 1.9.1 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Zubair Lutfullah Kakakhel Subject: [PATCH_V2 18/34] MIPS: clk: move jz4740 UDC auto suspend functions to jz4740-cgu Date: Wed, 4 Feb 2015 15:21:47 +0000 Message-ID: <1423063323-19419-19-git-send-email-Zubair.Kakakhel@imgtec.com> References: <1423063323-19419-1-git-send-email-Zubair.Kakakhel@imgtec.com> Mime-Version: 1.0 Content-Type: text/plain Return-path: In-Reply-To: <1423063323-19419-1-git-send-email-Zubair.Kakakhel@imgtec.com> Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-subscribe: List-owner: List-post: List-archive: To: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org, Zubair.Kakakhel@imgtec.com, gregkh@linuxfoundation.org, mturquette@linaro.org, sboyd@codeaurora.org, ralf@linux-mips.org, jslaby@suse.cz, tglx@linutronix.de, jason@lakedaemon.net, lars@metafoo.de, paul.burton@imgtec.com List-Id: devicetree@vger.kernel.org From: Paul Burton The jz4740-cgu driver already has access to the CGU, so it makes sense to move the few remaining accesses to the CGU from arch/mips/jz4740 there too. Move the jz4740_clock_udc_{dis,en}able_auto_suspend functions there for such consistency. Signed-off-by: Paul Burton Cc: Lars-Peter Clausen Cc: Mike Turquette --- arch/mips/jz4740/clock.c | 13 ------------- drivers/clk/jz47xx/jz4740-cgu.c | 20 ++++++++++++++++++++ 2 files changed, 20 insertions(+), 13 deletions(-) diff --git a/arch/mips/jz4740/clock.c b/arch/mips/jz4740/clock.c index 90b44d7..2a10829 100644 --- a/arch/mips/jz4740/clock.c +++ b/arch/mips/jz4740/clock.c @@ -33,7 +33,6 @@ #define JZ_CLOCK_GATE_UART0 BIT(0) #define JZ_CLOCK_GATE_TCU BIT(1) -#define JZ_CLOCK_GATE_UDC BIT(11) #define JZ_CLOCK_GATE_DMAC BIT(12) #define JZ_CLOCK_PLL_STABLE BIT(10) @@ -64,18 +63,6 @@ static void jz_clk_reg_clear_bits(int reg, uint32_t mask) writel(val, jz_clock_base + reg); } -void jz4740_clock_udc_disable_auto_suspend(void) -{ - jz_clk_reg_clear_bits(JZ_REG_CLOCK_GATE, JZ_CLOCK_GATE_UDC); -} -EXPORT_SYMBOL_GPL(jz4740_clock_udc_disable_auto_suspend); - -void jz4740_clock_udc_enable_auto_suspend(void) -{ - jz_clk_reg_set_bits(JZ_REG_CLOCK_GATE, JZ_CLOCK_GATE_UDC); -} -EXPORT_SYMBOL_GPL(jz4740_clock_udc_enable_auto_suspend); - void jz4740_clock_suspend(void) { jz_clk_reg_set_bits(JZ_REG_CLOCK_GATE, diff --git a/drivers/clk/jz47xx/jz4740-cgu.c b/drivers/clk/jz47xx/jz4740-cgu.c index ef559e7..46b6c1a 100644 --- a/drivers/clk/jz47xx/jz4740-cgu.c +++ b/drivers/clk/jz47xx/jz4740-cgu.c @@ -27,6 +27,7 @@ #define CGU_REG_CPCCR 0x00 #define CGU_REG_LCR 0x04 #define CGU_REG_CPPCR 0x10 +#define CGU_REG_CLKGR 0x20 #define CGU_REG_I2SCDR 0x60 #define CGU_REG_LPCDR 0x64 #define CGU_REG_MSCCDR 0x68 @@ -47,6 +48,9 @@ /* bits within the LCR register */ #define LCR_SLEEP (1 << 0) +/* bits within the CLKGR register */ +#define CLKGR_UDC (1 << 11) + static struct jz47xx_cgu *cgu; static const s8 pll_od_encoding[4] = { @@ -239,3 +243,19 @@ void jz4740_clock_set_wait_mode(enum jz4740_wait_mode mode) writel(lcr, cgu->base + CGU_REG_LCR); } + +void jz4740_clock_udc_disable_auto_suspend(void) +{ + uint32_t clkgr = readl(cgu->base + CGU_REG_CLKGR); + clkgr &= ~CLKGR_UDC; + writel(clkgr, cgu->base + CGU_REG_CLKGR); +} +EXPORT_SYMBOL_GPL(jz4740_clock_udc_disable_auto_suspend); + +void jz4740_clock_udc_enable_auto_suspend(void) +{ + uint32_t clkgr = readl(cgu->base + CGU_REG_CLKGR); + clkgr |= CLKGR_UDC; + writel(clkgr, cgu->base + CGU_REG_CLKGR); +} +EXPORT_SYMBOL_GPL(jz4740_clock_udc_enable_auto_suspend); -- 1.9.1