From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S966526AbbBDPWk (ORCPT ); Wed, 4 Feb 2015 10:22:40 -0500 Received: from mailapp01.imgtec.com ([195.59.15.196]:18620 "EHLO mailapp01.imgtec.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S966205AbbBDPWd (ORCPT ); Wed, 4 Feb 2015 10:22:33 -0500 From: Zubair Lutfullah Kakakhel To: CC: , , , , , , , , , , , , Subject: [PATCH_V2 07/34] dt: interrupt-controller: Add ingenic,jz4740-intc binding doc Date: Wed, 4 Feb 2015 15:21:36 +0000 Message-ID: <1423063323-19419-8-git-send-email-Zubair.Kakakhel@imgtec.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1423063323-19419-1-git-send-email-Zubair.Kakakhel@imgtec.com> References: <1423063323-19419-1-git-send-email-Zubair.Kakakhel@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [192.168.154.89] Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Paul Burton Add binding documentation for the Ingenic jz4740 interrupt controller. Signed-off-by: Paul Burton Cc: Lars-Peter Clausen Cc: devicetree@vger.kernel.org --- .../interrupt-controller/ingenic,jz4740-intc.txt | 26 ++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ingenic,jz4740-intc.txt diff --git a/Documentation/devicetree/bindings/interrupt-controller/ingenic,jz4740-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/ingenic,jz4740-intc.txt new file mode 100644 index 0000000..5e7f4bb --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/ingenic,jz4740-intc.txt @@ -0,0 +1,26 @@ +Ingenic jz4740 SoC Interrupt Controller + +Required properties: + +- compatible : should be "ingenic,jz4740-intc" or "ingenic,jz4780-intc" +- reg : Specifies base physical address and size of the registers. +- interrupt-controller : Identifies the node as an interrupt controller +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The value shall be 1. +- interrupts - Specifies the CPU interrupt the controller is connected to. + +Optional properties: +- interrupt-parent: phandle of the CPU interrupt controller. + +Example: + +intc: intc@10001000 { + compatible = "ingenic,jz4740-intc"; + reg = <0x10001000 0x14>; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&cpuintc>; + interrupts = <2>; +}; -- 1.9.1 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Zubair Lutfullah Kakakhel Subject: [PATCH_V2 07/34] dt: interrupt-controller: Add ingenic,jz4740-intc binding doc Date: Wed, 4 Feb 2015 15:21:36 +0000 Message-ID: <1423063323-19419-8-git-send-email-Zubair.Kakakhel@imgtec.com> References: <1423063323-19419-1-git-send-email-Zubair.Kakakhel@imgtec.com> Mime-Version: 1.0 Content-Type: text/plain Return-path: In-Reply-To: <1423063323-19419-1-git-send-email-Zubair.Kakakhel@imgtec.com> Sender: linux-kernel-owner@vger.kernel.org To: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org, Zubair.Kakakhel@imgtec.com, gregkh@linuxfoundation.org, mturquette@linaro.org, sboyd@codeaurora.org, ralf@linux-mips.org, jslaby@suse.cz, tglx@linutronix.de, jason@lakedaemon.net, lars@metafoo.de, paul.burton@imgtec.com List-Id: devicetree@vger.kernel.org From: Paul Burton Add binding documentation for the Ingenic jz4740 interrupt controller. Signed-off-by: Paul Burton Cc: Lars-Peter Clausen Cc: devicetree@vger.kernel.org --- .../interrupt-controller/ingenic,jz4740-intc.txt | 26 ++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ingenic,jz4740-intc.txt diff --git a/Documentation/devicetree/bindings/interrupt-controller/ingenic,jz4740-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/ingenic,jz4740-intc.txt new file mode 100644 index 0000000..5e7f4bb --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/ingenic,jz4740-intc.txt @@ -0,0 +1,26 @@ +Ingenic jz4740 SoC Interrupt Controller + +Required properties: + +- compatible : should be "ingenic,jz4740-intc" or "ingenic,jz4780-intc" +- reg : Specifies base physical address and size of the registers. +- interrupt-controller : Identifies the node as an interrupt controller +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The value shall be 1. +- interrupts - Specifies the CPU interrupt the controller is connected to. + +Optional properties: +- interrupt-parent: phandle of the CPU interrupt controller. + +Example: + +intc: intc@10001000 { + compatible = "ingenic,jz4740-intc"; + reg = <0x10001000 0x14>; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&cpuintc>; + interrupts = <2>; +}; -- 1.9.1