From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44851) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YLxHp-0003tA-LB for qemu-devel@nongnu.org; Thu, 12 Feb 2015 12:10:53 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YLxHg-0008I6-2N for qemu-devel@nongnu.org; Thu, 12 Feb 2015 12:10:45 -0500 Received: from e06smtp14.uk.ibm.com ([195.75.94.110]:33662) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YLxHf-0008Gz-Qz for qemu-devel@nongnu.org; Thu, 12 Feb 2015 12:10:36 -0500 Received: from /spool/local by e06smtp14.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Thu, 12 Feb 2015 17:10:34 -0000 Received: from b06cxnps4074.portsmouth.uk.ibm.com (d06relay11.portsmouth.uk.ibm.com [9.149.109.196]) by d06dlp01.portsmouth.uk.ibm.com (Postfix) with ESMTP id CC8F217D805A for ; Thu, 12 Feb 2015 17:10:42 +0000 (GMT) Received: from d06av07.portsmouth.uk.ibm.com (d06av07.portsmouth.uk.ibm.com [9.149.37.248]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id t1CH9kBJ63832182 for ; Thu, 12 Feb 2015 17:09:46 GMT Received: from d06av07.portsmouth.uk.ibm.com (localhost [127.0.0.1]) by d06av07.portsmouth.uk.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id t1CH9kUm028423 for ; Thu, 12 Feb 2015 12:09:46 -0500 From: Jens Freimann Date: Thu, 12 Feb 2015 18:09:23 +0100 Message-Id: <1423760982-8474-7-git-send-email-jfrei@linux.vnet.ibm.com> In-Reply-To: <1423760982-8474-1-git-send-email-jfrei@linux.vnet.ibm.com> References: <1423760982-8474-1-git-send-email-jfrei@linux.vnet.ibm.com> Subject: [Qemu-devel] [PATCH 06/25] s390x/mmu: Fix translation exception code in lowcore List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Christian Borntraeger , Alexander Graf , Cornelia Huck Cc: Jens Freimann , qemu-devel@nongnu.org, Thomas Huth From: Thomas Huth The address space bits in the translation exception code were wrong. In fact, we can simply copy the bits from the PSW, so there's no need for the trans_bits() function anymore. Additionally, we now also set the fetch/store bits in the translation exception code, so a guest can determine whether the exception occured during a write or during a read. Signed-off-by: Thomas Huth Signed-off-by: Jens Freimann Reviewed-by: David Hildenbrand Reviewed-by: Cornelia Huck --- target-s390x/mmu_helper.c | 48 +++++++++++++++-------------------------------- 1 file changed, 15 insertions(+), 33 deletions(-) diff --git a/target-s390x/mmu_helper.c b/target-s390x/mmu_helper.c index 67ad3cc..109a2d3 100644 --- a/target-s390x/mmu_helper.c +++ b/target-s390x/mmu_helper.c @@ -42,45 +42,26 @@ do { } while (0) #endif -static int trans_bits(CPUS390XState *env, uint64_t mode) -{ - S390CPU *cpu = s390_env_get_cpu(env); - int bits = 0; - - switch (mode) { - case PSW_ASC_PRIMARY: - bits = 1; - break; - case PSW_ASC_SECONDARY: - bits = 2; - break; - case PSW_ASC_HOME: - bits = 3; - break; - default: - cpu_abort(CPU(cpu), "unknown asc mode\n"); - break; - } - - return bits; -} +/* Fetch/store bits in the translation exception code: */ +#define FS_READ 0x800 +#define FS_WRITE 0x400 static void trigger_prot_fault(CPUS390XState *env, target_ulong vaddr, - uint64_t mode, bool exc) + uint64_t asc, int rw, bool exc) { CPUState *cs = CPU(s390_env_get_cpu(env)); - int ilen = ILEN_LATER_INC; - int bits = trans_bits(env, mode) | 4; + uint64_t tec; - DPRINTF("%s: vaddr=%016" PRIx64 " bits=%d\n", __func__, vaddr, bits); + tec = vaddr | (rw == 1 ? FS_WRITE : FS_READ) | 4 | asc >> 46; + + DPRINTF("%s: trans_exc_code=%016" PRIx64 "\n", __func__, tec); if (!exc) { return; } - stq_phys(cs->as, - env->psa + offsetof(LowCore, trans_exc_code), vaddr | bits); - trigger_pgm_exception(env, PGM_PROTECTION, ilen); + stq_phys(cs->as, env->psa + offsetof(LowCore, trans_exc_code), tec); + trigger_pgm_exception(env, PGM_PROTECTION, ILEN_LATER_INC); } static void trigger_page_fault(CPUS390XState *env, target_ulong vaddr, @@ -88,7 +69,9 @@ static void trigger_page_fault(CPUS390XState *env, target_ulong vaddr, { CPUState *cs = CPU(s390_env_get_cpu(env)); int ilen = ILEN_LATER; - int bits = trans_bits(env, asc); + uint64_t tec; + + tec = vaddr | (rw == 1 ? FS_WRITE : FS_READ) | asc >> 46; DPRINTF("%s: vaddr=%016" PRIx64 " bits=%d\n", __func__, vaddr, bits); @@ -101,8 +84,7 @@ static void trigger_page_fault(CPUS390XState *env, target_ulong vaddr, ilen = 2; } - stq_phys(cs->as, - env->psa + offsetof(LowCore, trans_exc_code), vaddr | bits); + stq_phys(cs->as, env->psa + offsetof(LowCore, trans_exc_code), tec); trigger_pgm_exception(env, type, ilen); } @@ -307,7 +289,7 @@ static int mmu_translate_asc(CPUS390XState *env, target_ulong vaddr, r = mmu_translate_region(env, vaddr, asc, asce, level, raddr, flags, rw, exc); if ((rw == 1) && !(*flags & PAGE_WRITE)) { - trigger_prot_fault(env, vaddr, asc, exc); + trigger_prot_fault(env, vaddr, asc, rw, exc); return -1; } -- 2.1.4