From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755821AbbB0XFo (ORCPT ); Fri, 27 Feb 2015 18:05:44 -0500 Received: from mail-pd0-f178.google.com ([209.85.192.178]:34910 "EHLO mail-pd0-f178.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755752AbbB0XFS (ORCPT ); Fri, 27 Feb 2015 18:05:18 -0500 From: Mathieu Poirier To: gregkh@linuxfoundation.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, zhang.chunyan@linaro.org, kaixu.xia@linaro.org Subject: [PATCH 5/5] coresight-stm: Bindings for System Trace Macrocell Date: Fri, 27 Feb 2015 16:04:54 -0700 Message-Id: <1425078294-13059-6-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1425078294-13059-1-git-send-email-mathieu.poirier@linaro.org> References: <1425078294-13059-1-git-send-email-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The System Trace Macrocell (STM) is an IP block falling under the CoreSight umbrella. It's main purpose it so expose stimulus channels to any system component for the purpose of information logging. Bindings for this IP block adds a couple of items to the current mandatory definition for CoreSight components. Signed-off-by: Mathieu Poirier Acked-by: Rob Herring --- .../devicetree/bindings/arm/coresight.txt | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt index a3089359aaa6..648d50024429 100644 --- a/Documentation/devicetree/bindings/arm/coresight.txt +++ b/Documentation/devicetree/bindings/arm/coresight.txt @@ -17,6 +17,7 @@ its hardware characteristcs. - "arm,coresight-tmc", "arm,primecell"; - "arm,coresight-funnel", "arm,primecell"; - "arm,coresight-etm3x", "arm,primecell"; + - "arm,coresight-stm", "arm,primecell"; [1] * reg: physical base address and length of the register set(s) of the component. @@ -31,6 +32,14 @@ its hardware characteristcs. layout using the generic DT graph presentation found in "bindings/graph.txt". +* Additional required properties for System Trace Macrocells (STM): + * reg: along with the physical base address and length of the register + set as described above, another entry is required to describe the + mapping of the extended stimulus port area. + + * reg-names: the only acceptable values are "stm-base" and + "stm-stimulus-base", each corresponding to the areas defined in "reg". + * Required properties for devices that don't show up on the AMBA bus, such as non-configurable replicators: @@ -198,3 +207,22 @@ Example: }; }; }; + +4. STM + stm@20100000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0 0x20100000 0 0x1000>, + <0 0x28000000 0 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + port { + stm_out_port: endpoint { + remote-endpoint = <&main_funnel_in_port2>; + }; + }; + }; + +[1]. There is currently two version of STM: STM32 and STM500. Both +have the same HW interface and as such don't need an explicit binding name. -- 1.9.1 From mboxrd@z Thu Jan 1 00:00:00 1970 From: mathieu.poirier@linaro.org (Mathieu Poirier) Date: Fri, 27 Feb 2015 16:04:54 -0700 Subject: [PATCH 5/5] coresight-stm: Bindings for System Trace Macrocell In-Reply-To: <1425078294-13059-1-git-send-email-mathieu.poirier@linaro.org> References: <1425078294-13059-1-git-send-email-mathieu.poirier@linaro.org> Message-ID: <1425078294-13059-6-git-send-email-mathieu.poirier@linaro.org> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org The System Trace Macrocell (STM) is an IP block falling under the CoreSight umbrella. It's main purpose it so expose stimulus channels to any system component for the purpose of information logging. Bindings for this IP block adds a couple of items to the current mandatory definition for CoreSight components. Signed-off-by: Mathieu Poirier Acked-by: Rob Herring --- .../devicetree/bindings/arm/coresight.txt | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt index a3089359aaa6..648d50024429 100644 --- a/Documentation/devicetree/bindings/arm/coresight.txt +++ b/Documentation/devicetree/bindings/arm/coresight.txt @@ -17,6 +17,7 @@ its hardware characteristcs. - "arm,coresight-tmc", "arm,primecell"; - "arm,coresight-funnel", "arm,primecell"; - "arm,coresight-etm3x", "arm,primecell"; + - "arm,coresight-stm", "arm,primecell"; [1] * reg: physical base address and length of the register set(s) of the component. @@ -31,6 +32,14 @@ its hardware characteristcs. layout using the generic DT graph presentation found in "bindings/graph.txt". +* Additional required properties for System Trace Macrocells (STM): + * reg: along with the physical base address and length of the register + set as described above, another entry is required to describe the + mapping of the extended stimulus port area. + + * reg-names: the only acceptable values are "stm-base" and + "stm-stimulus-base", each corresponding to the areas defined in "reg". + * Required properties for devices that don't show up on the AMBA bus, such as non-configurable replicators: @@ -198,3 +207,22 @@ Example: }; }; }; + +4. STM + stm at 20100000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0 0x20100000 0 0x1000>, + <0 0x28000000 0 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + port { + stm_out_port: endpoint { + remote-endpoint = <&main_funnel_in_port2>; + }; + }; + }; + +[1]. There is currently two version of STM: STM32 and STM500. Both +have the same HW interface and as such don't need an explicit binding name. -- 1.9.1