From: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com>
To: Intel Graphics <intel-gfx@lists.freedesktop.org>
Subject: [PATCH 1/3] drm/i915: Disable M2 frac division for integer case
Date: Tue, 3 Mar 2015 20:41:54 +0530 [thread overview]
Message-ID: <1425395514-18377-1-git-send-email-vijay.a.purushothaman@linux.intel.com> (raw)
In-Reply-To: <20150216112356.GM9152@intel.com>
v2 : Handle M2 frac division for both M2 frac and int cases
v3 : Addressed Ville's review comments. Cleared the old bits for RMW
Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_display.c | 24 ++++++++++++++++++------
2 files changed, 19 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 55143cb..8200e98 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1029,6 +1029,7 @@ enum skl_disp_power_wells {
#define DPIO_CHV_FIRST_MOD (0 << 8)
#define DPIO_CHV_SECOND_MOD (1 << 8)
#define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0
+#define DPIO_CHV_FEEDFWD_GAIN_MASK (0xF << 0)
#define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)
#define _CHV_PLL_DW6_CH0 0x8018
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 7298796..15904a8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6131,6 +6131,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
enum dpio_channel port = vlv_pipe_to_channel(pipe);
u32 loopfilter, intcoeff;
u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
+ u32 dpio_val;
int refclk;
bestn = pipe_config->dpll.n;
@@ -6139,6 +6140,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
bestm2 = pipe_config->dpll.m2 >> 22;
bestp1 = pipe_config->dpll.p1;
bestp2 = pipe_config->dpll.p2;
+ dpio_val = 0;
/*
* Enable Refclk and SSC
@@ -6163,13 +6165,23 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
DPIO_CHV_M1_DIV_BY_2 |
1 << DPIO_CHV_N_DIV_SHIFT);
- /* M2 fraction division */
- vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
+ if (bestm2_frac) {
+ /* M2 fraction division */
+ vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
- /* M2 fraction division enable */
- vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
- DPIO_CHV_FRAC_DIV_EN |
- (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
+ /* M2 fraction division enable */
+ dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
+ dpio_val |= DPIO_CHV_FRAC_DIV_EN;
+ dpio_val &= ~DPIO_CHV_FEEDFWD_GAIN_MASK;
+ dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
+ vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
+
+ } else {
+ /* M2 fraction division disable */
+ dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
+ dpio_val &= ~DPIO_CHV_FRAC_DIV_EN;
+ vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
+ }
/* Loop filter */
refclk = i9xx_get_refclk(crtc, 0);
--
1.7.9.5
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next prev parent reply other threads:[~2015-03-03 15:03 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-01-29 18:31 [PATCH] drm/i915: More DPIO magic for CHV HDMI & DP Vijay Purushothaman
2015-01-30 11:09 ` Ville Syrjälä
2015-02-12 13:19 ` Purushothaman, Vijay A
2015-02-16 9:37 ` [v2 0/5] " Vijay Purushothaman
2015-02-16 9:37 ` [v2 1/5] drm/i915: Add new PHY reg definitions for lock threshold Vijay Purushothaman
2015-02-16 11:21 ` Ville Syrjälä
2015-02-16 9:37 ` [v2 2/5] drm/i915: Limit max VCO supported in CHV to 6.48GHz Vijay Purushothaman
2015-02-16 11:21 ` Ville Syrjälä
2015-02-23 16:13 ` Daniel Vetter
2015-03-03 14:57 ` Purushothaman, Vijay A
2015-03-05 15:52 ` Daniel Vetter
2015-03-05 15:59 ` Ville Syrjälä
2015-02-16 9:38 ` [v2 3/5] drm/i915: Disable M2 frac division for integer case Vijay Purushothaman
2015-02-16 11:23 ` Ville Syrjälä
2015-03-03 15:11 ` Vijay Purushothaman [this message]
2015-03-03 15:36 ` [PATCH 1/3] " Ville Syrjälä
2015-03-05 13:49 ` Purushothaman, Vijay A
2015-03-05 14:00 ` Vijay Purushothaman
2015-03-10 9:23 ` Daniel Vetter
2015-02-16 9:38 ` [v2 4/5] drm/i915: Initialize CHV digital lock detect threshold Vijay Purushothaman
2015-02-16 11:27 ` Ville Syrjälä
2015-03-03 15:13 ` [PATCH 2/3] " Vijay Purushothaman
2015-03-03 15:38 ` Ville Syrjälä
2015-03-05 13:50 ` Purushothaman, Vijay A
2015-03-05 14:02 ` Vijay Purushothaman
2015-02-16 9:38 ` [v2 5/5] drm/i915: Update prop, int co-eff and gain threshold for CHV Vijay Purushothaman
2015-02-16 11:32 ` Ville Syrjälä
2015-03-03 14:59 ` Purushothaman, Vijay A
2015-03-03 15:14 ` [PATCH 3/3] " Vijay Purushothaman
2015-03-03 15:45 ` Ville Syrjälä
2015-03-05 14:03 ` Vijay Purushothaman
2015-03-05 14:35 ` Ville Syrjälä
2015-02-23 16:13 ` [v2 0/5] More DPIO magic for CHV HDMI & DP Daniel Vetter
2015-02-10 12:43 ` [PATCH] drm/i915: " Jani Nikula
2015-02-12 13:20 ` Purushothaman, Vijay A
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