From mboxrd@z Thu Jan 1 00:00:00 1970 From: Lina Iyer Subject: [PATCH v15 08/11] ARM: dts: qcom: Add idle states device nodes for 8074 Date: Mon, 9 Mar 2015 09:16:43 -0600 Message-ID: <1425914206-22295-9-git-send-email-lina.iyer@linaro.org> References: <1425914206-22295-1-git-send-email-lina.iyer@linaro.org> Return-path: Received: from mail-pd0-f178.google.com ([209.85.192.178]:39460 "EHLO mail-pd0-f178.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754712AbbCIPRd (ORCPT ); Mon, 9 Mar 2015 11:17:33 -0400 Received: by pdbft15 with SMTP id ft15so35192916pdb.6 for ; Mon, 09 Mar 2015 08:17:32 -0700 (PDT) In-Reply-To: <1425914206-22295-1-git-send-email-lina.iyer@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org List-Id: linux-arm-msm@vger.kernel.org To: daniel.lezcano@linaro.org, khilman@linaro.org, sboyd@codeaurora.org, galak@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: lorenzo.pieralisi@arm.com, msivasub@codeaurora.org, devicetree@vger.kernel.org, Lina Iyer Add ARM common idle states device bindings for cpuidle support for APQ 8074/8974. Support Standby and Standalone power collapse (power down that does not affect any SoC idle states) for each cpu. Cc: Kumar Gala Signed-off-by: Lina Iyer Reviewed-by: Stephen Boyd --- arch/arm/boot/dts/qcom-msm8974.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 5a41f44..ea31c3a 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -22,6 +22,7 @@ next-level-cache = <&L2>; qcom,acc = <&acc0>; qcom,saw = <&saw0>; + cpu-idle-states = <&CPU_STBY &CPU_SPC>; }; cpu@1 { @@ -32,6 +33,7 @@ next-level-cache = <&L2>; qcom,acc = <&acc1>; qcom,saw = <&saw1>; + cpu-idle-states = <&CPU_STBY &CPU_SPC>; }; cpu@2 { @@ -42,6 +44,7 @@ next-level-cache = <&L2>; qcom,acc = <&acc2>; qcom,saw = <&saw2>; + cpu-idle-states = <&CPU_STBY &CPU_SPC>; }; cpu@3 { @@ -52,6 +55,7 @@ next-level-cache = <&L2>; qcom,acc = <&acc3>; qcom,saw = <&saw3>; + cpu-idle-states = <&CPU_STBY &CPU_SPC>; }; L2: l2-cache { @@ -59,6 +63,24 @@ cache-level = <2>; qcom,saw = <&saw_l2>; }; + + idle-states { + CPU_STBY: standby { + compatible = "qcom,idle-state-stby", + "arm,idle-state"; + entry-latency-us = <1>; + exit-latency-us = <1>; + min-residency-us = <2>; + }; + + CPU_SPC: spc { + compatible = "qcom,idle-state-spc", + "arm,idle-state"; + entry-latency-us = <150>; + exit-latency-us = <200>; + min-residency-us = <2000>; + }; + }; }; cpu-pmu { -- 2.1.0 From mboxrd@z Thu Jan 1 00:00:00 1970 From: lina.iyer@linaro.org (Lina Iyer) Date: Mon, 9 Mar 2015 09:16:43 -0600 Subject: [PATCH v15 08/11] ARM: dts: qcom: Add idle states device nodes for 8074 In-Reply-To: <1425914206-22295-1-git-send-email-lina.iyer@linaro.org> References: <1425914206-22295-1-git-send-email-lina.iyer@linaro.org> Message-ID: <1425914206-22295-9-git-send-email-lina.iyer@linaro.org> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Add ARM common idle states device bindings for cpuidle support for APQ 8074/8974. Support Standby and Standalone power collapse (power down that does not affect any SoC idle states) for each cpu. Cc: Kumar Gala Signed-off-by: Lina Iyer Reviewed-by: Stephen Boyd --- arch/arm/boot/dts/qcom-msm8974.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 5a41f44..ea31c3a 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -22,6 +22,7 @@ next-level-cache = <&L2>; qcom,acc = <&acc0>; qcom,saw = <&saw0>; + cpu-idle-states = <&CPU_STBY &CPU_SPC>; }; cpu at 1 { @@ -32,6 +33,7 @@ next-level-cache = <&L2>; qcom,acc = <&acc1>; qcom,saw = <&saw1>; + cpu-idle-states = <&CPU_STBY &CPU_SPC>; }; cpu at 2 { @@ -42,6 +44,7 @@ next-level-cache = <&L2>; qcom,acc = <&acc2>; qcom,saw = <&saw2>; + cpu-idle-states = <&CPU_STBY &CPU_SPC>; }; cpu at 3 { @@ -52,6 +55,7 @@ next-level-cache = <&L2>; qcom,acc = <&acc3>; qcom,saw = <&saw3>; + cpu-idle-states = <&CPU_STBY &CPU_SPC>; }; L2: l2-cache { @@ -59,6 +63,24 @@ cache-level = <2>; qcom,saw = <&saw_l2>; }; + + idle-states { + CPU_STBY: standby { + compatible = "qcom,idle-state-stby", + "arm,idle-state"; + entry-latency-us = <1>; + exit-latency-us = <1>; + min-residency-us = <2>; + }; + + CPU_SPC: spc { + compatible = "qcom,idle-state-spc", + "arm,idle-state"; + entry-latency-us = <150>; + exit-latency-us = <200>; + min-residency-us = <2000>; + }; + }; }; cpu-pmu { -- 2.1.0