From mboxrd@z Thu Jan 1 00:00:00 1970 From: Philipp Zabel Subject: Re: [PATCH v3 06/15] drivers: reset: Add STM32 reset driver Date: Fri, 13 Mar 2015 09:54:55 +0100 Message-ID: <1426236895.3083.20.camel@pengutronix.de> References: <1426197361-19290-1-git-send-email-maxime.coquelin@st.com> <1426197361-19290-7-git-send-email-maxime.coquelin@st.com> Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1426197361-19290-7-git-send-email-maxime.coquelin@st.com> Sender: linux-doc-owner@vger.kernel.org To: Maxime Coquelin Cc: u.kleine-koenig@pengutronix.de, afaerber@suse.de, geert@linux-m68k.org, Rob Herring , Linus Walleij , Arnd Bergmann , stefan@agner.ch, pmeerw@pmeerw.net, pebolle@tiscali.nl, Jonathan Corbet , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Russell King , Daniel Lezcano , Thomas Gleixner , Greg Kroah-Hartman , Jiri Slaby , Andrew Morton , "David S. Miller" , Mauro Carvalho Chehab , Joe Perches , Antti Palosaari , Tejun Heo , Will Deacon List-Id: linux-gpio@vger.kernel.org Am Donnerstag, den 12.03.2015, 22:55 +0100 schrieb Maxime Coquelin: > From: Maxime Coquelin > > The STM32 MCUs family IP can be reset by accessing some shared registers. > > The specificity is that some reset lines are used by the timers. > At timer initialization time, the timer has to be reset, that's why > we cannot use a regular driver. But this is a regular driver now, should this comment be updated? > Signed-off-by: Maxime Coquelin > --- > drivers/reset/Makefile | 1 + > drivers/reset/reset-stm32.c | 125 ++++++++++++++++++++++++++++++++++++++++++++ > 2 files changed, 126 insertions(+) > create mode 100644 drivers/reset/reset-stm32.c > > diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile > index 157d421..aed12d1 100644 > --- a/drivers/reset/Makefile > +++ b/drivers/reset/Makefile > @@ -1,5 +1,6 @@ > obj-$(CONFIG_RESET_CONTROLLER) += core.o > obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o > obj-$(CONFIG_ARCH_BERLIN) += reset-berlin.o > +obj-$(CONFIG_ARCH_STM32) += reset-stm32.o > obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o > obj-$(CONFIG_ARCH_STI) += sti/ > diff --git a/drivers/reset/reset-stm32.c b/drivers/reset/reset-stm32.c > new file mode 100644 > index 0000000..0d389b1 > --- /dev/null > +++ b/drivers/reset/reset-stm32.c > @@ -0,0 +1,125 @@ > +/* > + * Copyright (C) Maxime Coquelin 2015 > + * Author: Maxime Coquelin > + * License terms: GNU General Public License (GPL), version 2 > + * > + * Heavily based on sunxi driver from Maxime Ripard. > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +struct stm32_reset_data { > + spinlock_t lock; > + void __iomem *membase; > + struct reset_controller_dev rcdev; > +}; > + > +static int stm32_reset_assert(struct reset_controller_dev *rcdev, > + unsigned long id) > +{ > + struct stm32_reset_data *data = container_of(rcdev, > + struct stm32_reset_data, > + rcdev); > + int bank = id / BITS_PER_LONG; > + int offset = id % BITS_PER_LONG; > + unsigned long flags; > + u32 reg; > + > + spin_lock_irqsave(&data->lock, flags); > + > + reg = readl_relaxed(data->membase + (bank * 4)); > + writel_relaxed(reg | BIT(offset), data->membase + (bank * 4)); > + > + spin_unlock_irqrestore(&data->lock, flags); > + > + return 0; > +} > + > +static int stm32_reset_deassert(struct reset_controller_dev *rcdev, > + unsigned long id) > +{ > + struct stm32_reset_data *data = container_of(rcdev, > + struct stm32_reset_data, > + rcdev); > + int bank = id / BITS_PER_LONG; > + int offset = id % BITS_PER_LONG; > + unsigned long flags; > + u32 reg; > + > + spin_lock_irqsave(&data->lock, flags); > + > + reg = readl_relaxed(data->membase + (bank * 4)); > + writel_relaxed(reg & ~BIT(offset), data->membase + (bank * 4)); > + > + spin_unlock_irqrestore(&data->lock, flags); > + > + return 0; > +} > + > +static struct reset_control_ops stm32_reset_ops = { > + .assert = stm32_reset_assert, > + .deassert = stm32_reset_deassert, > +}; > + > +static const struct of_device_id stm32_reset_dt_ids[] = { > + { .compatible = "st,stm32-rcc", }, > + { /* sentinel */ }, > +}; > +MODULE_DEVICE_TABLE(of, sstm32_reset_dt_ids); > + > +static int stm32_reset_probe(struct platform_device *pdev) > +{ > + struct stm32_reset_data *data; > + struct resource *res; > + > + data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); > + if (!data) > + return -ENOMEM; > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + data->membase = devm_ioremap_resource(&pdev->dev, res); > + if (IS_ERR(data->membase)) > + return PTR_ERR(data->membase); > + > + spin_lock_init(&data->lock); > + > + data->rcdev.owner = THIS_MODULE; > + data->rcdev.nr_resets = resource_size(res) * 8; > + data->rcdev.ops = &stm32_reset_ops; > + data->rcdev.of_node = pdev->dev.of_node; > + > + return reset_controller_register(&data->rcdev); > +} > + > +static int stm32_reset_remove(struct platform_device *pdev) > +{ > + struct stm32_reset_data *data = platform_get_drvdata(pdev); > + > + reset_controller_unregister(&data->rcdev); > + > + return 0; > +} > + > +static struct platform_driver stm32_reset_driver = { > + .probe = stm32_reset_probe, > + .remove = stm32_reset_remove, > + .driver = { > + .name = "stm32-rcc-reset", > + .of_match_table = stm32_reset_dt_ids, > + }, > +}; > +module_platform_driver(stm32_reset_driver); > + > +MODULE_AUTHOR("Maxime Coquelin "); > +MODULE_DESCRIPTION("STM32 MCUs Reset Controller Driver"); > +MODULE_LICENSE("GPL"); > + regards Philipp From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752844AbbCMIzp (ORCPT ); Fri, 13 Mar 2015 04:55:45 -0400 Received: from metis.ext.pengutronix.de ([92.198.50.35]:33929 "EHLO metis.ext.pengutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751168AbbCMIzm (ORCPT ); Fri, 13 Mar 2015 04:55:42 -0400 Message-ID: <1426236895.3083.20.camel@pengutronix.de> Subject: Re: [PATCH v3 06/15] drivers: reset: Add STM32 reset driver From: Philipp Zabel To: Maxime Coquelin Cc: u.kleine-koenig@pengutronix.de, afaerber@suse.de, geert@linux-m68k.org, Rob Herring , Linus Walleij , Arnd Bergmann , stefan@agner.ch, pmeerw@pmeerw.net, pebolle@tiscali.nl, Jonathan Corbet , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Russell King , Daniel Lezcano , Thomas Gleixner , Greg Kroah-Hartman , Jiri Slaby , Andrew Morton , "David S. Miller" , Mauro Carvalho Chehab , Joe Perches , Antti Palosaari , Tejun Heo , Will Deacon , Nikolay Borisov , Rusty Russell , Kees Cook , Michal Marek , linux-doc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-arch@vger.kernel.org, linux-api@vger.kernel.org Date: Fri, 13 Mar 2015 09:54:55 +0100 In-Reply-To: <1426197361-19290-7-git-send-email-maxime.coquelin@st.com> References: <1426197361-19290-1-git-send-email-maxime.coquelin@st.com> <1426197361-19290-7-git-send-email-maxime.coquelin@st.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.12.9-1+b1 Mime-Version: 1.0 Content-Transfer-Encoding: 7bit X-SA-Exim-Connect-IP: 2001:67c:670:100:96de:80ff:fec2:9969 X-SA-Exim-Mail-From: p.zabel@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Am Donnerstag, den 12.03.2015, 22:55 +0100 schrieb Maxime Coquelin: > From: Maxime Coquelin > > The STM32 MCUs family IP can be reset by accessing some shared registers. > > The specificity is that some reset lines are used by the timers. > At timer initialization time, the timer has to be reset, that's why > we cannot use a regular driver. But this is a regular driver now, should this comment be updated? > Signed-off-by: Maxime Coquelin > --- > drivers/reset/Makefile | 1 + > drivers/reset/reset-stm32.c | 125 ++++++++++++++++++++++++++++++++++++++++++++ > 2 files changed, 126 insertions(+) > create mode 100644 drivers/reset/reset-stm32.c > > diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile > index 157d421..aed12d1 100644 > --- a/drivers/reset/Makefile > +++ b/drivers/reset/Makefile > @@ -1,5 +1,6 @@ > obj-$(CONFIG_RESET_CONTROLLER) += core.o > obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o > obj-$(CONFIG_ARCH_BERLIN) += reset-berlin.o > +obj-$(CONFIG_ARCH_STM32) += reset-stm32.o > obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o > obj-$(CONFIG_ARCH_STI) += sti/ > diff --git a/drivers/reset/reset-stm32.c b/drivers/reset/reset-stm32.c > new file mode 100644 > index 0000000..0d389b1 > --- /dev/null > +++ b/drivers/reset/reset-stm32.c > @@ -0,0 +1,125 @@ > +/* > + * Copyright (C) Maxime Coquelin 2015 > + * Author: Maxime Coquelin > + * License terms: GNU General Public License (GPL), version 2 > + * > + * Heavily based on sunxi driver from Maxime Ripard. > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +struct stm32_reset_data { > + spinlock_t lock; > + void __iomem *membase; > + struct reset_controller_dev rcdev; > +}; > + > +static int stm32_reset_assert(struct reset_controller_dev *rcdev, > + unsigned long id) > +{ > + struct stm32_reset_data *data = container_of(rcdev, > + struct stm32_reset_data, > + rcdev); > + int bank = id / BITS_PER_LONG; > + int offset = id % BITS_PER_LONG; > + unsigned long flags; > + u32 reg; > + > + spin_lock_irqsave(&data->lock, flags); > + > + reg = readl_relaxed(data->membase + (bank * 4)); > + writel_relaxed(reg | BIT(offset), data->membase + (bank * 4)); > + > + spin_unlock_irqrestore(&data->lock, flags); > + > + return 0; > +} > + > +static int stm32_reset_deassert(struct reset_controller_dev *rcdev, > + unsigned long id) > +{ > + struct stm32_reset_data *data = container_of(rcdev, > + struct stm32_reset_data, > + rcdev); > + int bank = id / BITS_PER_LONG; > + int offset = id % BITS_PER_LONG; > + unsigned long flags; > + u32 reg; > + > + spin_lock_irqsave(&data->lock, flags); > + > + reg = readl_relaxed(data->membase + (bank * 4)); > + writel_relaxed(reg & ~BIT(offset), data->membase + (bank * 4)); > + > + spin_unlock_irqrestore(&data->lock, flags); > + > + return 0; > +} > + > +static struct reset_control_ops stm32_reset_ops = { > + .assert = stm32_reset_assert, > + .deassert = stm32_reset_deassert, > +}; > + > +static const struct of_device_id stm32_reset_dt_ids[] = { > + { .compatible = "st,stm32-rcc", }, > + { /* sentinel */ }, > +}; > +MODULE_DEVICE_TABLE(of, sstm32_reset_dt_ids); > + > +static int stm32_reset_probe(struct platform_device *pdev) > +{ > + struct stm32_reset_data *data; > + struct resource *res; > + > + data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); > + if (!data) > + return -ENOMEM; > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + data->membase = devm_ioremap_resource(&pdev->dev, res); > + if (IS_ERR(data->membase)) > + return PTR_ERR(data->membase); > + > + spin_lock_init(&data->lock); > + > + data->rcdev.owner = THIS_MODULE; > + data->rcdev.nr_resets = resource_size(res) * 8; > + data->rcdev.ops = &stm32_reset_ops; > + data->rcdev.of_node = pdev->dev.of_node; > + > + return reset_controller_register(&data->rcdev); > +} > + > +static int stm32_reset_remove(struct platform_device *pdev) > +{ > + struct stm32_reset_data *data = platform_get_drvdata(pdev); > + > + reset_controller_unregister(&data->rcdev); > + > + return 0; > +} > + > +static struct platform_driver stm32_reset_driver = { > + .probe = stm32_reset_probe, > + .remove = stm32_reset_remove, > + .driver = { > + .name = "stm32-rcc-reset", > + .of_match_table = stm32_reset_dt_ids, > + }, > +}; > +module_platform_driver(stm32_reset_driver); > + > +MODULE_AUTHOR("Maxime Coquelin "); > +MODULE_DESCRIPTION("STM32 MCUs Reset Controller Driver"); > +MODULE_LICENSE("GPL"); > + regards Philipp From mboxrd@z Thu Jan 1 00:00:00 1970 From: p.zabel@pengutronix.de (Philipp Zabel) Date: Fri, 13 Mar 2015 09:54:55 +0100 Subject: [PATCH v3 06/15] drivers: reset: Add STM32 reset driver In-Reply-To: <1426197361-19290-7-git-send-email-maxime.coquelin@st.com> References: <1426197361-19290-1-git-send-email-maxime.coquelin@st.com> <1426197361-19290-7-git-send-email-maxime.coquelin@st.com> Message-ID: <1426236895.3083.20.camel@pengutronix.de> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Am Donnerstag, den 12.03.2015, 22:55 +0100 schrieb Maxime Coquelin: > From: Maxime Coquelin > > The STM32 MCUs family IP can be reset by accessing some shared registers. > > The specificity is that some reset lines are used by the timers. > At timer initialization time, the timer has to be reset, that's why > we cannot use a regular driver. But this is a regular driver now, should this comment be updated? > Signed-off-by: Maxime Coquelin > --- > drivers/reset/Makefile | 1 + > drivers/reset/reset-stm32.c | 125 ++++++++++++++++++++++++++++++++++++++++++++ > 2 files changed, 126 insertions(+) > create mode 100644 drivers/reset/reset-stm32.c > > diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile > index 157d421..aed12d1 100644 > --- a/drivers/reset/Makefile > +++ b/drivers/reset/Makefile > @@ -1,5 +1,6 @@ > obj-$(CONFIG_RESET_CONTROLLER) += core.o > obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o > obj-$(CONFIG_ARCH_BERLIN) += reset-berlin.o > +obj-$(CONFIG_ARCH_STM32) += reset-stm32.o > obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o > obj-$(CONFIG_ARCH_STI) += sti/ > diff --git a/drivers/reset/reset-stm32.c b/drivers/reset/reset-stm32.c > new file mode 100644 > index 0000000..0d389b1 > --- /dev/null > +++ b/drivers/reset/reset-stm32.c > @@ -0,0 +1,125 @@ > +/* > + * Copyright (C) Maxime Coquelin 2015 > + * Author: Maxime Coquelin > + * License terms: GNU General Public License (GPL), version 2 > + * > + * Heavily based on sunxi driver from Maxime Ripard. > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +struct stm32_reset_data { > + spinlock_t lock; > + void __iomem *membase; > + struct reset_controller_dev rcdev; > +}; > + > +static int stm32_reset_assert(struct reset_controller_dev *rcdev, > + unsigned long id) > +{ > + struct stm32_reset_data *data = container_of(rcdev, > + struct stm32_reset_data, > + rcdev); > + int bank = id / BITS_PER_LONG; > + int offset = id % BITS_PER_LONG; > + unsigned long flags; > + u32 reg; > + > + spin_lock_irqsave(&data->lock, flags); > + > + reg = readl_relaxed(data->membase + (bank * 4)); > + writel_relaxed(reg | BIT(offset), data->membase + (bank * 4)); > + > + spin_unlock_irqrestore(&data->lock, flags); > + > + return 0; > +} > + > +static int stm32_reset_deassert(struct reset_controller_dev *rcdev, > + unsigned long id) > +{ > + struct stm32_reset_data *data = container_of(rcdev, > + struct stm32_reset_data, > + rcdev); > + int bank = id / BITS_PER_LONG; > + int offset = id % BITS_PER_LONG; > + unsigned long flags; > + u32 reg; > + > + spin_lock_irqsave(&data->lock, flags); > + > + reg = readl_relaxed(data->membase + (bank * 4)); > + writel_relaxed(reg & ~BIT(offset), data->membase + (bank * 4)); > + > + spin_unlock_irqrestore(&data->lock, flags); > + > + return 0; > +} > + > +static struct reset_control_ops stm32_reset_ops = { > + .assert = stm32_reset_assert, > + .deassert = stm32_reset_deassert, > +}; > + > +static const struct of_device_id stm32_reset_dt_ids[] = { > + { .compatible = "st,stm32-rcc", }, > + { /* sentinel */ }, > +}; > +MODULE_DEVICE_TABLE(of, sstm32_reset_dt_ids); > + > +static int stm32_reset_probe(struct platform_device *pdev) > +{ > + struct stm32_reset_data *data; > + struct resource *res; > + > + data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); > + if (!data) > + return -ENOMEM; > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + data->membase = devm_ioremap_resource(&pdev->dev, res); > + if (IS_ERR(data->membase)) > + return PTR_ERR(data->membase); > + > + spin_lock_init(&data->lock); > + > + data->rcdev.owner = THIS_MODULE; > + data->rcdev.nr_resets = resource_size(res) * 8; > + data->rcdev.ops = &stm32_reset_ops; > + data->rcdev.of_node = pdev->dev.of_node; > + > + return reset_controller_register(&data->rcdev); > +} > + > +static int stm32_reset_remove(struct platform_device *pdev) > +{ > + struct stm32_reset_data *data = platform_get_drvdata(pdev); > + > + reset_controller_unregister(&data->rcdev); > + > + return 0; > +} > + > +static struct platform_driver stm32_reset_driver = { > + .probe = stm32_reset_probe, > + .remove = stm32_reset_remove, > + .driver = { > + .name = "stm32-rcc-reset", > + .of_match_table = stm32_reset_dt_ids, > + }, > +}; > +module_platform_driver(stm32_reset_driver); > + > +MODULE_AUTHOR("Maxime Coquelin "); > +MODULE_DESCRIPTION("STM32 MCUs Reset Controller Driver"); > +MODULE_LICENSE("GPL"); > + regards Philipp