[PATCH 00/49] Basic Broxton enabling

[PATCH 00/49] Basic Broxton enabling

[Imre Deak]

Hi,

This patchset adds basic graphics driver support for Broxton (BXT).

Broxton is the latest Intel® Atom(tm) Processor from Intel® with HD Graphics.

The major GPU hardware features include:
- Gen9 Intel® HD Graphics
- The addition of a 3rd display plane
- Three HDMI/DP/eDP display ports
- Two MIPI/DSI display ports

The GPU side is very similar to the one in Skylake. This is also true
for the display side, with the exception of the added DSI ports and a
different DP/HDMI PHY hardware implementation, the latter one being a
Valleyview/Cherryview derivative. Based on this most of the patches in
this series are related to the display side. Features yet to be
implemented include DSI support and runtime power management, patches
for these will follow after this series.

Thanks for all who contributed to this effort, especially:
Damien Lespiau
Satheesh Krishna
Vandana Kannan
Ben Widawsky
Jesse Barnes

--Imre

A.Sunil Kamath (4):
  drm/i915/bxt: Add change to support gmbus pin pair for BXT
  drm/i915/bxt: WARN in case BXT unused gmbus ports are accessed
  drm/i915/bxt: Avoid registering unused gmbus ports as i2c adapter
  drm/i915/bxt: Implement enable/disable for Display C9 state

Ben Widawsky (3):
  drm/i915/bxt: add GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ workaround
  drm/i915/bxt: add WaDisableMaskBasedCammingInRCC workaround
  drm/i915/skl: add WaDisableMaskBasedCammingInRCC workaround

Daisy Sun (1):
  drm/i915/bxt: BXT FBC enablement

Damien Lespiau (8):
  drm/i915/bxt: Add BXT PCI ids
  drm/i915/bxt: Broxton uses the same GMS values as Skylake
  drm/i915/bxt: Broxton has 3 sprite planes on pipe A/B, 2 on pipe C
  drm/i915/bxt: Add the plane4 related interrupt definitions
  drm/i915/bxt: Broxton DDB is 512 blocks
  drm/i915/bxt: Broxton raises the maximum number of planes to 4
  drm/i915: Iterate through the initialized DDIs to prepare their
    buffers
  drm/i915: Don't write the HDMI buffer translation entry when not
    needed

Imre Deak (10):
  drm/i915/bxt: map GTT as uncached
  drm/i915/gen9: fix PIPE_CONTROL flush for VS_INVALIDATE
  drm/i915/bxt: add bxt_init_clock_gating
  drm/i915/bxt: add GEN8_SDEUNIT_CLOCK_GATE_DISABLE workaround
  drm/i915/bxt: add description about the BXT PHYs
  drm/i915: factor out vlv_PLL_is_optimal
  drm/i915: check for div-by-zero in vlv_PLL_is_optimal
  drm/i915/chv: use vlv_PLL_is_optimal in chv_find_best_dpll
  drm/i915/bxt: add bxt_find_best_dpll
  drm/i915: suppress false PLL state warnings on non-GMCH platforms

Jesse Barnes (1):
  drm/i915/bxt: fix panel fitter setup in crtc disable/enable

Nick Hoath (1):
  drm/i915/bxt: HardWare WorkAround ring initialisation for Broxton

Robert Beckett (1):
  drm/i915/bxt: add workaround to avoid PTE corruption

Satheeshakrishna M (8):
  drm/i915/bxt: Add IS_BROXTON macro
  drm/i915/bxt: Define BXT power domains
  drm/i915/bxt: Restrict PORT_CLK_SEL programming below gen9
  drm/i915/bxt: Define bxt DDI PLLs and implement enable/disable
    sequence
  drm/i915/bxt: BXT clock divider calculation
  drm/i915/bxt: Assign PLL for pipe
  drm/i915/bxt: Determine PLL attached to pipe
  drm/i915/bxt: Determine programmed frequency

Shashank Sharma (4):
  drm/i915/bxt: DDI Hotplug interrupt setup
  drm/i915/bxt: Add DDI hpd handler
  drm/i915/bxt: Add BXT support in gen8_irq functions
  drm/i915/bxt: Enable GMBUS IRQ

Suketu Shah (1):
  drm/i915/bxt: Add DC9 Trigger sequence

Sumit Singh (1):
  drm/i915/bxt: Enable PTE encoding

Vandana Kannan (6):
  drm/i915/bxt: don't use unsupported port detection
  drm/i915/bxt: Increase DDI buf idle timeout
  drm/i915: Rename vlv_cdclk_freq to cdclk_freq
  drm/i915/bxt: add display initialize/uninitialize sequence
  drm/i915/bxt: VSwing programming sequence
  drm/i915/bxt: Update max level of vswing

 Documentation/DocBook/drm.tmpl          |   4 +-
 arch/x86/kernel/early-quirks.c          |   1 +
 drivers/gpu/drm/i915/i915_dma.c         |   6 +-
 drivers/gpu/drm/i915/i915_drv.c         |  45 +-
 drivers/gpu/drm/i915/i915_drv.h         |  20 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c     |   9 +-
 drivers/gpu/drm/i915/i915_irq.c         | 122 ++++-
 drivers/gpu/drm/i915/i915_reg.h         | 316 ++++++++++++-
 drivers/gpu/drm/i915/intel_bios.c       |   3 +-
 drivers/gpu/drm/i915/intel_ddi.c        | 787 ++++++++++++++++++++++++++++++--
 drivers/gpu/drm/i915/intel_display.c    | 290 ++++++++++--
 drivers/gpu/drm/i915/intel_dp.c         |  70 ++-
 drivers/gpu/drm/i915/intel_dp_mst.c     |   6 +-
 drivers/gpu/drm/i915/intel_drv.h        |  11 +
 drivers/gpu/drm/i915/intel_dvo.c        |   2 +-
 drivers/gpu/drm/i915/intel_i2c.c        |  79 +++-
 drivers/gpu/drm/i915/intel_lrc.c        |  19 +-
 drivers/gpu/drm/i915/intel_lvds.c       |   2 +-
 drivers/gpu/drm/i915/intel_pm.c         |  33 +-
 drivers/gpu/drm/i915/intel_ringbuffer.c |  21 +-
 drivers/gpu/drm/i915/intel_runtime_pm.c | 121 +++++
 drivers/gpu/drm/i915/intel_sdvo.c       |   4 +-
 include/drm/i915_pciids.h               |   6 +
 23 files changed, 1857 insertions(+), 120 deletions(-)

-- 
2.1.0

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[PATCH 01/49] drm/i915/bxt: Add BXT PCI ids

[Imre Deak]

From: Damien Lespiau <damien.lespiau@intel.com>

v2: Switch to info->ring_mask and add VEBOX support.
v3: Fold in update from Damien.
v4: Add GEN_DEFAULT_PIPEOFFSETS and IVB_CURSOR_OFFSETS
v5: set no-LLC (imre)

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> (v1,v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (v4)
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c | 14 +++++++++++++-
 include/drm/i915_pciids.h       |  6 ++++++
 2 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 82f8be4..4d50785 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -381,6 +381,17 @@ static const struct intel_device_info intel_skylake_gt3_info = {
 	IVB_CURSOR_OFFSETS,
 };
 
+static const struct intel_device_info intel_broxton_info = {
+	.is_preliminary = 1,
+	.gen = 9,
+	.need_gfx_hws = 1, .has_hotplug = 1,
+	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
+	.num_pipes = 3,
+	.has_ddi = 1,
+	GEN_DEFAULT_PIPEOFFSETS,
+	IVB_CURSOR_OFFSETS,
+};
+
 /*
  * Make sure any device matches here are from most specific to most
  * general.  For example, since the Quanta match is based on the subsystem
@@ -420,7 +431,8 @@ static const struct intel_device_info intel_skylake_gt3_info = {
 	INTEL_CHV_IDS(&intel_cherryview_info),	\
 	INTEL_SKL_GT1_IDS(&intel_skylake_info),	\
 	INTEL_SKL_GT2_IDS(&intel_skylake_info),	\
-	INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info)	\
+	INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),	\
+	INTEL_BXT_IDS(&intel_broxton_info)
 
 static const struct pci_device_id pciidlist[] = {		/* aka */
 	INTEL_PCI_IDS,
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 6133723..bd0d644 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -287,4 +287,10 @@
 	INTEL_SKL_GT3_IDS(info)
 
 
+#define INTEL_BXT_IDS(info) \
+	INTEL_VGA_DEVICE(0x0A84, info), \
+	INTEL_VGA_DEVICE(0x0A85, info), \
+	INTEL_VGA_DEVICE(0x0A86, info), \
+	INTEL_VGA_DEVICE(0x0A87, info)
+
 #endif /* _I915_PCIIDS_H */
-- 
2.1.0

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[PATCH 02/49] drm/i915/bxt: BXT FBC enablement

[Imre Deak]

From: Daisy Sun <daisy.sun@intel.com>

Enable FBC feature on Broxton

Issue: VIZ-3784
Signed-off-by: Daisy Sun <daisy.sun@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 4d50785..48434cb6 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -388,6 +388,7 @@ static const struct intel_device_info intel_broxton_info = {
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 	.num_pipes = 3,
 	.has_ddi = 1,
+	.has_fbc = 1,
 	GEN_DEFAULT_PIPEOFFSETS,
 	IVB_CURSOR_OFFSETS,
 };
-- 
2.1.0

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[PATCH 03/49] drm/i915/bxt: Add IS_BROXTON macro

[Imre Deak]

From: Satheeshakrishna M <satheeshakrishna.m@intel.com>

Adding IS_BROXTON macro for broxton specific implementation.

Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 81f60b4..eba53c3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2305,6 +2305,7 @@ struct drm_i915_cmd_table {
 #define IS_HASWELL(dev)	(INTEL_INFO(dev)->is_haswell)
 #define IS_BROADWELL(dev)	(!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
 #define IS_SKYLAKE(dev)	(INTEL_INFO(dev)->is_skylake)
+#define IS_BROXTON(dev)	(!INTEL_INFO(dev)->is_skylake && IS_GEN9(dev))
 #define IS_MOBILE(dev)		(INTEL_INFO(dev)->is_mobile)
 #define IS_HSW_EARLY_SDV(dev)	(IS_HASWELL(dev) && \
 				 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
-- 
2.1.0

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[PATCH 04/49] drm/i915/bxt: Broxton uses the same GMS values as Skylake

[Imre Deak]

From: Damien Lespiau <damien.lespiau@intel.com>

v2: Rebase on top of the early-quirks rework from Ville.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> (v1)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 arch/x86/kernel/early-quirks.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index fe9f0b7..ab470e4 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -546,6 +546,7 @@ static const struct pci_device_id intel_stolen_ids[] __initconst = {
 	INTEL_BDW_D_IDS(&gen8_stolen_funcs),
 	INTEL_CHV_IDS(&chv_stolen_funcs),
 	INTEL_SKL_IDS(&gen9_stolen_funcs),
+	INTEL_BXT_IDS(&gen9_stolen_funcs),
 };
 
 static void __init intel_graphics_stolen(int num, int slot, int func)
-- 
2.1.0

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[PATCH 05/49] drm/i915/bxt: Enable PTE encoding

[Imre Deak]

From: Sumit Singh <sumit.k.singh@intel.com>

The caching options for page table entries have remained the same as
Cherryview. This patch fixes it so the right code path is taken on BXT.

v2: Fix up commit message (Mike)

Signed-off-by: Sumit Singh <sumit.k.singh@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index f1b9ea6..4311292 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1506,7 +1506,7 @@ void i915_gem_restore_gtt_mappings(struct drm_device *dev)
 
 
 	if (INTEL_INFO(dev)->gen >= 8) {
-		if (IS_CHERRYVIEW(dev))
+		if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
 			chv_setup_private_ppat(dev_priv);
 		else
 			bdw_setup_private_ppat(dev_priv);
@@ -2187,7 +2187,7 @@ static int gen8_gmch_probe(struct drm_device *dev,
 
 	*gtt_total = (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT;
 
-	if (IS_CHERRYVIEW(dev))
+	if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
 		chv_setup_private_ppat(dev_priv);
 	else
 		bdw_setup_private_ppat(dev_priv);
-- 
2.1.0

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[PATCH 06/49] drm/i915/bxt: Broxton has 3 sprite planes on pipe A/B, 2 on pipe C

[Imre Deak]

From: Damien Lespiau <damien.lespiau@intel.com>

v2: Rebase on top of the for_each_pipe() change adding dev_priv as first
    argument.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/i915_dma.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index d49ed68..a94a970 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -585,7 +585,11 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
 
 	info = (struct intel_device_info *)&dev_priv->info;
 
-	if (IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen == 9)
+	if (IS_BROXTON(dev)) {
+		info->num_sprites[PIPE_A] = 3;
+		info->num_sprites[PIPE_B] = 3;
+		info->num_sprites[PIPE_C] = 2;
+	} else if (IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen == 9)
 		for_each_pipe(dev_priv, pipe)
 			info->num_sprites[pipe] = 2;
 	else
-- 
2.1.0

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[PATCH 07/49] drm/i915/bxt: Add the plane4 related interrupt definitions

[Imre Deak]

From: Damien Lespiau <damien.lespiau@intel.com>

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cc8ebab..3369a11 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5216,9 +5216,11 @@ enum skl_disp_power_wells {
 #define  GEN8_PIPE_VSYNC		(1 << 1)
 #define  GEN8_PIPE_VBLANK		(1 << 0)
 #define  GEN9_PIPE_CURSOR_FAULT		(1 << 11)
+#define  GEN9_PIPE_PLANE4_FAULT		(1 << 10)
 #define  GEN9_PIPE_PLANE3_FAULT		(1 << 9)
 #define  GEN9_PIPE_PLANE2_FAULT		(1 << 8)
 #define  GEN9_PIPE_PLANE1_FAULT		(1 << 7)
+#define  GEN9_PIPE_PLANE4_FLIP_DONE	(1 << 6)
 #define  GEN9_PIPE_PLANE3_FLIP_DONE	(1 << 5)
 #define  GEN9_PIPE_PLANE2_FLIP_DONE	(1 << 4)
 #define  GEN9_PIPE_PLANE1_FLIP_DONE	(1 << 3)
@@ -5229,6 +5231,7 @@ enum skl_disp_power_wells {
 	 GEN8_PIPE_PRIMARY_FAULT)
 #define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \
 	(GEN9_PIPE_CURSOR_FAULT | \
+	 GEN9_PIPE_PLANE4_FAULT | \
 	 GEN9_PIPE_PLANE3_FAULT | \
 	 GEN9_PIPE_PLANE2_FAULT | \
 	 GEN9_PIPE_PLANE1_FAULT)
-- 
2.1.0

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[PATCH 08/49] drm/i915/bxt: Broxton DDB is 512 blocks

[Imre Deak]

From: Damien Lespiau <damien.lespiau@intel.com>

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 288c9d2..b89ab4d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2538,6 +2538,7 @@ static bool ilk_disable_lp_wm(struct drm_device *dev)
  */
 
 #define SKL_DDB_SIZE		896	/* in blocks */
+#define BXT_DDB_SIZE		512
 
 static void
 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
@@ -2556,7 +2557,10 @@ skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
 		return;
 	}
 
-	ddb_size = SKL_DDB_SIZE;
+	if (IS_BROXTON(dev))
+		ddb_size = BXT_DDB_SIZE;
+	else
+		ddb_size = SKL_DDB_SIZE;
 
 	ddb_size -= 4; /* 4 blocks for bypass path allocation */
 
-- 
2.1.0

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[PATCH 09/49] drm/i915/bxt: Broxton raises the maximum number of planes to 4

[Imre Deak]

From: Damien Lespiau <damien.lespiau@intel.com>

Pipe A and b have 4 planes.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index eba53c3..8fb7cc0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -130,7 +130,7 @@ enum transcoder {
  *
  * This value doesn't count the cursor plane.
  */
-#define I915_MAX_PLANES	3
+#define I915_MAX_PLANES	4
 
 enum plane {
 	PLANE_A = 0,
-- 
2.1.0

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[PATCH 10/49] drm/i915/bxt: map GTT as uncached

[Imre Deak]

On Broxton per specification the GTT has to be mapped as uncached.
This was caught by the PTE write readback warning, which showed a
corrupted PTE value with using the current write-combine mapping.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 4311292..8edf3cf 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2065,7 +2065,10 @@ static int ggtt_probe_common(struct drm_device *dev,
 	gtt_phys_addr = pci_resource_start(dev->pdev, 0) +
 		(pci_resource_len(dev->pdev, 0) / 2);
 
-	dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size);
+	if (IS_BROXTON(dev))
+		dev_priv->gtt.gsm = ioremap_nocache(gtt_phys_addr, gtt_size);
+	else
+		dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size);
 	if (!dev_priv->gtt.gsm) {
 		DRM_ERROR("Failed to map the gtt page table\n");
 		return -ENOMEM;
-- 
2.1.0

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[PATCH 11/49] drm/i915/gen9: fix PIPE_CONTROL flush for VS_INVALIDATE

[Imre Deak]

On GEN9+ per specification a NULL PIPE_CONTROL needs to be emitted
before any PIPE_CONTROL command with the VS_INVALIDATE flag set.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/intel_lrc.c | 19 ++++++++++++++++++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index fcb074b..71aeeb3 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1262,6 +1262,7 @@ static int gen8_emit_flush_render(struct intel_ringbuffer *ringbuf,
 {
 	struct intel_engine_cs *ring = ringbuf->ring;
 	u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
+	bool vf_flush_wa;
 	u32 flags = 0;
 	int ret;
 
@@ -1283,10 +1284,26 @@ static int gen8_emit_flush_render(struct intel_ringbuffer *ringbuf,
 		flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 	}
 
-	ret = intel_logical_ring_begin(ringbuf, ctx, 6);
+	/*
+	 * On GEN9+ Before VF_CACHE_INVALIDATE we need to emit a NULL pipe
+	 * control.
+	 */
+	vf_flush_wa = INTEL_INFO(ring->dev)->gen >= 9 &&
+		      flags & PIPE_CONTROL_VF_CACHE_INVALIDATE;
+
+	ret = intel_logical_ring_begin(ringbuf, ctx, vf_flush_wa ? 12 : 6);
 	if (ret)
 		return ret;
 
+	if (vf_flush_wa) {
+		intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
+		intel_logical_ring_emit(ringbuf, 0);
+		intel_logical_ring_emit(ringbuf, 0);
+		intel_logical_ring_emit(ringbuf, 0);
+		intel_logical_ring_emit(ringbuf, 0);
+		intel_logical_ring_emit(ringbuf, 0);
+	}
+
 	intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
 	intel_logical_ring_emit(ringbuf, flags);
 	intel_logical_ring_emit(ringbuf, scratch_addr);
-- 
2.1.0

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[PATCH 12/49] drm/i915/bxt: HardWare WorkAround ring initialisation for Broxton

[Imre Deak]

From: Nick Hoath <nicholas.hoath@intel.com>

Adds framework for Broxton HW WAs

Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 441e250..abe062a 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1027,6 +1027,13 @@ static int skl_init_workarounds(struct intel_engine_cs *ring)
 	return skl_tune_iz_hashing(ring);
 }
 
+static int bxt_init_workarounds(struct intel_engine_cs *ring)
+{
+	gen9_init_workarounds(ring);
+
+	return 0;
+}
+
 int init_workarounds_ring(struct intel_engine_cs *ring)
 {
 	struct drm_device *dev = ring->dev;
@@ -1044,8 +1051,9 @@ int init_workarounds_ring(struct intel_engine_cs *ring)
 
 	if (IS_SKYLAKE(dev))
 		return skl_init_workarounds(ring);
-	else if (IS_GEN9(dev))
-		return gen9_init_workarounds(ring);
+
+	if (IS_BROXTON(dev))
+		return bxt_init_workarounds(ring);
 
 	return 0;
 }
-- 
2.1.0

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[PATCH 13/49] drm/i915/bxt: add bxt_init_clock_gating

[Imre Deak]

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b89ab4d..3d4a7c3 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -94,6 +94,11 @@ static void skl_init_clock_gating(struct drm_device *dev)
 			   GEN8_LQSC_RO_PERF_DIS);
 }
 
+static void bxt_init_clock_gating(struct drm_device *dev)
+{
+	gen9_init_clock_gating(dev);
+}
+
 static void i915_pineview_get_mem_freq(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -6503,7 +6508,12 @@ void intel_init_pm(struct drm_device *dev)
 	if (INTEL_INFO(dev)->gen >= 9) {
 		skl_setup_wm_latency(dev);
 
-		dev_priv->display.init_clock_gating = skl_init_clock_gating;
+		if (IS_BROXTON(dev))
+			dev_priv->display.init_clock_gating =
+				bxt_init_clock_gating;
+		else
+			dev_priv->display.init_clock_gating =
+				skl_init_clock_gating;
 		dev_priv->display.update_wm = skl_update_wm;
 		dev_priv->display.update_sprite_wm = skl_update_sprite_wm;
 	} else if (HAS_PCH_SPLIT(dev)) {
-- 
2.1.0

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[PATCH 14/49] drm/i915/bxt: add GEN8_SDEUNIT_CLOCK_GATE_DISABLE workaround

[Imre Deak]

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 3d4a7c3..d5dd0b3 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -96,7 +96,18 @@ static void skl_init_clock_gating(struct drm_device *dev)
 
 static void bxt_init_clock_gating(struct drm_device *dev)
 {
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
 	gen9_init_clock_gating(dev);
+
+	/*
+	 * FIXME:
+	 * GEN8_SDEUNIT_CLOCK_GATE_DISABLE applies on A0 only.
+	 */
+	 /* WaDisableSDEUnitClockGating:bxt */
+	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
+		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
+
 }
 
 static void i915_pineview_get_mem_freq(struct drm_device *dev)
-- 
2.1.0

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[PATCH 15/49] drm/i915/bxt: add GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ workaround

[Imre Deak]

From: Ben Widawsky <benjamin.widawsky@intel.com>

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 1 +
 drivers/gpu/drm/i915/intel_pm.c | 4 +++-
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3369a11..b7ba061 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6104,6 +6104,7 @@ enum skl_disp_power_wells {
 #define GEN8_UCGCTL6				0x9430
 #define   GEN8_GAPSUNIT_CLOCK_GATE_DISABLE	(1<<24)
 #define   GEN8_SDEUNIT_CLOCK_GATE_DISABLE	(1<<14)
+#define   GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ (1<<28)
 
 #define GEN6_GFXPAUSE				0xA000
 #define GEN6_RPNSWREQ				0xA008
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d5dd0b3..52d3c02 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -103,10 +103,12 @@ static void bxt_init_clock_gating(struct drm_device *dev)
 	/*
 	 * FIXME:
 	 * GEN8_SDEUNIT_CLOCK_GATE_DISABLE applies on A0 only.
+	 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
 	 */
 	 /* WaDisableSDEUnitClockGating:bxt */
 	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
-		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
+		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE |
+		   GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
 
 }
 
-- 
2.1.0

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[PATCH 16/49] drm/i915/bxt: add WaDisableMaskBasedCammingInRCC workaround

[Imre Deak]

From: Ben Widawsky <benjamin.widawsky@intel.com>

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h         | 4 ++++
 drivers/gpu/drm/i915/intel_ringbuffer.c | 9 +++++++++
 2 files changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b7ba061..1d074e8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5346,6 +5346,10 @@ enum skl_disp_power_wells {
 #define  HDC_FORCE_NON_COHERENT			(1<<4)
 #define  HDC_BARRIER_PERFORMANCE_DISABLE	(1<<10)
 
+/* GEN9 chicken */
+#define SLICE_ECO_CHICKEN0			0x7308
+#define   PIXEL_MASK_CAMMING_DISABLE		(1 << 14)
+
 /* WaCatErrorRejectionIssue */
 #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		0x9030
 #define  GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB	(1<<11)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index abe062a..e23cbdc 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -966,6 +966,15 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
 	WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 			  GEN9_CCS_TLB_PREFETCH_ENABLE);
 
+	/*
+	 * FIXME: don't apply the following on BXT for stepping C. On BXT A0
+	 * the flag reads back as 0.
+	 */
+	/* WaDisableMaskBasedCammingInRCC:bxtA */
+	if (IS_BROXTON(dev))
+		WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
+				  PIXEL_MASK_CAMMING_DISABLE);
+
 	return 0;
 }
 
-- 
2.1.0

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[PATCH 17/49] drm/i915/skl: add WaDisableMaskBasedCammingInRCC workaround

[Imre Deak]

From: Ben Widawsky <benjamin.widawsky@intel.com>

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index e23cbdc..000f608 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -970,8 +970,8 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
 	 * FIXME: don't apply the following on BXT for stepping C. On BXT A0
 	 * the flag reads back as 0.
 	 */
-	/* WaDisableMaskBasedCammingInRCC:bxtA */
-	if (IS_BROXTON(dev))
+	/* WaDisableMaskBasedCammingInRCC:sklC,bxtA */
+	if (INTEL_REVID(dev) == SKL_REVID_C0 || IS_BROXTON(dev))
 		WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
 				  PIXEL_MASK_CAMMING_DISABLE);
 
-- 
2.1.0

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[PATCH 18/49] drm/i915/bxt: add workaround to avoid PTE corruption

[Imre Deak]

From: Robert Beckett <robert.beckett@intel.com>

Set TLBPF in TILECTL. This fixes an issue with BXT HW seeing
corrupted pte entries.

v2:
- move the workaround to bxt_init_clock_gating (imre)

Signed-off-by: Robert Beckett <robert.beckett@intel.com> (v1)
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 1 +
 drivers/gpu/drm/i915/intel_pm.c | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1d074e8..d69d7b9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1151,6 +1151,7 @@ enum skl_disp_power_wells {
 /* control register for cpu gtt access */
 #define TILECTL				0x101000
 #define   TILECTL_SWZCTL			(1 << 0)
+#define   TILECTL_TLBPF			(1 << 1)
 #define   TILECTL_TLB_PREFETCH_DIS	(1 << 2)
 #define   TILECTL_BACKSNOOP_DIS		(1 << 3)
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 52d3c02..d3f2557 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -110,6 +110,8 @@ static void bxt_init_clock_gating(struct drm_device *dev)
 		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE |
 		   GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
 
+	/* FIXME: apply on A0 only */
+	I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
 }
 
 static void i915_pineview_get_mem_freq(struct drm_device *dev)
-- 
2.1.0

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[PATCH 19/49] drm/i915/bxt: don't use unsupported port detection

[Imre Deak]

From: Vandana Kannan <vandana.kannan@intel.com>

The port detection register flags in SFUSE_STRAP and DDI_BUF_CTL_A are
not defined for BXT, so don't use them.

Suggested by Satheesh.

v2:
- DDI_BUF_CTL_A bit 0 is not useful on BXT. Making changes to use this
  bit when simulator or BXT is not applicable. Code re-arranged as per
  Damien's suggestion.

v3:
- clarify commit message, add code comment (imre)

Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> (v2)
Cc: M, Satheeshakrishna <satheeshakrishna.m@intel.com>
Cc: Lespiau, Damien <damien.lespiau@intel.com>
Cc: Shankar, Uma <uma.shankar@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 90b460c..e54e948 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12615,7 +12615,16 @@ static void intel_setup_outputs(struct drm_device *dev)
 	if (intel_crt_present(dev))
 		intel_crt_init(dev);
 
-	if (HAS_DDI(dev)) {
+	if (IS_BROXTON(dev)) {
+		/*
+		 * FIXME: Broxton doesn't support port detection via the
+		 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
+		 * detect the ports.
+		 */
+		intel_ddi_init(dev, PORT_A);
+		intel_ddi_init(dev, PORT_B);
+		intel_ddi_init(dev, PORT_C);
+	} else if (HAS_DDI(dev)) {
 		int found;
 
 		/*
-- 
2.1.0

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[PATCH 20/49] drm/i915/bxt: Add change to support gmbus pin pair for BXT

[Imre Deak]

From: "A.Sunil Kamath" <sunil.kamath@intel.com>

For BXT gmbus is pulled from GPU to CPU. From implementation
point of view only pin pair configuration will change. The
existing implementation supports all platforms previous to GEN8
and also SKL. But for BXT pin pair configuration
is completely different than SKL or other previous GEN's.
This patch introduces the new pin pair configuration structure
specific to BXT and also ensures every real gmbus port has a
gpio pin.

Tested on BDW hardware to confirm it doesnt break anything
in existing platform.

For BDW pin pair config will remain as:
gmbus[0]: Name = i915 gmbus ssc, gpio_reg = c5014, reg0 = 1
gmbus[1]: Name = i915 gmbus vga, gpio_reg = c5010, reg0 = 2
gmbus[2]: Name = i915 gmbus panel, gpio_reg = c5018, reg0 = 3
gmbus[3]: Name = i915 gmbus dpc, gpio_reg = c501c, reg0 = 4
gmbus[4]: Name = i915 gmbus dpb, gpio_reg = c5020, reg0 = 5
gmbus[5]: Name = i915 gmbus dpd, gpio_reg = c5024, reg0 = 6

BXT will have:
gmbus[0]: name = i915 gmbus None, gpio_reg = 0, reg0 = 0
gmbus[1]: name = i915 gmbus None, gpio_reg = 0, reg0 = 0
gmbus[2]: name = i915 gmbus None, gpio_reg = 0, reg0 = 0
gmbus[3]: name = i915 gmbus dpc, gpio_reg = c5018, reg0 = 2
gmbus[4]: name = i915 gmbus dpb, gpio_reg = c5014, reg0 = 1
gmbus[5]: name = i915 gmbus misc, gpio_reg = c501c, reg0 = 3

Values of GMBUS_PORT_DPB, GMBUS_PORT_DPC, GMBUS_PORT_DPD is
retained as it is like other platforms. Only logic in gmbus
structure creation is changed to minimize changes in multiple
files.

v1: Initial release
Structure gmbus_ports_bxt  created for 3 ports only.
Here for BXT, gmbus[0], gmbus[1], gmbus[2] is untouched.
Logic used to calculate pin from respective register address as:
pin = reg & 0x000f >> 2

v2: Incorporated review comments from Jani Nikula.
Added a full bxt specific gmbus_ports_bxt and used it for bxt
regardless of pin >= 4.
Added const char *name and initialized it conditionally to
IS_BROXTON() so and avoided duplication of snprintf.
Added port_to_pin_bxt(port) function which returns right
pin value for a port for bxt platform.

Issue: VIZ-3574
Signed-off-by: A.Sunil Kamath <sunil.kamath@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/intel_i2c.c | 55 +++++++++++++++++++++++++++++++++++-----
 1 file changed, 49 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index b31088a..3aa31e1 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -48,6 +48,16 @@ static const struct gmbus_port gmbus_ports[] = {
 	{ "dpd", GPIOF },
 };
 
+/* gmbus pin pair configuration for bxt */
+static const struct gmbus_port gmbus_ports_bxt[] = {
+	{ "None", 0 },
+	{ "None", 0 },
+	{ "None", 0 },
+	{ "dpc", PCH_GPIOC },
+	{ "dpb", PCH_GPIOB },
+	{ "misc", PCH_GPIOD },
+};
+
 /* Intel GPIO access functions */
 
 #define I2C_RISEFALL_TIME 10
@@ -185,12 +195,17 @@ static void
 intel_gpio_setup(struct intel_gmbus *bus, u32 pin)
 {
 	struct drm_i915_private *dev_priv = bus->dev_priv;
+	struct drm_device *dev = dev_priv->dev;
 	struct i2c_algo_bit_data *algo;
 
 	algo = &bus->bit_algo;
 
 	/* -1 to map pin pair to gmbus index */
-	bus->gpio_reg = dev_priv->gpio_mmio_base + gmbus_ports[pin - 1].reg;
+	if (IS_BROXTON(dev))
+		bus->gpio_reg = gmbus_ports_bxt[pin - 1].reg;
+	else
+		bus->gpio_reg = dev_priv->gpio_mmio_base
+				+ gmbus_ports[pin - 1].reg;
 
 	bus->adapter.algo_data = algo;
 	algo->setsda = set_data;
@@ -510,6 +525,27 @@ static const struct i2c_algorithm gmbus_algorithm = {
 	.functionality	= gmbus_func
 };
 
+/* returns mapped pin for a port in BXT */
+static u32 port_to_pin_bxt(u32 port)
+{
+	u32 pin;
+
+	switch (port) {
+	case GMBUS_PORT_DPB:
+		pin = 1;
+		break;
+	case GMBUS_PORT_DPC:
+		pin = 2;
+		break;
+	case GMBUS_PORT_DPD:
+		pin = 3;
+		break;
+	default:
+		pin = 0;
+	}
+	return pin;
+}
+
 /**
  * intel_gmbus_setup - instantiate all Intel i2c GMBuses
  * @dev: DRM device
@@ -534,13 +570,17 @@ int intel_setup_gmbus(struct drm_device *dev)
 	for (i = 0; i < GMBUS_NUM_PORTS; i++) {
 		struct intel_gmbus *bus = &dev_priv->gmbus[i];
 		u32 port = i + 1; /* +1 to map gmbus index to pin pair */
+		const char *name;
 
 		bus->adapter.owner = THIS_MODULE;
 		bus->adapter.class = I2C_CLASS_DDC;
-		snprintf(bus->adapter.name,
-			 sizeof(bus->adapter.name),
-			 "i915 gmbus %s",
-			 gmbus_ports[i].name);
+		if (IS_BROXTON(dev))
+			name = gmbus_ports_bxt[i].name;
+		else
+			name = gmbus_ports[i].name;
+
+		snprintf(bus->adapter.name, sizeof(bus->adapter.name),
+			 "i915 gmbus %s", name);
 
 		bus->adapter.dev.parent = &dev->pdev->dev;
 		bus->dev_priv = dev_priv;
@@ -548,7 +588,10 @@ int intel_setup_gmbus(struct drm_device *dev)
 		bus->adapter.algo = &gmbus_algorithm;
 
 		/* By default use a conservative clock rate */
-		bus->reg0 = port | GMBUS_RATE_100KHZ;
+		if (IS_BROXTON(dev))
+			bus->reg0 = port_to_pin_bxt(port) | GMBUS_RATE_100KHZ;
+		else
+			bus->reg0 = port | GMBUS_RATE_100KHZ;
 
 		/* gmbus seems to be broken on i830 */
 		if (IS_I830(dev))
-- 
2.1.0

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[PATCH 21/49] drm/i915/bxt: WARN in case BXT unused gmbus ports are accessed

[Imre Deak]

From: "A.Sunil Kamath" <sunil.kamath@intel.com>

This patch will WARN if unused gmbus ports gets accessed for
BXT using gmbus_get_adapter also ensure that only valid ports
of BXT gets used. For BXT its more important to do this as it
has only 3 valid ports and structure has empty content otherwise.

Because of additonal IS_BROXTON check an additional "dev"
argument is added to intel_gmbus_is_port_valid. Also added
related changes in other places from where this function is accessed.

v1: This WARN patch is added as per review comments from
Daniel Vetter on gmbus BXT patch

v2: Changed get_adapter to have only one is_port_valid call
according to review comments from M Satheeshakrishna.

v3: Early bail out on errors according to review comments from
Daniel Vetter.

Issue: VIZ-3574
Signed-off-by: A.Sunil Kamath <sunil.kamath@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h   | 8 ++++++--
 drivers/gpu/drm/i915/intel_bios.c | 3 ++-
 drivers/gpu/drm/i915/intel_dvo.c  | 2 +-
 drivers/gpu/drm/i915/intel_i2c.c  | 9 ++++++---
 drivers/gpu/drm/i915/intel_lvds.c | 2 +-
 drivers/gpu/drm/i915/intel_sdvo.c | 4 +++-
 6 files changed, 19 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8fb7cc0..52e5f18 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3037,9 +3037,13 @@ void i915_teardown_sysfs(struct drm_device *dev_priv);
 /* intel_i2c.c */
 extern int intel_setup_gmbus(struct drm_device *dev);
 extern void intel_teardown_gmbus(struct drm_device *dev);
-static inline bool intel_gmbus_is_port_valid(unsigned port)
+static inline bool
+intel_gmbus_is_port_valid(struct drm_device *dev, unsigned port)
 {
-	return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
+	if (IS_BROXTON(dev))
+		return port >= GMBUS_PORT_DPC && port <= GMBUS_PORT_DPD;
+	else
+		return port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD;
 }
 
 extern struct i2c_adapter *intel_gmbus_get_adapter(
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index c684085..e423cc8 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -431,6 +431,7 @@ parse_general_definitions(struct drm_i915_private *dev_priv,
 			  struct bdb_header *bdb)
 {
 	struct bdb_general_definitions *general;
+	struct drm_device *dev = dev_priv->dev;
 
 	general = find_section(bdb, BDB_GENERAL_DEFINITIONS);
 	if (general) {
@@ -438,7 +439,7 @@ parse_general_definitions(struct drm_i915_private *dev_priv,
 		if (block_size >= sizeof(*general)) {
 			int bus_pin = general->crt_ddc_gmbus_pin;
 			DRM_DEBUG_KMS("crt_ddc_bus_pin: %d\n", bus_pin);
-			if (intel_gmbus_is_port_valid(bus_pin))
+			if (intel_gmbus_is_port_valid(dev, bus_pin))
 				dev_priv->vbt.crt_ddc_pin = bus_pin;
 		} else {
 			DRM_DEBUG_KMS("BDB_GD too small (%d). Invalid.\n",
diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c
index d857951..27d5b9a 100644
--- a/drivers/gpu/drm/i915/intel_dvo.c
+++ b/drivers/gpu/drm/i915/intel_dvo.c
@@ -499,7 +499,7 @@ void intel_dvo_init(struct drm_device *dev)
 		 * special cases, but otherwise default to what's defined
 		 * in the spec.
 		 */
-		if (intel_gmbus_is_port_valid(dvo->gpio))
+		if (intel_gmbus_is_port_valid(dev, dvo->gpio))
 			gpio = dvo->gpio;
 		else if (dvo->type == INTEL_DVO_CHIP_LVDS)
 			gpio = GMBUS_PORT_SSC;
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index 3aa31e1..06892b5 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -619,10 +619,13 @@ err:
 struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv,
 					    unsigned port)
 {
-	WARN_ON(!intel_gmbus_is_port_valid(port));
+	struct drm_device *dev = dev_priv->dev;
+
+	if (WARN_ON(!intel_gmbus_is_port_valid(dev, port)))
+		return NULL;
+
 	/* -1 to map pin pair to gmbus index */
-	return (intel_gmbus_is_port_valid(port)) ?
-		&dev_priv->gmbus[port - 1].adapter : NULL;
+	return &dev_priv->gmbus[port - 1].adapter;
 }
 
 void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 24e8730..094b88e 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -780,7 +780,7 @@ static bool lvds_is_present_in_vbt(struct drm_device *dev,
 		    child->device_type != DEVICE_TYPE_LFP)
 			continue;
 
-		if (intel_gmbus_is_port_valid(child->i2c_pin))
+		if (intel_gmbus_is_port_valid(dev, child->i2c_pin))
 			*i2c_pin = child->i2c_pin;
 
 		/* However, we cannot trust the BIOS writers to populate
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 9e554c2..d68936e 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -2283,6 +2283,7 @@ intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
 			  struct intel_sdvo *sdvo, u32 reg)
 {
 	struct sdvo_device_mapping *mapping;
+	struct drm_device *dev = dev_priv->dev;
 	u8 pin;
 
 	if (sdvo->is_sdvob)
@@ -2290,7 +2291,8 @@ intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
 	else
 		mapping = &dev_priv->sdvo_mappings[1];
 
-	if (mapping->initialized && intel_gmbus_is_port_valid(mapping->i2c_pin))
+	if (mapping->initialized &&
+		intel_gmbus_is_port_valid(dev, mapping->i2c_pin))
 		pin = mapping->i2c_pin;
 	else
 		pin = GMBUS_PORT_DPB;
-- 
2.1.0

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[PATCH 22/49] drm/i915/bxt: Avoid registering unused gmbus ports as i2c adapter

[Imre Deak]

From: "A.Sunil Kamath" <sunil.kamath@intel.com>

Though we populate all gmbus ports during setup_gmbus, only
valid ones should be registered to i2c adapters. This is
important as userspace can directly interact with the i2c bus.

While populating gmbus register we ensure that unused ports
will have gpio_reg value set as 0. This patch ensures that
only those with non zero gpio reg will get registered as i2c
adapter and this is applicable for all platforms.

del_adapter will check if the adaptor was really added
before, still its better to avoid unnecessary calls to the same.
This patch also adds a check to deregister only added i2c adapters.

Tested using i2c-tools to confirm that only valid gmbus ports
are registered as i2c adapter.

BXT will have only valid i2c adapters as below:
i2c-x      i2c     i915 gmbus dpc      I2C adapter
i2c-x+1    i2c     i915 gmbus dpb      I2C adapter
i2c-x+2    i2c     i915 gmbus misc     I2C adapter

v1: This patch is added as per review comments from
Daniel Vetter on gmbus BXT patch

Issue: VIZ-3574
Signed-off-by: A.Sunil Kamath <sunil.kamath@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/intel_i2c.c | 15 ++++++++++-----
 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index 06892b5..d5ca310 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -599,9 +599,12 @@ int intel_setup_gmbus(struct drm_device *dev)
 
 		intel_gpio_setup(bus, port);
 
-		ret = i2c_add_adapter(&bus->adapter);
-		if (ret)
-			goto err;
+		/* Do not register unused gmbus ports as i2c adapter */
+		if (bus->gpio_reg) {
+			ret = i2c_add_adapter(&bus->adapter);
+			if (ret)
+				goto err;
+		}
 	}
 
 	intel_i2c_reset(dev_priv->dev);
@@ -611,7 +614,8 @@ int intel_setup_gmbus(struct drm_device *dev)
 err:
 	while (--i) {
 		struct intel_gmbus *bus = &dev_priv->gmbus[i];
-		i2c_del_adapter(&bus->adapter);
+		if (bus->gpio_reg)
+			i2c_del_adapter(&bus->adapter);
 	}
 	return ret;
 }
@@ -652,6 +656,7 @@ void intel_teardown_gmbus(struct drm_device *dev)
 
 	for (i = 0; i < GMBUS_NUM_PORTS; i++) {
 		struct intel_gmbus *bus = &dev_priv->gmbus[i];
-		i2c_del_adapter(&bus->adapter);
+		if (bus->gpio_reg)
+			i2c_del_adapter(&bus->adapter);
 	}
 }
-- 
2.1.0

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[PATCH 23/49] drm/i915/bxt: Increase DDI buf idle timeout

[Imre Deak]

From: Vandana Kannan <vandana.kannan@intel.com>

For BXT, DDI buf idle timeout delay needs to be increased to 16us.

Since this is a timeout value and we return as soon as the condition is
realized, no penalty incurred for other platforms.

Suggested-by: Satheeshakrishna M <satheeshakrishna.m@intel.com>
Cc: Satheeshakrishna M <satheeshakrishna.m@intel.com>
Cc: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  | 1 +
 drivers/gpu/drm/i915/intel_ddi.c | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d69d7b9..60ff760 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6576,6 +6576,7 @@ enum skl_disp_power_wells {
 #define  DDI_BUF_EMP_MASK			(0xf<<24)
 #define  DDI_BUF_PORT_REVERSAL			(1<<16)
 #define  DDI_BUF_IS_IDLE			(1<<7)
+#define  DDI_BUF_IDLE_TIMEOUT			16	  /* 16us */
 #define  DDI_A_4_LANES				(1<<4)
 #define  DDI_PORT_WIDTH(width)			(((width) - 1) << 1)
 #define  DDI_INIT_DISPLAY_DETECTED		(1<<0)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 8aee7d7..a203d9d 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -322,7 +322,7 @@ static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
 	uint32_t reg = DDI_BUF_CTL(port);
 	int i;
 
-	for (i = 0; i < 8; i++) {
+	for (i = 0; i < DDI_BUF_IDLE_TIMEOUT; i++) {
 		udelay(1);
 		if (I915_READ(reg) & DDI_BUF_IS_IDLE)
 			return;
-- 
2.1.0

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[PATCH 24/49] drm/i915/bxt: DDI Hotplug interrupt setup

[Imre Deak]

From: Shashank Sharma <shashank.sharma@intel.com>

In BXT, DDI hotplug control has been moved to CPU from PCH.
This patch adds a new IRQ setup function for BXT which:
1. Checks which HPD ports are requested to be enabled by encoders.
2. Enables those ports in the hot plug control register.
3. Un-masks these port interrupts in the IMR register.
4. Enables these port interrupts in the IER register.

V3: Kept the default HPD filter count to default (500 us) as per
    satheesh's comment
v4: Remove unused HPD filter defines (Damien)
v5: warn if trying to setup HPD on port A (imre)

Reviewed-by: Satheeshakrishna M <satheeshakrishna.m@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com> (v4)
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 49 ++++++++++++++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/i915_reg.h | 25 +++++++++++++++++++++
 2 files changed, 73 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 49ad5fb..a51c00e 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -88,6 +88,12 @@ static const u32 hpd_status_i915[HPD_NUM_PINS] = { /* i915 and valleyview are th
 	[HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
 };
 
+/* BXT hpd list */
+static const u32 hpd_bxt[] = {
+	[HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
+	[HPD_PORT_C] = BXT_DE_PORT_HP_DDIC
+};
+
 /* IIR can theoretically queue up two events. Be paranoid. */
 #define GEN8_IRQ_RESET_NDX(type, which) do { \
 	I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
@@ -3235,6 +3241,44 @@ static void ibx_hpd_irq_setup(struct drm_device *dev)
 	I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
 }
 
+static void bxt_hpd_irq_setup(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_mode_config *mode_config = &dev->mode_config;
+	struct intel_encoder *intel_encoder;
+	u32 hotplug_port = 0;
+	u32 hotplug_ctrl;
+
+	/* Now, enable HPD */
+	list_for_each_entry(intel_encoder, &mode_config->encoder_list,
+		base.head) {
+		if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark
+				== HPD_ENABLED)
+			hotplug_port |= hpd_bxt[intel_encoder->hpd_pin];
+	}
+
+	/* Mask all HPD control bits */
+	hotplug_ctrl = I915_READ(BXT_HOTPLUG_CTL) & ~BXT_HOTPLUG_CTL_MASK;
+
+	/* Enable requested port in hotplug control */
+	/* TODO: implement (short) HPD support on port A */
+	WARN_ON_ONCE(hotplug_port & BXT_DE_PORT_HP_DDIA);
+	if (hotplug_port & BXT_DE_PORT_HP_DDIB)
+		hotplug_ctrl |= BXT_DDIB_HPD_ENABLE;
+	if (hotplug_port & BXT_DE_PORT_HP_DDIC)
+		hotplug_ctrl |= BXT_DDIC_HPD_ENABLE;
+	I915_WRITE(BXT_HOTPLUG_CTL, hotplug_ctrl);
+
+	/* Unmask DDI hotplug in IMR */
+	hotplug_ctrl = I915_READ(GEN8_DE_PORT_IMR) & ~hotplug_port;
+	I915_WRITE(GEN8_DE_PORT_IMR, hotplug_ctrl);
+
+	/* Enable DDI hotplug in IER */
+	hotplug_ctrl = I915_READ(GEN8_DE_PORT_IER) | hotplug_port;
+	I915_WRITE(GEN8_DE_PORT_IER, hotplug_ctrl);
+	POSTING_READ(GEN8_DE_PORT_IER);
+}
+
 static void ibx_irq_postinstall(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -4355,7 +4399,10 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
 		dev->driver->irq_uninstall = gen8_irq_uninstall;
 		dev->driver->enable_vblank = gen8_enable_vblank;
 		dev->driver->disable_vblank = gen8_disable_vblank;
-		dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
+		if (HAS_PCH_SPLIT(dev))
+			dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
+		else
+			dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
 	} else if (HAS_PCH_SPLIT(dev)) {
 		dev->driver->irq_handler = ironlake_irq_handler;
 		dev->driver->irq_preinstall = ironlake_irq_reset;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 60ff760..1efee7d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5247,6 +5247,14 @@ enum skl_disp_power_wells {
 #define  GEN9_AUX_CHANNEL_B		(1 << 25)
 #define  GEN8_AUX_CHANNEL_A		(1 << 0)
 
+/* Gen 9 BXT DDI Hotplug */
+#define BXT_DE_PORT_HP_DDIC		(1 << 5)
+#define BXT_DE_PORT_HP_DDIB		(1 << 4)
+#define BXT_DE_PORT_HP_DDIA		(1 << 3)
+#define BXT_DE_PORT_HOTPLUG_MASK	(BXT_DE_PORT_HP_DDIA | \
+					BXT_DE_PORT_HP_DDIB | \
+					BXT_DE_PORT_HP_DDIC)
+
 #define GEN8_DE_MISC_ISR 0x44460
 #define GEN8_DE_MISC_IMR 0x44464
 #define GEN8_DE_MISC_IIR 0x44468
@@ -5258,6 +5266,23 @@ enum skl_disp_power_wells {
 #define GEN8_PCU_IIR 0x444e8
 #define GEN8_PCU_IER 0x444ec
 
+/* BXT hotplug control */
+#define BXT_HOTPLUG_CTL		0xC4030
+#define BXT_DDIA_HPD_ENABLE		(1 << 28)
+#define BXT_DDIB_HPD_ENABLE		(1 << 4)
+#define BXT_DDIC_HPD_ENABLE		(1 << 12)
+#define BXT_HOTPLUG_CTL_MASK		(BXT_DDIA_HPD_ENABLE | \
+					BXT_DDIB_HPD_ENABLE | \
+					BXT_DDIC_HPD_ENABLE)
+
+/* Hot plug status */
+#define BXT_DDIA_HPD_STATUS		(3 << 24)
+#define BXT_DDIB_HPD_STATUS		(3 << 0)
+#define BXT_DDIC_HPD_STATUS		(3 << 8)
+#define BXT_HPD_STATUS_MASK		(BXT_DDIA_HPD_STATUS | \
+					BXT_DDIB_HPD_STATUS | \
+					BXT_DDIC_HPD_STATUS)
+
 #define ILK_DISPLAY_CHICKEN2	0x42004
 /* Required on all Ironlake and Sandybridge according to the B-Spec. */
 #define  ILK_ELPIN_409_SELECT	(1 << 25)
-- 
2.1.0

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[PATCH 25/49] drm/i915/bxt: Add DDI hpd handler

[Imre Deak]

From: Shashank Sharma <shashank.sharma@intel.com>

This patch adds a hot plug interrupt handler function for BXT.
What this function typically does is:
1. Check if hot plug is enabled from hot plug control register.
2. Call hpd_irq_handler with appropriate trigger to detect a
   plug storm and schedule a bottom half.
3. Clear sticky status bits in hot plug control register..

Reviewed-by: Satheeshakrishna M <satheeshakrishna.m@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 45 +++++++++++++++++++++++++++++++++++++++--
 1 file changed, 43 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index a51c00e..4a2f85b 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2227,6 +2227,38 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg)
 	return ret;
 }
 
+static void bxt_hpd_handler(struct drm_device *dev, uint32_t iir_status)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	uint32_t hp_control;
+	uint32_t hp_trigger;
+
+	/* Get the status */
+	hp_trigger = iir_status & BXT_DE_PORT_HOTPLUG_MASK;
+	hp_control = I915_READ(BXT_HOTPLUG_CTL);
+
+	/* Hotplug not enabled ? */
+	if (unlikely(!(hp_control & BXT_HOTPLUG_CTL_MASK))) {
+		DRM_ERROR("Interrupt when HPD disabled\n");
+		return;
+	}
+
+	DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
+		hp_control & BXT_HOTPLUG_CTL_MASK);
+
+	/* Check for HPD storm and schedule bottom half */
+	intel_hpd_irq_handler(dev, hp_trigger, hp_control, hpd_bxt);
+
+	/*
+	 * Todo: Save the hot plug status for bottom half before
+	 * clearing the sticky status bits, else the status will be
+	 * lost.
+	 */
+
+	/* Clear sticky bits in hpd status */
+	I915_WRITE(BXT_HOTPLUG_CTL, hp_control);
+}
+
 static irqreturn_t gen8_irq_handler(int irq, void *arg)
 {
 	struct drm_device *dev = arg;
@@ -2236,6 +2268,7 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
 	uint32_t tmp = 0;
 	enum pipe pipe;
 	u32 aux_mask = GEN8_AUX_CHANNEL_A;
+	bool found = false;
 
 	if (!intel_irqs_enabled(dev_priv))
 		return IRQ_NONE;
@@ -2276,9 +2309,17 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
 			I915_WRITE(GEN8_DE_PORT_IIR, tmp);
 			ret = IRQ_HANDLED;
 
-			if (tmp & aux_mask)
+			if (tmp & aux_mask) {
 				dp_aux_irq_handler(dev);
-			else
+				found = true;
+			}
+
+			if (tmp & BXT_DE_PORT_HOTPLUG_MASK) {
+				bxt_hpd_handler(dev, tmp);
+				found = true;
+			}
+
+			if (!found)
 				DRM_ERROR("Unexpected DE Port interrupt\n");
 		}
 		else
-- 
2.1.0

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[PATCH 26/49] drm/i915/bxt: Add BXT support in gen8_irq functions

[Imre Deak]

From: Shashank Sharma <shashank.sharma@intel.com>

This patch adds conditional checks in gen8_irq functions
to support BXT. Most of the checks just look for PCH split
availability, and block the call to PCH interrupt functions if
not available.

Reviewed-by: Satheeshakrishna M <satheeshakrishna.m@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Shashank Sharma <ppashank.sharma@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 4a2f85b..3b82eb2 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2372,7 +2372,13 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
 			DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
 	}
 
-	if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) {
+	/*
+	 * Todo: BXT doesnt have a PCH, so GEN8_DE_PCH_IRQ shouldn't
+	 * be set. But until this part is confirmed, going paranoid, and adding
+	 * a IS_BROXTON check here.
+	 */
+	if (!IS_BROXTON(dev) && !HAS_PCH_NOP(dev) &&
+			master_ctl & GEN8_DE_PCH_IRQ) {
 		/*
 		 * FIXME(BDW): Assume for now that the new interrupt handling
 		 * scheme also closed the SDE interrupt handling race we've seen
@@ -3096,7 +3102,7 @@ static void ibx_irq_reset(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
-	if (HAS_PCH_NOP(dev))
+	if (HAS_PCH_NOP(dev) || !HAS_PCH_SPLIT(dev))
 		return;
 
 	GEN5_IRQ_RESET(SDE);
@@ -3117,7 +3123,7 @@ static void ibx_irq_pre_postinstall(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
-	if (HAS_PCH_NOP(dev))
+	if (HAS_PCH_NOP(dev) || !HAS_PCH_SPLIT(dev))
 		return;
 
 	WARN_ON(I915_READ(SDEIER) != 0);
@@ -3325,7 +3331,7 @@ static void ibx_irq_postinstall(struct drm_device *dev)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 mask;
 
-	if (HAS_PCH_NOP(dev))
+	if (HAS_PCH_NOP(dev) || !HAS_PCH_SPLIT(dev))
 		return;
 
 	if (HAS_PCH_IBX(dev))
-- 
2.1.0

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[PATCH 27/49] drm/i915/bxt: Enable GMBUS IRQ

[Imre Deak]

From: Shashank Sharma <shashank.sharma@intel.com>

GMBUS interrupt has been moved to CPU side in BXT.
What this patch does is:
1. Enable GMBUS IRQ in de_post_install function
2. Handle this interrupt as a port interrupt in display irq
   handler

v2: Rebase on top of the for_each_pipe() change adding dev_priv as
    first argument (Damien).
v3: read BXT_DE_PORT_GMBUS IIR flag only on BXT on other platforms
    it's reserved (imre)

Reviewed-by: Satheeshakrishna M <satheeshakrishna.m@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com> (v1)
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 14 +++++++++++---
 drivers/gpu/drm/i915/i915_reg.h |  3 +++
 2 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 3b82eb2..2be167c 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2319,6 +2319,11 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
 				found = true;
 			}
 
+			if (IS_BROXTON(dev) && (tmp & BXT_DE_PORT_GMBUS)) {
+				gmbus_irq_handler(dev);
+				found = true;
+			}
+
 			if (!found)
 				DRM_ERROR("Unexpected DE Port interrupt\n");
 		}
@@ -3596,13 +3601,16 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
 	uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
 	uint32_t de_pipe_enables;
 	int pipe;
-	u32 aux_en = GEN8_AUX_CHANNEL_A;
+	u32 de_port_en = GEN8_AUX_CHANNEL_A;
 
 	if (IS_GEN9(dev_priv)) {
 		de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
 				  GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
-		aux_en |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
+		de_port_en |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
 			GEN9_AUX_CHANNEL_D;
+
+		if (IS_BROXTON(dev_priv))
+			de_port_en |= BXT_DE_PORT_GMBUS;
 	} else
 		de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
 				  GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
@@ -3621,7 +3629,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
 					  dev_priv->de_irq_mask[pipe],
 					  de_pipe_enables);
 
-	GEN5_IRQ_INIT(GEN8_DE_PORT_, ~aux_en, aux_en);
+	GEN5_IRQ_INIT(GEN8_DE_PORT_, ~de_port_en, de_port_en);
 }
 
 static int gen8_irq_postinstall(struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1efee7d..b4474d3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5255,6 +5255,9 @@ enum skl_disp_power_wells {
 					BXT_DE_PORT_HP_DDIB | \
 					BXT_DE_PORT_HP_DDIC)
 
+/* BXT GMBUS */
+#define BXT_DE_PORT_GMBUS	(1 << 1)
+
 #define GEN8_DE_MISC_ISR 0x44460
 #define GEN8_DE_MISC_IMR 0x44464
 #define GEN8_DE_MISC_IIR 0x44468
-- 
2.1.0

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[PATCH 28/49] drm/i915/bxt: Define BXT power domains

[Imre Deak]

From: Satheeshakrishna M <satheeshakrishna.m@intel.com>

Add BXT power domains

v2: Use DOMAIN_PLLS instead of a new CDCLK one, whitespace fixes
    (Damien)
v3: add VGA, TRANSCODER_A power domains (imre)

Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> (v1)
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> (v2)
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/intel_runtime_pm.c | 55 +++++++++++++++++++++++++++++++++
 1 file changed, 55 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index ce00e69..ff5cce3 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -319,6 +319,38 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv,
 	SKL_DISPLAY_MISC_IO_POWER_DOMAINS)) |		\
 	BIT(POWER_DOMAIN_INIT))
 
+#define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS (		\
+	BIT(POWER_DOMAIN_TRANSCODER_A) |		\
+	BIT(POWER_DOMAIN_PIPE_B) |			\
+	BIT(POWER_DOMAIN_TRANSCODER_B) |		\
+	BIT(POWER_DOMAIN_PIPE_C) |			\
+	BIT(POWER_DOMAIN_TRANSCODER_C) |		\
+	BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |		\
+	BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |		\
+	BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |		\
+	BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |		\
+	BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |		\
+	BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |		\
+	BIT(POWER_DOMAIN_AUX_B) |			\
+	BIT(POWER_DOMAIN_AUX_C) |			\
+	BIT(POWER_DOMAIN_AUDIO) |			\
+	BIT(POWER_DOMAIN_VGA) |				\
+	BIT(POWER_DOMAIN_INIT))
+#define BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS (		\
+	BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS |		\
+	BIT(POWER_DOMAIN_PIPE_A) |			\
+	BIT(POWER_DOMAIN_TRANSCODER_EDP) |		\
+	BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) |		\
+	BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) |		\
+	BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) |		\
+	BIT(POWER_DOMAIN_AUX_A) |			\
+	BIT(POWER_DOMAIN_PLLS) |			\
+	BIT(POWER_DOMAIN_INIT))
+#define BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS (		\
+	(POWER_DOMAIN_MASK & ~(BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS |	\
+	BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) |	\
+	BIT(POWER_DOMAIN_INIT))
+
 static void skl_set_power_well(struct drm_i915_private *dev_priv,
 			struct i915_power_well *power_well, bool enable)
 {
@@ -1313,6 +1345,27 @@ static struct i915_power_well skl_power_wells[] = {
 	},
 };
 
+static struct i915_power_well bxt_power_wells[] = {
+	{
+		.name = "always-on",
+		.always_on = 1,
+		.domains = BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS,
+		.ops = &i9xx_always_on_power_well_ops,
+	},
+	{
+		.name = "power well 1",
+		.domains = BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS,
+		.ops = &skl_power_well_ops,
+		.data = SKL_DISP_PW_1,
+	},
+	{
+		.name = "power well 2",
+		.domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
+		.ops = &skl_power_well_ops,
+		.data = SKL_DISP_PW_2,
+	}
+};
+
 #define set_power_wells(power_domains, __power_wells) ({		\
 	(power_domains)->power_wells = (__power_wells);			\
 	(power_domains)->power_well_count = ARRAY_SIZE(__power_wells);	\
@@ -1341,6 +1394,8 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
 		set_power_wells(power_domains, bdw_power_wells);
 	} else if (IS_SKYLAKE(dev_priv->dev)) {
 		set_power_wells(power_domains, skl_power_wells);
+	} else if (IS_BROXTON(dev_priv->dev)) {
+		set_power_wells(power_domains, bxt_power_wells);
 	} else if (IS_CHERRYVIEW(dev_priv->dev)) {
 		set_power_wells(power_domains, chv_power_wells);
 	} else if (IS_VALLEYVIEW(dev_priv->dev)) {
-- 
2.1.0

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[PATCH 29/49] drm/i915: Rename vlv_cdclk_freq to cdclk_freq

[Imre Deak]

From: Vandana Kannan <vandana.kannan@intel.com>

Rename vlv_cdclk_freq to cdclk_freq so that it can be used for all
platforms as required. Needed by the next patch.

Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
Signed-off-by: A.Sunil Kamath <sunil.kamath@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h      |  2 +-
 drivers/gpu/drm/i915/intel_display.c | 18 ++++++++++--------
 2 files changed, 11 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 52e5f18..1b2a294 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1659,7 +1659,7 @@ struct drm_i915_private {
 	int num_fence_regs; /* 8 on pre-965, 16 otherwise */
 
 	unsigned int fsb_freq, mem_freq, is_ddr3;
-	unsigned int vlv_cdclk_freq;
+	unsigned int cdclk_freq;
 	unsigned int hpll_freq;
 
 	/**
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index e54e948..b91862e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4879,16 +4879,16 @@ static void vlv_update_cdclk(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
-	dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
+	dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
 	DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
-			 dev_priv->vlv_cdclk_freq);
+			 dev_priv->cdclk_freq);
 
 	/*
 	 * Program the gmbus_freq based on the cdclk frequency.
 	 * BSpec erroneously claims we should aim for 4MHz, but
 	 * in fact 1MHz is the correct frequency.
 	 */
-	I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
+	I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
 }
 
 /* Adjust CDclk dividers to allow high res or save power if possible */
@@ -4897,7 +4897,8 @@ static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 val, cmd;
 
-	WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
+	WARN_ON(dev_priv->display.get_display_clock_speed(dev)
+					!= dev_priv->cdclk_freq);
 
 	if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
 		cmd = 2;
@@ -4961,7 +4962,8 @@ static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 val, cmd;
 
-	WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
+	WARN_ON(dev_priv->display.get_display_clock_speed(dev)
+						!= dev_priv->cdclk_freq);
 
 	switch (cdclk) {
 	case 333333:
@@ -5050,7 +5052,7 @@ static void valleyview_modeset_global_pipes(struct drm_device *dev,
 	int max_pixclk = intel_mode_max_pixclk(dev_priv);
 
 	if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
-	    dev_priv->vlv_cdclk_freq)
+	    dev_priv->cdclk_freq)
 		return;
 
 	/* disable/enable all currently active pipes while we change cdclk */
@@ -5068,7 +5070,7 @@ static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
 	else
 		default_credits = PFI_CREDIT(8);
 
-	if (DIV_ROUND_CLOSEST(dev_priv->vlv_cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
+	if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
 		/* CHV suggested value is 31 or 63 */
 		if (IS_CHERRYVIEW(dev_priv))
 			credits = PFI_CREDIT_31;
@@ -5101,7 +5103,7 @@ static void valleyview_modeset_global_resources(struct drm_device *dev)
 	int max_pixclk = intel_mode_max_pixclk(dev_priv);
 	int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
 
-	if (req_cdclk != dev_priv->vlv_cdclk_freq) {
+	if (req_cdclk != dev_priv->cdclk_freq) {
 		/*
 		 * FIXME: We can end up here with all power domains off, yet
 		 * with a CDCLK frequency other than the minimum. To account
-- 
2.1.0

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[PATCH 30/49] drm/i915/bxt: add display initialize/uninitialize sequence

[Imre Deak]

From: Vandana Kannan <vandana.kannan@intel.com>

Add display clock/PHY initialization sequence as per BSpec.

Until GOP/VBIOS provides an upper limit value for CDCLK, comparing clock
value with 624 MHz and returning 0 in case it exceeds.

Note that the CD clock and PHY initialization/uninitialization are done
at their current place only for simplicity, in a future patch - when more
of the runtime PM features will be enabled - these will be moved to
power well#1 and modeset encoder enabling/disabling hooks respectively.
This also means that atm dynamic power gating power well #2 is
effectively disabled.

v1: Added function definitions in header files
v2: Imre's review comments addressed
- Moved CDCLK related definitions to i915_reg.h
- Removed defintions for CDCLK frequency
- Split uninit_cdclk() by adding a phy_uninit function
- Calculate freq and decimal based on input frequency
- Program SSA precharge based on input frequency
- Use wait_for 1ms instead 200us udelay for DE PLL locking
- Removed initial value for divider, freq, decimal, ratio.
- Replaced polling loops with wait_for
- Parameterized latency optim setting
- Fix the parts where DE PLL has to be disabled.
- Call CDCLK selection from mode set

v3: (imre)
- add note about the plan to move the cdclk/phy init to a better place
- take rps.hw_lock around pcode access
- fix DDI PHY timeout value
- squash in Vandana's "PORT_CL2CM_DW6_A BUN fix",
  "DDI PHY programming register defn", "Do ddi_phy_init always",
  "Check CDCLK upper limit" patches
- move PHY register macros next to the corresponding CHV/VLV macros
- move DE PLL register macros here from another patch since they are
  used here first
- add BXT_ prefix to CDCLK flags
- s/COMMON_RESET/COMMON_RESET_DIS/ and clarify related code comments
- fix incorrect read value for the RMW of BXT_PHY_CTL_FAMILY_DDI
- fix using GT_DISPLAY_EDP_POWER_ON vs. GT_DISPLAY_DDI_POWER_ON
  when powering on DDI ports
- fix incorrect port when setting BXT_PORT_TX_DW14_LN for DDI ports
- add missing masking when programming CDCLK_FREQ_DECIMAL
- add missing powering on for DDI-C port, rename OCL2_LDOFUSE_PWR_EN
  to OCL2_LDOFUSE_PWR_DIS to reduce confusion
- add note about mismatch with bspec in the PORT_REF_DW6 fields
- factor out PHY init code to a new function, so we can call it for
  PHY_A and PHY_BC, instead of open-coding the same

Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> (v2)
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      | 126 +++++++++++++++
 drivers/gpu/drm/i915/intel_ddi.c     | 291 +++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_display.c |  75 +++++++++
 drivers/gpu/drm/i915/intel_drv.h     |   4 +
 4 files changed, 496 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b4474d3..a3579c0 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1120,6 +1120,110 @@ enum skl_disp_power_wells {
 #define   DPIO_FRC_LATENCY_SHFIT	8
 #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
 #define   DPIO_UPAR_SHIFT		30
+
+/* BXT PHY registers */
+enum bxt_phy {
+	BXT_PHY_A,
+	BXT_PHY_BC
+};
+
+#define BXT_PHY(phy, a, b)		((a) + (phy) * ((b) - (a)))
+
+#define BXT_P_CR_GT_DISP_PWRON_0_2_0_GTTMMADR	0x138090
+#define   _EDP_POWER_ON				(1 << 1)
+#define   _DDI_POWER_ON				(1 << 0)
+#define   GT_DISPLAY_POWER_ON(phy)		BXT_PHY(phy, _EDP_POWER_ON, \
+							_DDI_POWER_ON)
+
+#define _PHY_CTL_FAMILY_EDP		0x64C80
+#define _PHY_CTL_FAMILY_DDI		0x64C90
+#define   COMMON_RESET_DIS		(1 << 31)
+#define BXT_PHY_CTL_FAMILY(phy)		BXT_PHY(phy, _PHY_CTL_FAMILY_EDP, \
+						     _PHY_CTL_FAMILY_DDI)
+
+/* BXT PHY common lane registers */
+#define _PORT_CL1CM_DW0_A		0x162000
+#define _PORT_CL1CM_DW0_BC		0x6C000
+#define   PHY_POWER_GOOD		(1 << 16)
+#define BXT_PORT_CL1CM_DW0(phy)		BXT_PHY(phy, _PORT_CL1CM_DW0_A,	\
+						     _PORT_CL1CM_DW0_BC)
+
+#define _PORT_CL1CM_DW9_A		0x162024
+#define _PORT_CL1CM_DW9_BC		0x6C024
+#define   IREF0RC_OFFSET_SHIFT		8
+#define   IREF0RC_OFFSET_MASK		(0xFF << IREF0RC_OFFSET_SHIFT)
+#define BXT_PORT_CL1CM_DW9(phy)		BXT_PHY(phy, _PORT_CL1CM_DW9_A,	\
+						     _PORT_CL1CM_DW9_BC)
+
+#define _PORT_CL1CM_DW10_A		0x162028
+#define _PORT_CL1CM_DW10_BC		0x6C028
+#define   IREF1RC_OFFSET_SHIFT		8
+#define   IREF1RC_OFFSET_MASK		(0xFF << IREF1RC_OFFSET_SHIFT)
+#define BXT_PORT_CL1CM_DW10(phy)	BXT_PHY(phy, _PORT_CL1CM_DW10_A, \
+						     _PORT_CL1CM_DW10_BC)
+
+#define _PORT_CL1CM_DW28_A		0x162070
+#define _PORT_CL1CM_DW28_BC		0x6C070
+#define   OCL1_POWER_DOWN_EN		(1 << 23)
+#define   DW28_OLDO_DYN_PWR_DOWN_EN	(1 << 22)
+#define   SUS_CLK_CONFIG		0x3
+#define BXT_PORT_CL1CM_DW28(phy)	BXT_PHY(phy, _PORT_CL1CM_DW28_A, \
+						     _PORT_CL1CM_DW28_BC)
+
+#define _PORT_CL1CM_DW30_A		0x162078
+#define _PORT_CL1CM_DW30_BC		0x6C078
+#define   OCL2_LDOFUSE_PWR_DIS		(1 << 6)
+#define BXT_PORT_CL1CM_DW30(phy)	BXT_PHY(phy, _PORT_CL1CM_DW30_A, \
+						     _PORT_CL1CM_DW30_BC)
+
+/* Defined for PHY_BC only */
+#define BXT_PORT_CL2CM_DW6_BC		0x6C358
+#define   DW6_OLDO_DYN_PWR_DOWN_EN	(1 << 28)
+
+/* BXT PHY Ref registers */
+#define _PORT_REF_DW3_A			0x16218C
+#define _PORT_REF_DW3_BC		0x6C18C
+#define   GRC_DONE			(1 << 22)
+#define BXT_PORT_REF_DW3(phy)		BXT_PHY(phy, _PORT_REF_DW3_A,	\
+						     _PORT_REF_DW3_BC)
+
+#define _PORT_REF_DW6_A			0x162198
+#define _PORT_REF_DW6_BC		0x6C198
+/*
+ * FIXME: BSpec disagrees on the following two fields, check them with
+ * HW/documentation people.
+ */
+#define   GRC_CODE_SHIFT		23
+#define   GRC_CODE_MASK			(0x1FF << GRC_CODE_SHIFT)
+#define   GRC_CODE_FAST_SHIFT		16
+#define   GRC_CODE_FAST_MASK		(0x7F << GRC_CODE_FAST_SHIFT)
+#define   GRC_CODE_SLOW_SHIFT		8
+#define   GRC_CODE_SLOW_MASK		(0xFF << GRC_CODE_SLOW_SHIFT)
+#define   GRC_CODE_NOM_MASK		0xFF
+#define BXT_PORT_REF_DW6(phy)		BXT_PHY(phy, _PORT_REF_DW6_A,	\
+						     _PORT_REF_DW6_BC)
+
+#define _PORT_REF_DW8_A			0x1621A0
+#define _PORT_REF_DW8_BC		0x6C1A0
+#define   GRC_DIS			(1 << 15)
+#define   GRC_RDY_OVRD			(1 << 1)
+#define BXT_PORT_REF_DW8(phy)		BXT_PHY(phy, _PORT_REF_DW8_A,	\
+						     _PORT_REF_DW8_BC)
+
+/* BXT PHY TX registers */
+#define BXT_LANE_OFFSET(lane)           (((lane) >> 1) * 0x200 +	\
+					 ((lane) & 1) * 0x80)
+
+#define _PORT_TX_DW14_LN0_A		0x162538
+#define _PORT_TX_DW14_LN0_B		0x6C538
+#define _PORT_TX_DW14_LN0_C		0x6C938
+#define   LATENCY_OPTIM_SHIFT		30
+#define   LATENCY_OPTIM			(1 << LATENCY_OPTIM_SHIFT)
+#define BXT_PORT_TX_DW14_LN(port, lane)	(_PORT3(port, _PORT_TX_DW14_LN0_A,   \
+						      _PORT_TX_DW14_LN0_B,   \
+						      _PORT_TX_DW14_LN0_C) + \
+					 BXT_LANE_OFFSET(lane))
+
 /*
  * Fence registers
  */
@@ -5326,6 +5430,9 @@ enum skl_disp_power_wells {
 #define  DISP_FBC_WM_DIS		(1<<15)
 #define DISP_ARB_CTL2	0x45004
 #define  DISP_DATA_PARTITION_5_6	(1<<6)
+#define DBUF_CTL	0x45008
+#define  DBUF_POWER_REQUEST		(1<<31)
+#define  DBUF_POWER_STATE		(1<<30)
 #define GEN7_MSG_CTL	0x45010
 #define  WAIT_FOR_PCH_RESET_ACK		(1<<1)
 #define  WAIT_FOR_PCH_FLR_ACK		(1<<0)
@@ -6271,6 +6378,7 @@ enum skl_disp_power_wells {
 #define   GEN6_PCODE_WRITE_D_COMP		0x11
 #define   GEN6_ENCODE_RC6_VID(mv)		(((mv) - 245) / 5)
 #define   GEN6_DECODE_RC6_VID(vids)		(((vids) * 5) + 245)
+#define   DISPLAY_PCU_CONTROL			0x17
 #define   DISPLAY_IPS_CONTROL			0x19
 #define	  HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL	0x1A
 #define GEN6_PCODE_DATA				0x138128
@@ -6748,6 +6856,13 @@ enum skl_disp_power_wells {
 #define  CDCLK_FREQ_675_617		(3<<26)
 #define  CDCLK_FREQ_DECIMAL_MASK	(0x7ff)
 
+#define  BXT_CDCLK_CD2X_DIV_SEL_MASK	(3<<22)
+#define  BXT_CDCLK_CD2X_DIV_SEL_1	(0<<22)
+#define  BXT_CDCLK_CD2X_DIV_SEL_1_5	(1<<22)
+#define  BXT_CDCLK_CD2X_DIV_SEL_2	(2<<22)
+#define  BXT_CDCLK_CD2X_DIV_SEL_4	(3<<22)
+#define  BXT_CDCLK_SSA_PRECHARGE_ENABLE	(1<<16)
+
 /* LCPLL_CTL */
 #define LCPLL1_CTL		0x46010
 #define LCPLL2_CTL		0x46014
@@ -6812,6 +6927,17 @@ enum skl_disp_power_wells {
 #define GET_CFG_CR1_REG(id) (DPLL1_CFGCR1 + (id - SKL_DPLL1) * 8)
 #define GET_CFG_CR2_REG(id) (DPLL1_CFGCR2 + (id - SKL_DPLL1) * 8)
 
+/* BXT display engine PLL */
+#define BXT_DE_PLL_CTL			0x6d000
+#define   BXT_DE_PLL_RATIO_1152		0x3c
+#define   BXT_DE_PLL_RATIO_1248		0x41
+#define   BXT_DE_PLL_RATIO_DEFAULT	0x64
+#define   BXT_DE_PLL_RATIO_MASK		0x7f
+
+#define BXT_DE_PLL_ENABLE		0x46070
+#define   BXT_DE_PLL_PLL_ENABLE		(1 << 31)
+#define   BXT_DE_PLL_LOCK		(1 << 30)
+
 /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
  * since on HSW we can't write to it using I915_WRITE. */
 #define D_COMP_HSW			(MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index a203d9d..789682d 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1957,6 +1957,294 @@ static void skl_shared_dplls_init(struct drm_i915_private *dev_priv)
 	}
 }
 
+static void bxt_init_phy(struct drm_i915_private *dev_priv, enum bxt_phy phy)
+{
+	enum port port;
+	uint32_t val;
+
+	val = I915_READ(BXT_P_CR_GT_DISP_PWRON_0_2_0_GTTMMADR);
+	val |= GT_DISPLAY_POWER_ON(phy);
+	I915_WRITE(BXT_P_CR_GT_DISP_PWRON_0_2_0_GTTMMADR, val);
+
+	/* Considering 10ms timeout until BSpec is updated */
+	if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10))
+		DRM_ERROR("timeout during PHY#%d power on\n", phy);
+
+	/* Program latency optim setting */
+	for (port =  (phy == BXT_PHY_A ? PORT_A : PORT_B);
+	     port <= (phy == BXT_PHY_A ? PORT_A : PORT_C); port++) {
+		int lane;
+
+		for (lane = 0; lane < 4; lane++) {
+			val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
+			val &= ~LATENCY_OPTIM;
+			if (lane == 1)
+				val |= LATENCY_OPTIM;
+
+			I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val);
+		}
+	}
+
+	/* Program PLL Rcomp code offset */
+	val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
+	val &= ~IREF0RC_OFFSET_MASK;
+	val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
+	I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
+
+	val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
+	val &= ~IREF1RC_OFFSET_MASK;
+	val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
+	I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
+
+	/* Program power gating */
+	val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
+	val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
+		SUS_CLK_CONFIG;
+	I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
+
+	if (phy == BXT_PHY_BC) {
+		val = I915_READ(BXT_PORT_CL2CM_DW6_BC);
+		val |= DW6_OLDO_DYN_PWR_DOWN_EN;
+		I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val);
+	}
+
+	val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
+	val &= ~OCL2_LDOFUSE_PWR_DIS;
+	/*
+	 * On PHY_A disable power on the second channel, since no port is
+	 * connected there. On PHY_BC both channels have a port, so leave it
+	 * enabled.
+	 * Note that port C is only connected on BXT-P, so on BXT0/1 we should
+	 * power down the second channel on PHY_BC as well.
+	 */
+	if (phy == BXT_PHY_A)
+		val |= OCL2_LDOFUSE_PWR_DIS;
+	I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
+
+	if (phy == BXT_PHY_BC) {
+		uint32_t grc_code;
+		/*
+		 * PHY_BC isn't connected to an RCOMP resistor so copy over
+		 * the corresponding calibrated value from PHY_A, and disable
+		 * the automatic calibration on PHY_BC.
+		 */
+		if (wait_for(I915_READ(BXT_PORT_REF_DW3(BXT_PHY_A)) & GRC_DONE,
+			     10))
+			DRM_ERROR("timeout waiting for PHY#0 GRC\n");
+
+		val = I915_READ(BXT_PORT_REF_DW6(BXT_PHY_A));
+		val = (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
+		grc_code = val << GRC_CODE_FAST_SHIFT |
+			   val << GRC_CODE_SLOW_SHIFT |
+			   val;
+		I915_WRITE(BXT_PORT_REF_DW6(BXT_PHY_BC), grc_code);
+
+		val = I915_READ(BXT_PORT_REF_DW8(BXT_PHY_BC));
+		val |= GRC_DIS | GRC_RDY_OVRD;
+		I915_WRITE(BXT_PORT_REF_DW8(BXT_PHY_BC), val);
+	}
+
+	/* Release common_reset */
+	val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
+	val |= COMMON_RESET_DIS;
+	I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
+}
+
+void bxt_ddi_phy_init(struct drm_device *dev)
+{
+	/* Enable PHY_A first since it provides Rcomp for PHY_BC */
+	bxt_init_phy(dev->dev_private, BXT_PHY_A);
+	bxt_init_phy(dev->dev_private, BXT_PHY_BC);
+}
+
+static void bxt_ddi_phy_uninit(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	uint32_t temp;
+
+	temp = I915_READ(BXT_PHY_CTL_FAMILY(BXT_PHY_A));
+	I915_WRITE(BXT_PHY_CTL_FAMILY(BXT_PHY_A), temp & ~COMMON_RESET_DIS);
+
+	temp = I915_READ(BXT_PHY_CTL_FAMILY(BXT_PHY_BC));
+	I915_WRITE(BXT_PHY_CTL_FAMILY(BXT_PHY_BC), temp & ~COMMON_RESET_DIS);
+
+	I915_WRITE(BXT_P_CR_GT_DISP_PWRON_0_2_0_GTTMMADR, 0);
+}
+
+/*
+ * It is the responsibility of the caller to ensure that
+ * criteria for changing the CD clk frequency is met.
+ *
+ * This function only changes CD clock frequency.
+ * TODO:- 1. Add functions to change only the divider and
+ *	  2. call impacted functions like backlight, WiDi, watermark.
+*/
+void bxt_select_cdclk_freq(struct drm_device *dev, u32 frequency)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	uint32_t cdclk_ctl, decimal, ratio;
+	uint32_t divider, freq, current_freq;
+	int ret;
+
+	freq = (frequency / 1000 - 1) * 2;
+	decimal = DIV_ROUND_UP(frequency, 25000);
+
+	switch (frequency) {
+	case 144000:
+		divider = BXT_CDCLK_CD2X_DIV_SEL_4;
+		ratio = BXT_DE_PLL_RATIO_1152;
+		break;
+	case 288000:
+		divider = BXT_CDCLK_CD2X_DIV_SEL_2;
+		ratio = BXT_DE_PLL_RATIO_1152;
+		break;
+	case 384000:
+		divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
+		ratio = BXT_DE_PLL_RATIO_1152;
+		break;
+	case 576000:
+		divider = BXT_CDCLK_CD2X_DIV_SEL_1;
+		ratio = BXT_DE_PLL_RATIO_1152;
+		break;
+	case 624000:
+		divider = BXT_CDCLK_CD2X_DIV_SEL_1;
+		ratio = BXT_DE_PLL_RATIO_1248;
+		break;
+	case 0:
+		/* Incase incoming frequency is 0, only DE PLL has to be
+		 * disabled, divider/ratio need not be programmed.
+		 * Hence, initializing to 0.
+		 */
+		divider = ratio = 0;
+		break;
+	default:
+		DRM_ERROR("Unsupported cd frequency %d enable request",
+								frequency);
+		return;
+	}
+
+	current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
+	current_freq = ((current_freq / 2) + 1) * 1000;
+
+	mutex_lock(&dev_priv->rps.hw_lock);
+	/* Inform power controller of upcoming frequency change */
+	ret = sandybridge_pcode_write(dev_priv, DISPLAY_PCU_CONTROL,
+				      0x80000000);
+	mutex_unlock(&dev_priv->rps.hw_lock);
+
+	if (ret) {
+		DRM_DEBUG_KMS("pcode write failed, leaving CDCLK unchanged (%d)\n",
+			      ret);
+		return;
+	}
+
+	/* DE PLL has to be disabled when input frequency is 0 or
+	 * frequency is to be changed to 624MHz or changed from 624 MHz
+	 */
+	if (!frequency || current_freq == 624000 || frequency == 624000) {
+		I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
+		WARN(wait_for(
+			!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
+			1), "DE PLL locked\n");
+	}
+
+	if (frequency) {
+		I915_WRITE(BXT_DE_PLL_CTL, ratio);
+		I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
+		WARN(wait_for(
+			I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1),
+			"DE PLL not locked\n");
+
+		cdclk_ctl = I915_READ(CDCLK_CTL);
+		cdclk_ctl &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
+		cdclk_ctl |= divider;
+
+		/* Disable SSA Precharge when CD clock frequency < 500 MHz,
+		 * enable otherwise.
+		 */
+		cdclk_ctl &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
+		if (frequency >= 500000)
+			cdclk_ctl |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
+
+		cdclk_ctl &= ~CDCLK_FREQ_DECIMAL_MASK;
+		cdclk_ctl |= freq;
+		I915_WRITE(CDCLK_CTL, cdclk_ctl);
+
+		mutex_lock(&dev_priv->rps.hw_lock);
+		ret = sandybridge_pcode_write(dev_priv, DISPLAY_PCU_CONTROL,
+					      decimal);
+		mutex_unlock(&dev_priv->rps.hw_lock);
+
+		if (ret) {
+			DRM_DEBUG_KMS("pcode write failed. err = %d decimal = %d\n",
+				      ret, decimal);
+			return;
+		}
+
+		dev_priv->cdclk_freq = frequency;
+	} else {
+		mutex_lock(&dev_priv->rps.hw_lock);
+		ret = sandybridge_pcode_write(dev_priv, DISPLAY_PCU_CONTROL, 1);
+		mutex_unlock(&dev_priv->rps.hw_lock);
+
+		if (ret)
+			DRM_DEBUG_KMS("pcode write failed. err = %d decimal = 1\n",
+				      ret);
+	}
+}
+
+void bxt_init_cdclk(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	/* NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
+	 * or else the reset will hang because there is no PCH to respond.
+	 * Move the handshake programming to initialization sequence.
+	 * Previously was left up to BIOS.
+	 */
+	u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
+
+	temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
+	I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
+
+	/* Enable PG1 for cdclk */
+	intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
+
+	/* check if cd clock is enabled */
+	if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
+		DRM_DEBUG_KMS("Display already initialized\n");
+		return;
+	}
+
+	/* FIXME:- The initial CDCLK needs to be read from VBT.
+	 * Need to make this change after VBT has changes for BXT.
+	 */
+	bxt_select_cdclk_freq(dev, 624000);
+
+	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
+	udelay(10);
+
+	if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
+		DRM_ERROR("DBuf power enable timeout!\n");
+}
+
+void bxt_uninit_cdclk(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	bxt_ddi_phy_uninit(dev);
+
+	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
+	udelay(10);
+
+	if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
+		DRM_ERROR("DBuf power disable timeout!\n");
+
+	bxt_select_cdclk_freq(dev, 0);
+
+	intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
+}
+
 void intel_ddi_pll_init(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -1973,6 +2261,9 @@ void intel_ddi_pll_init(struct drm_device *dev)
 	if (IS_SKYLAKE(dev)) {
 		if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
 			DRM_ERROR("LCPLL1 is disabled\n");
+	} else if (IS_BROXTON(dev)) {
+		bxt_init_cdclk(dev);
+		bxt_ddi_phy_init(dev);
 	} else {
 		/*
 		 * The LCPLL register should be turned on by the BIOS. For now
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b91862e..ba2d1ae 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8284,6 +8284,75 @@ void hsw_disable_pc8(struct drm_i915_private *dev_priv)
 	intel_prepare_ddi(dev);
 }
 
+static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
+				int max_pixclk)
+{
+	/*
+	 * CDclks are supported:
+	 *   144MHz
+	 *   288MHz
+	 *   384MHz
+	 *   576MHz
+	 *   624MHz
+	 * Check to see whether we're above 90% of the lower bin and
+	 * adjust if needed.
+	 */
+
+	/* If max_pixclk is greater than the max allowed clock, return 0.
+	 * FIXME:- The max clock allowed needs to be provided by GOP/VBIOS
+	 * via a scratch pad register. Till that is enabled, use 624MHz as max.
+	 */
+	if (max_pixclk > 624000)
+		return 0;
+	else if (max_pixclk > 576000*9/10)
+		return 624000;
+	else if (max_pixclk > 384000*9/10)
+		return 576000;
+	else if (max_pixclk > 288000*9/10)
+		return 384000;
+	else if (max_pixclk > 144000*9/10)
+		return 288000;
+	else
+		return 144000;
+}
+
+static void broxton_modeset_global_pipes(struct drm_device *dev,
+					    unsigned *prepare_pipes)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_crtc *intel_crtc;
+	int max_pixclk = intel_mode_max_pixclk(dev_priv);
+	int req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
+
+	if (!req_cdclk) {
+		DRM_ERROR("CDCLK exceeds maximum allowable value\n");
+		return;
+	}
+
+	if (req_cdclk == dev_priv->cdclk_freq)
+		return;
+
+	/* disable/enable all currently active pipes while we change cdclk */
+	for_each_intel_crtc(dev, intel_crtc)
+		if (intel_crtc->base.enabled)
+			*prepare_pipes |= (1 << intel_crtc->pipe);
+}
+
+static void broxton_modeset_global_resources(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	int max_pixclk = intel_mode_max_pixclk(dev_priv);
+	int req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
+
+	if (!req_cdclk) {
+		DRM_ERROR("CDCLK exceeds maximum allowable value\n");
+		return;
+	}
+
+	if (req_cdclk != dev_priv->cdclk_freq)
+		bxt_select_cdclk_freq(dev, req_cdclk);
+}
+
 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
 				      struct intel_crtc_state *crtc_state)
 {
@@ -11239,6 +11308,9 @@ static int __intel_set_mode(struct drm_crtc *crtc,
 
 		/* may have added more to prepare_pipes than we should */
 		prepare_pipes &= ~disable_pipes;
+	} else if (IS_BROXTON(dev)) {
+		broxton_modeset_global_pipes(dev, &prepare_pipes);
+		prepare_pipes &= ~disable_pipes;
 	}
 
 	ret = __intel_set_mode_setup_plls(dev, modeset_pipes, disable_pipes);
@@ -13133,6 +13205,9 @@ static void intel_init_display(struct drm_device *dev)
 	} else if (IS_VALLEYVIEW(dev)) {
 		dev_priv->display.modeset_global_resources =
 			valleyview_modeset_global_resources;
+	} else if (IS_BROXTON(dev)) {
+		dev_priv->display.modeset_global_resources =
+			broxton_modeset_global_resources;
 	}
 
 	switch (INTEL_INFO(dev)->gen) {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index c77128c..4bc2041 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -873,6 +873,7 @@ void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
 void intel_ddi_clock_get(struct intel_encoder *encoder,
 			 struct intel_crtc_state *pipe_config);
 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
+void bxt_select_cdclk_freq(struct drm_device *dev, u32 frequency);
 
 /* intel_frontbuffer.c */
 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
@@ -1020,6 +1021,9 @@ void intel_prepare_reset(struct drm_device *dev);
 void intel_finish_reset(struct drm_device *dev);
 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
+void bxt_init_cdclk(struct drm_device *dev);
+void bxt_uninit_cdclk(struct drm_device *dev);
+void bxt_ddi_phy_init(struct drm_device *dev);
 void intel_dp_get_m_n(struct intel_crtc *crtc,
 		      struct intel_crtc_state *pipe_config);
 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
-- 
2.1.0

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[PATCH 31/49] drm/i915/bxt: add description about the BXT PHYs

[Imre Deak]

Extend the VLV/CHV DPIO (PHY) documentation with the BXT specifics.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 Documentation/DocBook/drm.tmpl  |  4 ++--
 drivers/gpu/drm/i915/i915_reg.h | 10 +++++++---
 2 files changed, 9 insertions(+), 5 deletions(-)

diff --git a/Documentation/DocBook/drm.tmpl b/Documentation/DocBook/drm.tmpl
index 7a45775..327757f 100644
--- a/Documentation/DocBook/drm.tmpl
+++ b/Documentation/DocBook/drm.tmpl
@@ -4067,7 +4067,7 @@ int num_ioctls;</synopsis>
         <title>DPIO</title>
 !Pdrivers/gpu/drm/i915/i915_reg.h DPIO
 	<table id="dpiox2">
-	  <title>Dual channel PHY (VLV/CHV)</title>
+	  <title>Dual channel PHY (VLV/CHV/BXT)</title>
 	  <tgroup cols="8">
 	    <colspec colname="c0" />
 	    <colspec colname="c1" />
@@ -4118,7 +4118,7 @@ int num_ioctls;</synopsis>
 	  </tgroup>
 	</table>
 	<table id="dpiox1">
-	  <title>Single channel PHY (CHV)</title>
+	  <title>Single channel PHY (CHV/BXT)</title>
 	  <tgroup cols="4">
 	    <colspec colname="c0" />
 	    <colspec colname="c1" />
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a3579c0..95532b4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -718,7 +718,7 @@ enum skl_disp_power_wells {
 /**
  * DOC: DPIO
  *
- * VLV and CHV have slightly peculiar display PHYs for driving DP/HDMI
+ * VLV, CHV and BXT have slightly peculiar display PHYs for driving DP/HDMI
  * ports. DPIO is the name given to such a display PHY. These PHYs
  * don't follow the standard programming model using direct MMIO
  * registers, and instead their registers must be accessed trough IOSF
@@ -773,9 +773,13 @@ enum skl_disp_power_wells {
  *
  * Note: digital port B is DDI0, digital port C is DDI1,
  * digital port D is DDI2
+ *
+ * On BXT the above mappings apply for both the dual and single channel PHY,
+ * with the difference that any of the three ports can connect to any of the
+ * three pipes. Also the single channel PHY is used for port A (DDI2/EDP).
  */
 /*
- * Dual channel PHY (VLV/CHV)
+ * Dual channel PHY (VLV/CHV/BXT)
  * ---------------------------------
  * |      CH0      |      CH1      |
  * |  CMN/PLL/REF  |  CMN/PLL/REF  |
@@ -787,7 +791,7 @@ enum skl_disp_power_wells {
  * |     DDI0      |     DDI1      | DP/HDMI ports
  * ---------------------------------
  *
- * Single channel PHY (CHV)
+ * Single channel PHY (CHV/BXT)
  * -----------------
  * |      CH0      |
  * |  CMN/PLL/REF  |
-- 
2.1.0

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[PATCH 32/49] drm/i915/bxt: Implement enable/disable for Display C9 state

[Imre Deak]

From: "A.Sunil Kamath" <sunil.kamath@intel.com>

v2: Modified as per review comments from Imre
- Mention enabling instead of allowing in the debug trace and
  remove unnecessary comments.

v3:
- Rebase to latest.
- Move DC9-related functions from intel_display.c to intel_runtime_pm.c.

v4: (imre)
- remove DC5 disabling, it's a nop at this point
- squashed in Suketu's "Assert the requirements to enter or exit DC9"
  patch
- remove check for RUNTIME_PM from assert_can_enable_dc9, it's not a
  dependency

Signed-off-by: A.Sunil Kamath <sunil.kamath@intel.com> (v3)
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h         |  5 +++
 drivers/gpu/drm/i915/intel_drv.h        |  2 +
 drivers/gpu/drm/i915/intel_runtime_pm.c | 66 +++++++++++++++++++++++++++++++++
 3 files changed, 73 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 95532b4..4c781cb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6942,6 +6942,11 @@ enum bxt_phy {
 #define   BXT_DE_PLL_PLL_ENABLE		(1 << 31)
 #define   BXT_DE_PLL_LOCK		(1 << 30)
 
+/* GEN9 DC */
+#define DC_STATE_EN			0x45504
+#define  DC_STATE_EN_UPTO_DC5		(1<<0)
+#define  DC_STATE_EN_DC9		(1<<3)
+
 /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
  * since on HSW we can't write to it using I915_WRITE. */
 #define D_COMP_HSW			(MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 4bc2041..262314b 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1024,6 +1024,8 @@ void hsw_disable_pc8(struct drm_i915_private *dev_priv);
 void bxt_init_cdclk(struct drm_device *dev);
 void bxt_uninit_cdclk(struct drm_device *dev);
 void bxt_ddi_phy_init(struct drm_device *dev);
+void bxt_enable_dc9(struct drm_i915_private *dev_priv);
+void bxt_disable_dc9(struct drm_i915_private *dev_priv);
 void intel_dp_get_m_n(struct intel_crtc *crtc,
 		      struct intel_crtc_state *pipe_config);
 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index ff5cce3..8fe2fde 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -351,6 +351,72 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv,
 	BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) |	\
 	BIT(POWER_DOMAIN_INIT))
 
+static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
+{
+	struct drm_device *dev = dev_priv->dev;
+
+	WARN(!IS_BROXTON(dev), "Platform doesn't support DC9.\n");
+	WARN((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
+		"DC9 already programmed to be enabled.\n");
+	WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
+		"DC5 still not disabled to enable DC9.\n");
+	WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on.\n");
+	WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n");
+
+	 /*
+	  * TODO: check for the following to verify the conditions to enter DC9
+	  * state are satisfied:
+	  * 1] Check relevant display engine registers to verify if mode set
+	  * disable sequence was followed.
+	  * 2] Check if display uninitialize sequence is initialized.
+	  */
+}
+
+static void assert_can_disable_dc9(struct drm_i915_private *dev_priv)
+{
+	WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n");
+	WARN(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
+		"DC9 already programmed to be disabled.\n");
+	WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
+		"DC5 still not disabled.\n");
+
+	 /*
+	  * TODO: check for the following to verify DC9 state was indeed
+	  * entered before programming to disable it:
+	  * 1] Check relevant display engine registers to verify if mode
+	  *  set disable sequence was followed.
+	  * 2] Check if display uninitialize sequence is initialized.
+	  */
+}
+
+void bxt_enable_dc9(struct drm_i915_private *dev_priv)
+{
+	uint32_t val;
+
+	assert_can_enable_dc9(dev_priv);
+
+	DRM_DEBUG_KMS("Enabling DC9\n");
+
+	val = I915_READ(DC_STATE_EN);
+	val |= DC_STATE_EN_DC9;
+	I915_WRITE(DC_STATE_EN, val);
+	POSTING_READ(DC_STATE_EN);
+}
+
+void bxt_disable_dc9(struct drm_i915_private *dev_priv)
+{
+	uint32_t val;
+
+	assert_can_disable_dc9(dev_priv);
+
+	DRM_DEBUG_KMS("Disabling DC9\n");
+
+	val = I915_READ(DC_STATE_EN);
+	val &= ~DC_STATE_EN_DC9;
+	I915_WRITE(DC_STATE_EN, val);
+	POSTING_READ(DC_STATE_EN);
+}
+
 static void skl_set_power_well(struct drm_i915_private *dev_priv,
 			struct i915_power_well *power_well, bool enable)
 {
-- 
2.1.0

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[PATCH 33/49] drm/i915/bxt: Add DC9 Trigger sequence

[Imre Deak]

From: Suketu Shah <suketu.j.shah@intel.com>

Add triggers for DC9 as per details provided in bxt_enable_dc9
and bxt_disable_dc9 implementations.

v1:
- Add SKL check in gen9_disable_dc5 as it is possible for DC5
  to remain disabled only for SKL.
- Add additional checks for whether DC5 is already disabled during
  DC5-disabling only for BXT.

v2:
- rebase to latest.
- Load CSR during DC9 disabling in the beginning before DC9 is
  disabled.
- Make gen9_disable_dc5 function non-static as it's being called by
  functions in i915_drv.c.
- Enable DC9-related functionality using a macro.

v3: (imre)
- remove BXT_ENABLE_DC9, we want DC9 always, and it's only valid on BXT
- remove DC5 disabling and CSR FW loaded check, these are nop atm
- squash in Vandana's "Do ddi_phy_init always" patch

Signed-off-by: Suketu Shah <suketu.j.shah@intel.com>
Signed-off-by: A.Sunil Kamath <sunil.kamath@intel.com> (v2)
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 48434cb6..396606a 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1002,6 +1002,18 @@ static int i915_pm_resume(struct device *dev)
 	return i915_drm_resume(drm_dev);
 }
 
+static int bxt_suspend_complete(struct drm_i915_private *dev_priv)
+{
+	struct drm_device *dev = dev_priv->dev;
+
+	/* TODO: when DC5 support is added disable DC5 here. */
+
+	bxt_uninit_cdclk(dev);
+	bxt_enable_dc9(dev_priv);
+
+	return 0;
+}
+
 static int hsw_suspend_complete(struct drm_i915_private *dev_priv)
 {
 	hsw_enable_pc8(dev_priv);
@@ -1009,6 +1021,20 @@ static int hsw_suspend_complete(struct drm_i915_private *dev_priv)
 	return 0;
 }
 
+static int bxt_resume_prepare(struct drm_i915_private *dev_priv)
+{
+	struct drm_device *dev = dev_priv->dev;
+
+	/* TODO: When CSR FW support is added make sure the FW is loaded. */
+
+	bxt_disable_dc9(dev_priv);
+	bxt_init_cdclk(dev);
+	bxt_ddi_phy_init(dev);
+	intel_prepare_ddi(dev);
+
+	return 0;
+}
+
 /*
  * Save all Gunit registers that may be lost after a D3 and a subsequent
  * S0i[R123] transition. The list of registers needing a save/restore is
@@ -1477,6 +1503,8 @@ static int intel_runtime_resume(struct device *device)
 
 	if (IS_GEN6(dev_priv))
 		intel_init_pch_refclk(dev);
+	else if (IS_BROXTON(dev))
+		ret = bxt_resume_prepare(dev_priv);
 	else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 		hsw_disable_pc8(dev_priv);
 	else if (IS_VALLEYVIEW(dev_priv))
@@ -1509,6 +1537,8 @@ static int intel_suspend_complete(struct drm_i915_private *dev_priv)
 	struct drm_device *dev = dev_priv->dev;
 	int ret;
 
+	if (IS_BROXTON(dev))
+		ret = bxt_suspend_complete(dev_priv);
 	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 		ret = hsw_suspend_complete(dev_priv);
 	else if (IS_VALLEYVIEW(dev))
-- 
2.1.0

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[PATCH 34/49] drm/i915/bxt: Restrict PORT_CLK_SEL programming below gen9

[Imre Deak]

From: Satheeshakrishna M <satheeshakrishna.m@intel.com>

PORT_CLK_SEL programming is needed only on HSW/BDW.

v2:
- don't program PORT_CLK_SEL from mst encoders either (imre)

Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c    | 4 ++--
 drivers/gpu/drm/i915/intel_dp_mst.c | 6 ++++--
 2 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 789682d..9203d81 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1559,7 +1559,7 @@ static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
 
 		I915_WRITE(DPLL_CTRL2, val);
 
-	} else {
+	} else if (INTEL_INFO(dev)->gen < 9) {
 		WARN_ON(crtc->config->ddi_pll_sel == PORT_CLK_SEL_NONE);
 		I915_WRITE(PORT_CLK_SEL(port), crtc->config->ddi_pll_sel);
 	}
@@ -1618,7 +1618,7 @@ static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
 	if (IS_SKYLAKE(dev))
 		I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
 					DPLL_CTRL2_DDI_CLK_OFF(port)));
-	else
+	else if (INTEL_INFO(dev)->gen < 9)
 		I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
 }
 
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
index be12492..76f32bb 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -158,8 +158,10 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder)
 	if (intel_dp->active_mst_links == 0) {
 		enum port port = intel_ddi_get_encoder_port(encoder);
 
-		I915_WRITE(PORT_CLK_SEL(port),
-			   intel_crtc->config->ddi_pll_sel);
+		/* FIXME: add support for SKL */
+		if (!INTEL_INFO(dev)->gen < 9)
+			I915_WRITE(PORT_CLK_SEL(port),
+				   intel_crtc->config->ddi_pll_sel);
 
 		intel_ddi_init_dp_buf_reg(&intel_dig_port->base);
 
-- 
2.1.0

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[PATCH 35/49] drm/i915/bxt: fix panel fitter setup in crtc disable/enable

[Imre Deak]

From: Jesse Barnes <jbarnes@virtuousgeek.org>

Broxton has the same panel fitter registers as Skylake.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index ba2d1ae..95ce0a8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4532,7 +4532,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
 
 	intel_ddi_enable_pipe_clock(intel_crtc);
 
-	if (IS_SKYLAKE(dev))
+	if (INTEL_INFO(dev)->gen == 9)
 		skylake_pfit_enable(intel_crtc);
 	else
 		ironlake_pfit_enable(intel_crtc);
@@ -4695,7 +4695,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
 
 	intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
 
-	if (IS_SKYLAKE(dev))
+	if (INTEL_INFO(dev)->gen == 9)
 		skylake_pfit_disable(intel_crtc);
 	else
 		ironlake_pfit_disable(intel_crtc);
@@ -8504,7 +8504,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
 
 	pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
 	if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
-		if (IS_SKYLAKE(dev))
+		if (INTEL_INFO(dev)->gen == 9)
 			skylake_get_pfit_config(crtc, pipe_config);
 		else
 			ironlake_get_pfit_config(crtc, pipe_config);
-- 
2.1.0

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[PATCH 36/49] drm/i915/bxt: Define bxt DDI PLLs and implement enable/disable sequence

[Imre Deak]

From: Satheeshakrishna M <satheeshakrishna.m@intel.com>

Plug bxt PLL code into existing shared DPLL framework.

v2: (imre)
- squash in Satheeshakrishna's "Define BXT clock registers" and
  "Add state variables for bxt clock registers" patches
- squash in Vandanas's "Change grp access to lane access for PLL"
- fix group vs. lane access in bxt_ddi_pll_get_hw_state
- add code comment why we read from lane registers while writing to
  group registers
- clean up register macros
- use BXT_PORT_PLL_* macros instead of open-coding the same
- check if BXT_PORT_PCS_DW12_LN01 matches BXT_PORT_PCS_DW12_LN23
  during hardware state readout
- add missing LANESTAGGER_STRAP_OVRD masking
- add note about missing step according to the latest BUN for
  PORT_PLL_9/lockthresh

Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> (v1)
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h  |   3 +
 drivers/gpu/drm/i915/i915_reg.h  |  76 ++++++++++++++++++
 drivers/gpu/drm/i915/intel_ddi.c | 165 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 244 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1b2a294..e4dd4bba 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -303,6 +303,9 @@ struct intel_dpll_hw_state {
 	uint32_t ctrl1;
 	/* HDMI only, 0 when used for DP */
 	uint32_t cfgcr1, cfgcr2;
+
+	/* bxt */
+	uint32_t ebb0, pll0, pll1, pll2, pll3, pll6, pll8, pcsdw12;
 };
 
 struct intel_shared_dpll_config {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4c781cb..2e72283c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1145,6 +1145,60 @@ enum bxt_phy {
 #define BXT_PHY_CTL_FAMILY(phy)		BXT_PHY(phy, _PHY_CTL_FAMILY_EDP, \
 						     _PHY_CTL_FAMILY_DDI)
 
+/* BXT PHY PLL registers */
+#define _PORT_PLL_A			0x46074
+#define _PORT_PLL_B			0x46078
+#define _PORT_PLL_C			0x4607c
+#define   PORT_PLL_ENABLE		(1 << 31)
+#define   PORT_PLL_LOCK			(1 << 30)
+#define   PORT_PLL_REF_SEL		(1 << 27)
+#define BXT_PORT_PLL_ENABLE(port)	_PORT(port, _PORT_PLL_A, _PORT_PLL_B)
+
+#define _PORT_PLL_EBB_0_A		0x162034
+#define _PORT_PLL_EBB_0_B		0x6C034
+#define _PORT_PLL_EBB_0_C		0x6C340
+#define   PORT_PLL_P1_MASK		(0x07 << 13)
+#define   PORT_PLL_P1(x)		((x)  << 13)
+#define   PORT_PLL_P2_MASK		(0x1f << 8)
+#define   PORT_PLL_P2(x)		((x)  << 8)
+#define BXT_PORT_PLL_EBB_0(port)	_PORT3(port, _PORT_PLL_EBB_0_A, \
+						_PORT_PLL_EBB_0_B,	\
+						_PORT_PLL_EBB_0_C)
+
+#define _PORT_PLL_EBB_4_A		0x162038
+#define _PORT_PLL_EBB_4_B		0x6C038
+#define _PORT_PLL_EBB_4_C		0x6C344
+#define   PORT_PLL_10BIT_CLK_ENABLE	(1 << 13)
+#define   PORT_PLL_RECALIBRATE		(1 << 14)
+#define BXT_PORT_PLL_EBB_4(port)	_PORT3(port, _PORT_PLL_EBB_4_A, \
+						_PORT_PLL_EBB_4_B,	\
+						_PORT_PLL_EBB_4_C)
+
+#define _PORT_PLL_0_A			0x162100
+#define _PORT_PLL_0_B			0x6C100
+#define _PORT_PLL_0_C			0x6C380
+/* PORT_PLL_0_A */
+#define   PORT_PLL_M2_MASK		0xFF
+/* PORT_PLL_1_A */
+#define   PORT_PLL_N_MASK		(0x0F << 8)
+#define   PORT_PLL_N(x)			((x) << 8)
+/* PORT_PLL_2_A */
+#define   PORT_PLL_M2_FRAC_MASK		0x3FFFFF
+/* PORT_PLL_3_A */
+#define   PORT_PLL_M2_FRAC_ENABLE	(1 << 16)
+/* PORT_PLL_6_A */
+#define   PORT_PLL_PROP_COEFF_MASK	0xF
+#define   PORT_PLL_INT_COEFF_MASK	(0x1F << 8)
+#define   PORT_PLL_INT_COEFF(x)		((x)  << 8)
+#define   PORT_PLL_GAIN_CTL_MASK	(0x07 << 16)
+#define   PORT_PLL_GAIN_CTL(x)		((x)  << 16)
+/* PORT_PLL_8_A */
+#define   PORT_PLL_TARGET_CNT_MASK	0x3FF
+#define _PORT_PLL_BASE(port)		_PORT3(port, _PORT_PLL_0_A,	\
+						_PORT_PLL_0_B,		\
+						_PORT_PLL_0_C)
+#define BXT_PORT_PLL(port, idx)		(_PORT_PLL_BASE(port) + (idx) * 4)
+
 /* BXT PHY common lane registers */
 #define _PORT_CL1CM_DW0_A		0x162000
 #define _PORT_CL1CM_DW0_BC		0x6C000
@@ -1214,6 +1268,28 @@ enum bxt_phy {
 #define BXT_PORT_REF_DW8(phy)		BXT_PHY(phy, _PORT_REF_DW8_A,	\
 						     _PORT_REF_DW8_BC)
 
+/* BXT PHY PCS registers */
+#define _PORT_PCS_DW12_LN01_A		0x162430
+#define _PORT_PCS_DW12_LN01_B		0x6C430
+#define _PORT_PCS_DW12_LN01_C		0x6C830
+#define _PORT_PCS_DW12_LN23_A		0x162630
+#define _PORT_PCS_DW12_LN23_B		0x6C630
+#define _PORT_PCS_DW12_LN23_C		0x6CA30
+#define _PORT_PCS_DW12_GRP_A		0x162c30
+#define _PORT_PCS_DW12_GRP_B		0x6CC30
+#define _PORT_PCS_DW12_GRP_C		0x6CE30
+#define   LANESTAGGER_STRAP_OVRD	(1 << 6)
+#define   LANE_STAGGER_MASK		0x1F
+#define BXT_PORT_PCS_DW12_LN01(port)	_PORT3(port, _PORT_PCS_DW12_LN01_A, \
+						     _PORT_PCS_DW12_LN01_B, \
+						     _PORT_PCS_DW12_LN01_C)
+#define BXT_PORT_PCS_DW12_LN23(port)	_PORT3(port, _PORT_PCS_DW12_LN23_A, \
+						     _PORT_PCS_DW12_LN23_B, \
+						     _PORT_PCS_DW12_LN23_C)
+#define BXT_PORT_PCS_DW12_GRP(port)	_PORT3(port, _PORT_PCS_DW12_GRP_A, \
+						     _PORT_PCS_DW12_GRP_B, \
+						     _PORT_PCS_DW12_GRP_C)
+
 /* BXT PHY TX registers */
 #define BXT_LANE_OFFSET(lane)           (((lane) >> 1) * 0x200 +	\
 					 ((lane) & 1) * 0x80)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 9203d81..bbc3da5 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2245,6 +2245,169 @@ void bxt_uninit_cdclk(struct drm_device *dev)
 	intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
 }
 
+static const char * const bxt_ddi_pll_names[] = {
+	"PORT PLL A",
+	"PORT PLL B",
+	"PORT PLL C",
+};
+
+static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
+				struct intel_shared_dpll *pll)
+{
+	uint32_t temp;
+	enum port port = (enum port)pll->id;	/* 1:1 port->PLL mapping */
+
+	temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
+	temp &= ~PORT_PLL_REF_SEL;
+	/* Non-SSC reference */
+	I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
+
+	/* Disable 10 bit clock */
+	temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
+	temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
+	I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
+
+	/* Write P1 & P2 */
+	temp = I915_READ(BXT_PORT_PLL_EBB_0(port));
+	temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK);
+	temp |= pll->config.hw_state.ebb0;
+	I915_WRITE(BXT_PORT_PLL_EBB_0(port), temp);
+
+	/* Write M2 integer */
+	temp = I915_READ(BXT_PORT_PLL(port, 0));
+	temp &= ~PORT_PLL_M2_MASK;
+	temp |= pll->config.hw_state.pll0;
+	I915_WRITE(BXT_PORT_PLL(port, 0), temp);
+
+	/* Write N */
+	temp = I915_READ(BXT_PORT_PLL(port, 1));
+	temp &= ~PORT_PLL_N_MASK;
+	temp |= pll->config.hw_state.pll1;
+	I915_WRITE(BXT_PORT_PLL(port, 1), temp);
+
+	/* Write M2 fraction */
+	temp = I915_READ(BXT_PORT_PLL(port, 2));
+	temp &= ~PORT_PLL_M2_FRAC_MASK;
+	temp |= pll->config.hw_state.pll2;
+	I915_WRITE(BXT_PORT_PLL(port, 2), temp);
+
+	/* Write M2 fraction enable */
+	temp = I915_READ(BXT_PORT_PLL(port, 3));
+	temp &= ~PORT_PLL_M2_FRAC_ENABLE;
+	temp |= pll->config.hw_state.pll3;
+	I915_WRITE(BXT_PORT_PLL(port, 3), temp);
+
+	/* Write coeff */
+	temp = I915_READ(BXT_PORT_PLL(port, 6));
+	temp &= ~PORT_PLL_PROP_COEFF_MASK;
+	temp &= ~PORT_PLL_INT_COEFF_MASK;
+	temp &= ~PORT_PLL_GAIN_CTL_MASK;
+	temp |= pll->config.hw_state.pll6;
+	I915_WRITE(BXT_PORT_PLL(port, 6), temp);
+
+	/* Write calibration val */
+	temp = I915_READ(BXT_PORT_PLL(port, 8));
+	temp &= ~PORT_PLL_TARGET_CNT_MASK;
+	temp |= pll->config.hw_state.pll8;
+	I915_WRITE(BXT_PORT_PLL(port, 8), temp);
+
+	/*
+	 * FIXME: program PORT_PLL_9/i_lockthresh according to the latest
+	 * specification update.
+	 */
+
+	/* Recalibrate with new settings */
+	temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
+	temp |= PORT_PLL_RECALIBRATE;
+	I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
+	/* Enable 10 bit clock */
+	temp |= PORT_PLL_10BIT_CLK_ENABLE;
+	I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
+
+	/* Enable PLL */
+	temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
+	temp |= PORT_PLL_ENABLE;
+	I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
+	POSTING_READ(BXT_PORT_PLL_ENABLE(port));
+
+	if (wait_for_atomic_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) &
+			PORT_PLL_LOCK), 200))
+		DRM_ERROR("PLL %d not locked\n", port);
+
+	/*
+	 * While we write to the group register to program all lanes at once we
+	 * can read only lane registers and we pick lanes 0/1 for that.
+	 */
+	temp = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
+	temp &= ~LANE_STAGGER_MASK;
+	temp &= ~LANESTAGGER_STRAP_OVRD;
+	temp |= pll->config.hw_state.pcsdw12;
+	I915_WRITE(BXT_PORT_PCS_DW12_GRP(port), temp);
+}
+
+static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv,
+					struct intel_shared_dpll *pll)
+{
+	enum port port = (enum port)pll->id;	/* 1:1 port->PLL mapping */
+	uint32_t temp;
+
+	temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
+	temp &= ~PORT_PLL_ENABLE;
+	I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
+	POSTING_READ(BXT_PORT_PLL_ENABLE(port));
+}
+
+static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
+					struct intel_shared_dpll *pll,
+					struct intel_dpll_hw_state *hw_state)
+{
+	enum port port = (enum port)pll->id;	/* 1:1 port->PLL mapping */
+	uint32_t val;
+
+	if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
+		return false;
+
+	val = I915_READ(BXT_PORT_PLL_ENABLE(port));
+	if (!(val & PORT_PLL_ENABLE))
+		return false;
+
+	hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port));
+	hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0));
+	hw_state->pll1 = I915_READ(BXT_PORT_PLL(port, 1));
+	hw_state->pll2 = I915_READ(BXT_PORT_PLL(port, 2));
+	hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3));
+	hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6));
+	hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8));
+	/*
+	 * While we write to the group register to program all lanes at once we
+	 * can read only lane registers. We configure all lanes the same way, so
+	 * here just read out lanes 0/1 and output a note if lanes 2/3 differ.
+	 */
+	hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
+	if (I915_READ(BXT_PORT_PCS_DW12_LN23(port) != hw_state->pcsdw12))
+		DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",
+				 hw_state->pcsdw12,
+				 I915_READ(BXT_PORT_PCS_DW12_LN23(port)));
+
+	return true;
+}
+
+static void bxt_shared_dplls_init(struct drm_i915_private *dev_priv)
+{
+	int i;
+
+	dev_priv->num_shared_dpll = 3;
+
+	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
+		dev_priv->shared_dplls[i].id = i;
+		dev_priv->shared_dplls[i].name = bxt_ddi_pll_names[i];
+		dev_priv->shared_dplls[i].disable = bxt_ddi_pll_disable;
+		dev_priv->shared_dplls[i].enable = bxt_ddi_pll_enable;
+		dev_priv->shared_dplls[i].get_hw_state =
+			bxt_ddi_pll_get_hw_state;
+	}
+}
+
 void intel_ddi_pll_init(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -2252,6 +2415,8 @@ void intel_ddi_pll_init(struct drm_device *dev)
 
 	if (IS_SKYLAKE(dev))
 		skl_shared_dplls_init(dev_priv);
+	else if (IS_BROXTON(dev))
+		bxt_shared_dplls_init(dev_priv);
 	else
 		hsw_shared_dplls_init(dev_priv);
 
-- 
2.1.0

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[PATCH 37/49] drm/i915: factor out vlv_PLL_is_optimal

[Imre Deak]

Factor out the logic to decide whether the newly calculated dividers are
better than the best found so far. Do this for clarity and to prepare
for the upcoming BXT helper needing the same.

No functional change.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 50 ++++++++++++++++++++++++++----------
 1 file changed, 36 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 95ce0a8..7feb047 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -776,6 +776,33 @@ g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 	return found;
 }
 
+/*
+ * Check if the calculated PLL configuration is more optimal compared to the
+ * best configuration and error found so far. Return the calculated error.
+ */
+static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
+			       const intel_clock_t *calculated_clock,
+			       const intel_clock_t *best_clock,
+			       unsigned int best_error_ppm,
+			       unsigned int *error_ppm)
+{
+	*error_ppm = div_u64(1000000ULL *
+				abs(target_freq - calculated_clock->dot),
+			     target_freq);
+	/*
+	 * Prefer a better P value over a better (smaller) error if the error
+	 * is small. Ensure this preference for future configurations too by
+	 * setting the error to 0.
+	 */
+	if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
+		*error_ppm = 0;
+
+		return true;
+	}
+
+	return *error_ppm + 10 < best_error_ppm;
+}
+
 static bool
 vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 		   int target, int refclk, intel_clock_t *match_clock,
@@ -800,7 +827,7 @@ vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 				clock.p = clock.p1 * clock.p2;
 				/* based on hardware requirement, prefer bigger m1,m2 values */
 				for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
-					unsigned int ppm, diff;
+					unsigned int ppm;
 
 					clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 								     refclk * clock.m1);
@@ -811,20 +838,15 @@ vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 								&clock))
 						continue;
 
-					diff = abs(clock.dot - target);
-					ppm = div_u64(1000000ULL * diff, target);
+					if (!vlv_PLL_is_optimal(dev, target,
+								&clock,
+								best_clock,
+								bestppm, &ppm))
+						continue;
 
-					if (ppm < 100 && clock.p > best_clock->p) {
-						bestppm = 0;
-						*best_clock = clock;
-						found = true;
-					}
-
-					if (bestppm >= 10 && ppm < bestppm - 10) {
-						bestppm = ppm;
-						*best_clock = clock;
-						found = true;
-					}
+					*best_clock = clock;
+					bestppm = ppm;
+					found = true;
 				}
 			}
 		}
-- 
2.1.0

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[PATCH 38/49] drm/i915: check for div-by-zero in vlv_PLL_is_optimal

[Imre Deak]

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 7feb047..5874512 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -786,6 +786,9 @@ static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 			       unsigned int best_error_ppm,
 			       unsigned int *error_ppm)
 {
+	if (WARN_ON_ONCE(!target_freq))
+		return false;
+
 	*error_ppm = div_u64(1000000ULL *
 				abs(target_freq - calculated_clock->dot),
 			     target_freq);
-- 
2.1.0

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[PATCH 39/49] drm/i915/chv: use vlv_PLL_is_optimal in chv_find_best_dpll

[Imre Deak]

Prepare chv_find_best_dpll to be used for BXT too, where we want to
consider the error between target and calculated frequency too when
choosing a better PLL configuration.

No functional change.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 26 ++++++++++++++++++++------
 1 file changed, 20 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 5874512..9ca84a2 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -786,6 +786,16 @@ static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 			       unsigned int best_error_ppm,
 			       unsigned int *error_ppm)
 {
+	/*
+	 * For CHV ignore the error and consider only the P value.
+	 * Prefer a bigger P value based on HW requirements.
+	 */
+	if (IS_CHERRYVIEW(dev)) {
+		*error_ppm = 0;
+
+		return calculated_clock->p > best_clock->p;
+	}
+
 	if (WARN_ON_ONCE(!target_freq))
 		return false;
 
@@ -864,11 +874,13 @@ chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 		   intel_clock_t *best_clock)
 {
 	struct drm_device *dev = crtc->base.dev;
+	unsigned int best_error_ppm;
 	intel_clock_t clock;
 	uint64_t m2;
 	int found = false;
 
 	memset(best_clock, 0, sizeof(*best_clock));
+	best_error_ppm = 1000000;
 
 	/*
 	 * Based on hardware doc, the n always set to 1, and m1 always
@@ -882,6 +894,7 @@ chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 		for (clock.p2 = limit->p2.p2_fast;
 				clock.p2 >= limit->p2.p2_slow;
 				clock.p2 -= clock.p2 > 10 ? 2 : 1) {
+			unsigned int error_ppm;
 
 			clock.p = clock.p1 * clock.p2;
 
@@ -898,12 +911,13 @@ chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 			if (!intel_PLL_is_valid(dev, limit, &clock))
 				continue;
 
-			/* based on hardware requirement, prefer bigger p
-			 */
-			if (clock.p > best_clock->p) {
-				*best_clock = clock;
-				found = true;
-			}
+			if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
+						best_error_ppm, &error_ppm))
+				continue;
+
+			*best_clock = clock;
+			best_error_ppm = error_ppm;
+			found = true;
 		}
 	}
 
-- 
2.1.0

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[PATCH 40/49] drm/i915/bxt: add bxt_find_best_dpll

[Imre Deak]

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 32 ++++++++++++++++++++++++++++----
 drivers/gpu/drm/i915/intel_drv.h     |  2 ++
 2 files changed, 30 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 9ca84a2..3606366 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -102,6 +102,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
 			    const struct intel_crtc_state *pipe_config);
 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
+static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors);
 
 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
 {
@@ -399,6 +400,18 @@ static const intel_limit_t intel_limits_chv = {
 	.p2 = {	.p2_slow = 1, .p2_fast = 14 },
 };
 
+static const intel_limit_t intel_limits_bxt = {
+	/* FIXME: find real dot limits */
+	.dot = { .min = 0, .max = INT_MAX },
+	.vco = { .min = 4800000, .max = 6480000 },
+	.n = { .min = 1, .max = 1 },
+	.m1 = { .min = 2, .max = 2 },
+	/* FIXME: find real m2 limits */
+	.m2 = { .min = 2 << 22, .max = 255 << 22 },
+	.p1 = { .min = 2, .max = 4 },
+	.p2 = { .p2_slow = 1, .p2_fast = 20 },
+};
+
 static void vlv_clock(int refclk, intel_clock_t *clock)
 {
 	clock->m = clock->m1 * clock->m2;
@@ -492,7 +505,9 @@ static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
 	struct drm_device *dev = crtc->base.dev;
 	const intel_limit_t *limit;
 
-	if (HAS_PCH_SPLIT(dev))
+	if (IS_BROXTON(dev))
+		limit = &intel_limits_bxt;
+	else if (HAS_PCH_SPLIT(dev))
 		limit = intel_ironlake_limit(crtc, refclk);
 	else if (IS_G4X(dev)) {
 		limit = intel_g4x_limit(crtc);
@@ -577,11 +592,11 @@ static bool intel_PLL_is_valid(struct drm_device *dev,
 	if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 		INTELPllInvalid("m1 out of range\n");
 
-	if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
+	if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
 		if (clock->m1 <= clock->m2)
 			INTELPllInvalid("m1 <= m2\n");
 
-	if (!IS_VALLEYVIEW(dev)) {
+	if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
 		if (clock->p < limit->p.min || limit->p.max < clock->p)
 			INTELPllInvalid("p out of range\n");
 		if (clock->m < limit->m.min || limit->m.max < clock->m)
@@ -924,6 +939,15 @@ chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 	return found;
 }
 
+bool bxt_find_best_dpll(struct intel_crtc *crtc, int target_clock,
+			intel_clock_t *best_clock)
+{
+	int refclk = i9xx_get_refclk(crtc, 0);
+
+	return chv_find_best_dpll(intel_limit(crtc, refclk), crtc, target_clock,
+				  refclk, NULL, best_clock);
+}
+
 bool intel_crtc_active(struct drm_crtc *crtc)
 {
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
@@ -5913,7 +5937,7 @@ static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int refclk;
 
-	if (IS_VALLEYVIEW(dev)) {
+	if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
 		refclk = 100000;
 	} else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
 	    intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 262314b..56a5cc9 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1033,6 +1033,8 @@ int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
 void
 ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
 				int dotclock);
+bool bxt_find_best_dpll(struct intel_crtc *crtc, int target_clock,
+			intel_clock_t *best_clock);
 bool intel_crtc_active(struct drm_crtc *crtc);
 void hsw_enable_ips(struct intel_crtc *crtc);
 void hsw_disable_ips(struct intel_crtc *crtc);
-- 
2.1.0

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[PATCH 41/49] drm/i915/bxt: BXT clock divider calculation

[Imre Deak]

From: Satheeshakrishna M <satheeshakrishna.m@intel.com>

Calculate and cache clock parameters. Follow bspec algorithm for HDMI.
Use precalculated values for DisplayPort linkrates.

v2: (imre)
- rebase against upstream crtc_state change
- use the existing CHV based helper instead of handrolling the same

Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> (v1)
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 129 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 129 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index bbc3da5..fa4f8f4 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1204,6 +1204,132 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
 	return true;
 }
 
+/* bxt clock parameters */
+struct bxt_clk_div {
+	uint32_t p1;
+	uint32_t p2;
+	uint32_t m2_int;
+	uint32_t m2_frac;
+	bool m2_frac_en;
+	uint32_t n;
+	uint32_t prop_coef;
+	uint32_t int_coef;
+	uint32_t gain_ctl;
+	uint32_t targ_cnt;
+	uint32_t lanestagger;
+};
+
+/* pre-calculated values for DP linkrates */
+static struct bxt_clk_div bxt_dp_clk_val[7] = {
+	/* 162 */ {4, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
+	/* 270 */ {4, 1, 27,       0, 0, 1, 3,  8, 1, 9, 0xd},
+	/* 540 */ {2, 1, 27,       0, 0, 1, 3,  8, 1, 9, 0x18},
+	/* 216 */ {3, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
+	/* 243 */ {4, 1, 24, 1258291, 1, 1, 5, 11, 2, 9, 0xd},
+	/* 324 */ {4, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
+	/* 432 */ {3, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0x18}
+};
+
+static bool
+bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
+		   struct intel_crtc_state *crtc_state,
+		   struct intel_encoder *intel_encoder,
+		   int clock)
+{
+	struct intel_shared_dpll *pll;
+	struct bxt_clk_div clk_div = {0};
+
+	if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
+		intel_clock_t best_clock;
+
+		/* Calculate HDMI div */
+		/*
+		 * FIXME: tie the following calculation into
+		 * i9xx_crtc_compute_clock
+		 */
+		if (!bxt_find_best_dpll(intel_crtc, clock, &best_clock)) {
+			DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n",
+					 clock, pipe_name(intel_crtc->pipe));
+			return false;
+		}
+
+		clk_div.p1 = best_clock.p1;
+		clk_div.p2 = best_clock.p2;
+		WARN_ON(best_clock.m1 != 2);
+		clk_div.n = best_clock.n;
+		clk_div.m2_int = best_clock.m2 >> 22;
+		clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1);
+		clk_div.m2_frac_en = clk_div.m2_frac != 0;
+
+		/* FIXME: set coef, gain, targcnt based on freq band */
+		clk_div.prop_coef = 5;
+		clk_div.int_coef = 11;
+		clk_div.gain_ctl = 2;
+		clk_div.targ_cnt = 9;
+		if (clock > 270000)
+			clk_div.lanestagger = 0x18;
+		else if (clock > 135000)
+			clk_div.lanestagger = 0x0d;
+		else if (clock > 67000)
+			clk_div.lanestagger = 0x07;
+		else if (clock > 33000)
+			clk_div.lanestagger = 0x04;
+		else
+			clk_div.lanestagger = 0x02;
+	} else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
+			intel_encoder->type == INTEL_OUTPUT_EDP) {
+		struct drm_encoder *encoder = &intel_encoder->base;
+		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+		switch (intel_dp->link_bw) {
+		case DP_LINK_BW_1_62:
+			clk_div = bxt_dp_clk_val[0];
+			break;
+		case DP_LINK_BW_2_7:
+			clk_div = bxt_dp_clk_val[1];
+			break;
+		case DP_LINK_BW_5_4:
+			clk_div = bxt_dp_clk_val[2];
+			break;
+		default:
+			clk_div = bxt_dp_clk_val[0];
+			DRM_ERROR("Unknown link rate\n");
+		}
+	}
+
+	crtc_state->dpll_hw_state.ebb0 =
+		PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2);
+	crtc_state->dpll_hw_state.pll0 = clk_div.m2_int;
+	crtc_state->dpll_hw_state.pll1 = PORT_PLL_N(clk_div.n);
+	crtc_state->dpll_hw_state.pll2 = clk_div.m2_frac;
+
+	if (clk_div.m2_frac_en)
+		crtc_state->dpll_hw_state.pll3 =
+			PORT_PLL_M2_FRAC_ENABLE;
+
+	crtc_state->dpll_hw_state.pll6 =
+		clk_div.prop_coef | PORT_PLL_INT_COEFF(clk_div.int_coef);
+	crtc_state->dpll_hw_state.pll6 |=
+		PORT_PLL_GAIN_CTL(clk_div.gain_ctl);
+
+	crtc_state->dpll_hw_state.pll8 = clk_div.targ_cnt;
+
+	crtc_state->dpll_hw_state.pcsdw12 =
+		LANESTAGGER_STRAP_OVRD | clk_div.lanestagger;
+
+	pll = intel_get_shared_dpll(intel_crtc, crtc_state);
+	if (pll == NULL) {
+		DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
+			pipe_name(intel_crtc->pipe));
+		return false;
+	}
+
+	/* shared DPLL id 0 is DPLL A */
+	crtc_state->ddi_pll_sel = pll->id;
+
+	return true;
+}
+
 /*
  * Tries to find a *shared* PLL for the CRTC and store it in
  * intel_crtc->ddi_pll_sel.
@@ -1222,6 +1348,9 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
 	if (IS_SKYLAKE(dev))
 		return skl_ddi_pll_select(intel_crtc, crtc_state,
 					  intel_encoder, clock);
+	else if (IS_BROXTON(dev))
+		return bxt_ddi_pll_select(intel_crtc, crtc_state,
+					  intel_encoder, clock);
 	else
 		return hsw_ddi_pll_select(intel_crtc, crtc_state,
 					  intel_encoder, clock);
-- 
2.1.0

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[PATCH 42/49] drm/i915/bxt: Assign PLL for pipe

[Imre Deak]

From: Satheeshakrishna M <satheeshakrishna.m@intel.com>

Assign PLL for pipe (dependent on port attached to the pipe)

v2:
- fix incorrect encoder vs. new_encoder check for crtc (imre)

v3:
- warn and return error if no encoder is attached (imre)

Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> (v2)
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c     | 21 ------------------
 drivers/gpu/drm/i915/intel_display.c | 41 ++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_drv.h     |  1 +
 3 files changed, 42 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index fa4f8f4..0a5d71e 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -491,27 +491,6 @@ intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
 	return ret;
 }
 
-static struct intel_encoder *
-intel_ddi_get_crtc_new_encoder(struct intel_crtc *crtc)
-{
-	struct drm_device *dev = crtc->base.dev;
-	struct intel_encoder *intel_encoder, *ret = NULL;
-	int num_encoders = 0;
-
-	for_each_intel_encoder(dev, intel_encoder) {
-		if (intel_encoder->new_crtc == crtc) {
-			ret = intel_encoder;
-			num_encoders++;
-		}
-	}
-
-	WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
-	     pipe_name(crtc->pipe));
-
-	BUG_ON(ret == NULL);
-	return ret;
-}
-
 #define LC_FREQ 2700
 #define LC_FREQ_2K U64_C(LC_FREQ * 2000)
 
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3606366..411bf50 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4037,6 +4037,27 @@ void intel_put_shared_dpll(struct intel_crtc *crtc)
 	crtc->config->shared_dpll = DPLL_ID_PRIVATE;
 }
 
+struct intel_encoder *
+intel_ddi_get_crtc_new_encoder(struct intel_crtc *crtc)
+{
+	struct drm_device *dev = crtc->base.dev;
+	struct intel_encoder *intel_encoder, *ret = NULL;
+	int num_encoders = 0;
+
+	for_each_intel_encoder(dev, intel_encoder) {
+		if (intel_encoder->new_crtc == crtc) {
+			ret = intel_encoder;
+			num_encoders++;
+		}
+	}
+
+	WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
+	     pipe_name(crtc->pipe));
+
+	BUG_ON(ret == NULL);
+	return ret;
+}
+
 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
 						struct intel_crtc_state *crtc_state)
 {
@@ -4057,6 +4078,26 @@ struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
 		goto found;
 	}
 
+	if (IS_BROXTON(dev_priv->dev)) {
+		/* PLL is attached to port in bxt */
+		struct intel_encoder *encoder;
+		struct intel_digital_port *intel_dig_port;
+
+		encoder = intel_ddi_get_crtc_new_encoder(crtc);
+		if (WARN_ON(!encoder))
+			return NULL;
+
+		intel_dig_port = enc_to_dig_port(&encoder->base);
+		/* 1:1 mapping between ports and PLLs */
+		i = (enum intel_dpll_id)intel_dig_port->port;
+		pll = &dev_priv->shared_dplls[i];
+		DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
+			crtc->base.base.id, pll->name);
+		WARN_ON(pll->new_config->crtc_mask);
+
+		goto found;
+	}
+
 	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
 		pll = &dev_priv->shared_dplls[i];
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 56a5cc9..097fb85 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -991,6 +991,7 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv,
 			bool state);
 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
+struct intel_encoder *intel_ddi_get_crtc_new_encoder(struct intel_crtc *crtc);
 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
 						struct intel_crtc_state *state);
 void intel_put_shared_dpll(struct intel_crtc *crtc);
-- 
2.1.0

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[PATCH 43/49] drm/i915/bxt: Determine PLL attached to pipe

[Imre Deak]

From: Satheeshakrishna M <satheeshakrishna.m@intel.com>

Determine PLL attached to pipe (which is same as DDI PLL)

v2:
- rebased on upstream s/crtc_config/crtc_state/ (imre)

Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> (v1)
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 411bf50..c060496 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8468,6 +8468,28 @@ static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
 	return 0;
 }
 
+static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
+				enum port port,
+				struct intel_crtc_state *pipe_config)
+{
+	switch (port) {
+	case PORT_A:
+		pipe_config->ddi_pll_sel = SKL_DPLL0;
+		pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
+		break;
+	case PORT_B:
+		pipe_config->ddi_pll_sel = SKL_DPLL1;
+		pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
+		break;
+	case PORT_C:
+		pipe_config->ddi_pll_sel = SKL_DPLL2;
+		pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
+		break;
+	default:
+		DRM_ERROR("Incorrect port type\n");
+	}
+}
+
 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
 				enum port port,
 				struct intel_crtc_state *pipe_config)
@@ -8530,6 +8552,8 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
 
 	if (IS_SKYLAKE(dev))
 		skylake_get_ddi_pll(dev_priv, port, pipe_config);
+	else if (IS_BROXTON(dev))
+		bxt_get_ddi_pll(dev_priv, port, pipe_config);
 	else
 		haswell_get_ddi_pll(dev_priv, port, pipe_config);
 
-- 
2.1.0

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[PATCH 44/49] drm/i915/bxt: Determine programmed frequency

[Imre Deak]

From: Satheeshakrishna M <satheeshakrishna.m@intel.com>

Add placeholder function for calculating programmed pixel clock.
Note: Formula to back calculate link clock from dividers not
available currently.

v2:
- rebased on upstream s/crtc_config/crtc_state/ change (imre)

Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> (v1)
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 30 +++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_dp.c  |  2 ++
 2 files changed, 31 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 0a5d71e..ff62054 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -851,6 +851,32 @@ static void hsw_ddi_clock_get(struct intel_encoder *encoder,
 		pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
 }
 
+static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
+				enum intel_dpll_id dpll)
+{
+	/* FIXME formula not available in bspec */
+	return 0;
+}
+
+static void bxt_ddi_clock_get(struct intel_encoder *encoder,
+				struct intel_crtc_state *pipe_config)
+{
+	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
+	enum port port = intel_ddi_get_encoder_port(encoder);
+	uint32_t dpll = port;
+
+	pipe_config->port_clock =
+		bxt_calc_pll_link(dev_priv, dpll);
+
+	if (pipe_config->has_dp_encoder)
+		pipe_config->base.adjusted_mode.crtc_clock =
+			intel_dotclock_calculate(pipe_config->port_clock,
+							&pipe_config->dp_m_n);
+	else
+		pipe_config->base.adjusted_mode.crtc_clock =
+							pipe_config->port_clock;
+}
+
 void intel_ddi_clock_get(struct intel_encoder *encoder,
 			 struct intel_crtc_state *pipe_config)
 {
@@ -858,8 +884,10 @@ void intel_ddi_clock_get(struct intel_encoder *encoder,
 
 	if (INTEL_INFO(dev)->gen <= 8)
 		hsw_ddi_clock_get(encoder, pipe_config);
-	else
+	else if (IS_SKYLAKE(dev))
 		skl_ddi_clock_get(encoder, pipe_config);
+	else if (IS_BROXTON(dev))
+		bxt_ddi_clock_get(encoder, pipe_config);
 }
 
 static void
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index ca60060..4bfbeed 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1416,6 +1416,8 @@ found:
 
 	if (IS_SKYLAKE(dev) && is_edp(intel_dp))
 		skl_edp_set_pll_config(pipe_config, supported_rates[clock]);
+	else if (IS_BROXTON(dev))
+		/* handled in ddi */;
 	else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 		hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
 	else
-- 
2.1.0

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[PATCH 45/49] drm/i915: suppress false PLL state warnings on non-GMCH platforms

[Imre Deak]

The checks for PLL enabled state on CPU ports are valid only on GMCH
platforms but atm we'd also call them on non-PCH-split/non-GMCH
platforms like BXT, triggering false warnings. Until the proper check is
implented for these platforms simply disable the check.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index c060496..ff26752 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2099,7 +2099,7 @@ static void intel_enable_pipe(struct intel_crtc *crtc)
 	 * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
 	 * need the check.
 	 */
-	if (!HAS_PCH_SPLIT(dev_priv->dev))
+	if (HAS_GMCH_DISPLAY(dev_priv->dev))
 		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
 			assert_dsi_pll_enabled(dev_priv);
 		else
@@ -4376,7 +4376,7 @@ static void intel_crtc_load_lut(struct drm_crtc *crtc)
 	if (!crtc->state->enable || !intel_crtc->active)
 		return;
 
-	if (!HAS_PCH_SPLIT(dev_priv->dev)) {
+	if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
 		if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
 			assert_dsi_pll_enabled(dev_priv);
 		else
-- 
2.1.0

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[PATCH 46/49] drm/i915: Iterate through the initialized DDIs to prepare their buffers

[Imre Deak]

From: Damien Lespiau <damien.lespiau@intel.com>

Not every DDIs is necessarily connected can be strapped off and, in the
future, we'll have platforms with a different number of default DDI
ports. So, let's only call intel_prepare_ddi_buffers() on DDI ports that
are actually detected.

We also use the opportunity to give a struct intel_digital_port to
intel_prepare_ddi_buffers() as we'll need it in a following patch to
query if the port supports HMDI or not.

On my HSW machine this removes the initialization of a couple of
(unused) DDIs.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h  |  4 ++++
 drivers/gpu/drm/i915/intel_ddi.c | 16 ++++++++++++----
 2 files changed, 16 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e4dd4bba..e6402b0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -251,6 +251,10 @@ enum hpd_pin {
 			    &dev->mode_config.connector_list,	\
 			    base.head)
 
+#define for_each_digital_port(dev, digital_port)		\
+	list_for_each_entry(digital_port,			\
+			    &dev->mode_config.encoder_list,	\
+			    base.base.head)
 
 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
 	list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index ff62054..5c18018 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -189,10 +189,12 @@ enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
  * in either FDI or DP modes only, as HDMI connections will work with both
  * of those
  */
-static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port)
+static void intel_prepare_ddi_buffers(struct drm_device *dev,
+				      struct intel_digital_port *intel_dig_port)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 reg;
+	int port = intel_dig_port->port;
 	int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry,
 	    size;
 	int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
@@ -307,13 +309,19 @@ static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port)
  */
 void intel_prepare_ddi(struct drm_device *dev)
 {
-	int port;
+	struct intel_digital_port *intel_dig_port;
+	bool visited[I915_MAX_PORTS] = { 0, };
 
 	if (!HAS_DDI(dev))
 		return;
 
-	for (port = PORT_A; port <= PORT_E; port++)
-		intel_prepare_ddi_buffers(dev, port);
+	for_each_digital_port(dev, intel_dig_port) {
+		if (visited[intel_dig_port->port])
+			continue;
+
+		intel_prepare_ddi_buffers(dev, intel_dig_port);
+		visited[intel_dig_port->port] = true;
+	}
 }
 
 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
-- 
2.1.0

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[PATCH 47/49] drm/i915: Don't write the HDMI buffer translation entry when not needed

[Imre Deak]

From: Damien Lespiau <damien.lespiau@intel.com>

We don't actually need to write the HDMI entry on DDIs that have no
chance to be used as HDMI ports.

While this patch shouldn't change the current behaviour, it makes
further enabling work easier as we'll have an eDP table filling the full
10 entries.

v2: Rely on the logic from intel_ddi_init() to figure out if the DDI port
    supports HDMI or not (Paulo).

Suggested-by: Satheeshakrishna M <satheeshakrishna.m@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 5c18018..5aa4dab 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -182,6 +182,12 @@ enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
 	}
 }
 
+static bool
+intel_dig_port_supports_hdmi(const struct intel_digital_port *intel_dig_port)
+{
+	return intel_dig_port->hdmi.hdmi_reg;
+}
+
 /*
  * Starting with Haswell, DDI port buffers must be programmed with correct
  * values in advance. The buffer values are different for FDI and DP modes,
@@ -292,6 +298,9 @@ static void intel_prepare_ddi_buffers(struct drm_device *dev,
 		reg += 4;
 	}
 
+	if (!intel_dig_port_supports_hdmi(intel_dig_port))
+		return;
+
 	/* Choose a good default if VBT is badly populated */
 	if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
 	    hdmi_level >= n_hdmi_entries)
-- 
2.1.0

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[PATCH 48/49] drm/i915/bxt: VSwing programming sequence

[Imre Deak]

From: Vandana Kannan <vandana.kannan@intel.com>

VSwing programming sequence as specified in the updated BXT BSpec

v2: Satheesh's review comments addressed.
- clear value before setting into registers
- move print statement to bxt function
Other changes
- since signal level will not be set into DDI_BUF_CTL, the value need
  not be returned to intel_dp_set_signal_levels(). Making the bxt
  specific function to return void and setting signal_levels = 0 for
  bxt inside intel_dp_set_signal_levels()
- instead of signal levels, printing vswing level and pre-emphasis
  level
- in case none of the pre-emphasis levels or vswing levels are set,
  setting default of 400mV + 0dB

v3: Satheesh's review comments
- Check for mask before printing signal_levels.
- Removing redundant register writes
- Call intel_prepare_ddi_buffers only for HAS_PCH_SPLIT
- Making register write part generic as it will be required for HDMI as
  well.

Re-structure the code to include an array for vswing related values, set
signal levels

v4: Satheesh's review comments
- Rebase over latest renaming patches
- use hsw_signal_levels for HAS_DDI
Other changes
- Modified vswing_sequence() func definition
- Rebased on top of register macro definitions

v5: Satheesh's review comments
- Check ddi translation table size

v6: Imre's review comments
- removed comments in vswing sequence
- added vswing, pre-emphasis prints in intel_dp_set_signal_levels
- added comment explaining use of DP vswing values for eDP
- initialize n_entries and ddi_transaltion table based on encoder type
- create bxt_ddi_buf_trans structure and use decimal values
- adding a flag in bxt buffer translation table to indicate def entry

v7: (imre)
- squash in Vandana's "VSwing register definition",
  "HDMI VSwing programming", "Re-enable vswing programming",
  "Fix vswing sequence" patches
- use BXT_PORT_* regs directly instead of via a temp var
- simplify BXT_PORT_* macro definitions
- add code comment why we read lane while write group registers
- fix readout of DP_TRAIN_PRE_EMPHASIS in debug message

Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> (v6)
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  |  61 ++++++++++++++++++++
 drivers/gpu/drm/i915/intel_ddi.c | 120 ++++++++++++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_dp.c  |  64 ++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_drv.h |   2 +
 4 files changed, 244 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2e72283c..545b7cf 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1269,6 +1269,21 @@ enum bxt_phy {
 						     _PORT_REF_DW8_BC)
 
 /* BXT PHY PCS registers */
+#define _PORT_PCS_DW10_LN01_A		0x162428
+#define _PORT_PCS_DW10_LN01_B		0x6C428
+#define _PORT_PCS_DW10_LN01_C		0x6C828
+#define _PORT_PCS_DW10_GRP_A		0x162C28
+#define _PORT_PCS_DW10_GRP_B		0x6CC28
+#define _PORT_PCS_DW10_GRP_C		0x6CE28
+#define BXT_PORT_PCS_DW10_LN01(port)	_PORT3(port, _PORT_PCS_DW10_LN01_A, \
+						     _PORT_PCS_DW10_LN01_B, \
+						     _PORT_PCS_DW10_LN01_C)
+#define BXT_PORT_PCS_DW10_GRP(port)	_PORT3(port, _PORT_PCS_DW10_GRP_A,  \
+						     _PORT_PCS_DW10_GRP_B,  \
+						     _PORT_PCS_DW10_GRP_C)
+#define   TX2_SWING_CALC_INIT		(1 << 31)
+#define   TX1_SWING_CALC_INIT		(1 << 30)
+
 #define _PORT_PCS_DW12_LN01_A		0x162430
 #define _PORT_PCS_DW12_LN01_B		0x6C430
 #define _PORT_PCS_DW12_LN01_C		0x6C830
@@ -1294,6 +1309,52 @@ enum bxt_phy {
 #define BXT_LANE_OFFSET(lane)           (((lane) >> 1) * 0x200 +	\
 					 ((lane) & 1) * 0x80)
 
+#define _PORT_TX_DW2_LN0_A		0x162508
+#define _PORT_TX_DW2_LN0_B		0x6C508
+#define _PORT_TX_DW2_LN0_C		0x6C908
+#define _PORT_TX_DW2_GRP_A		0x162D08
+#define _PORT_TX_DW2_GRP_B		0x6CD08
+#define _PORT_TX_DW2_GRP_C		0x6CF08
+#define BXT_PORT_TX_DW2_GRP(port)	_PORT3(port, _PORT_TX_DW2_GRP_A,  \
+						     _PORT_TX_DW2_GRP_B,  \
+						     _PORT_TX_DW2_GRP_C)
+#define BXT_PORT_TX_DW2_LN0(port)	_PORT3(port, _PORT_TX_DW2_LN0_A,  \
+						     _PORT_TX_DW2_LN0_B,  \
+						     _PORT_TX_DW2_LN0_C)
+#define   MARGIN_000_SHIFT		16
+#define   MARGIN_000			(0xFF << MARGIN_000_SHIFT)
+#define   UNIQ_TRANS_SCALE_SHIFT	8
+#define   UNIQ_TRANS_SCALE		(0xFF << UNIQ_TRANS_SCALE_SHIFT)
+
+#define _PORT_TX_DW3_LN0_A		0x16250C
+#define _PORT_TX_DW3_LN0_B		0x6C50C
+#define _PORT_TX_DW3_LN0_C		0x6C90C
+#define _PORT_TX_DW3_GRP_A		0x162D0C
+#define _PORT_TX_DW3_GRP_B		0x6CD0C
+#define _PORT_TX_DW3_GRP_C		0x6CF0C
+#define BXT_PORT_TX_DW3_GRP(port)	_PORT3(port, _PORT_TX_DW3_GRP_A,  \
+						     _PORT_TX_DW3_GRP_B,  \
+						     _PORT_TX_DW3_GRP_C)
+#define BXT_PORT_TX_DW3_LN0(port)	_PORT3(port, _PORT_TX_DW3_LN0_A,  \
+						     _PORT_TX_DW3_LN0_B,  \
+						     _PORT_TX_DW3_LN0_C)
+#define   UNIQE_TRANGE_EN_METHOD	(1 << 27)
+
+#define _PORT_TX_DW4_LN0_A		0x162510
+#define _PORT_TX_DW4_LN0_B		0x6C510
+#define _PORT_TX_DW4_LN0_C		0x6C910
+#define _PORT_TX_DW4_GRP_A		0x162D10
+#define _PORT_TX_DW4_GRP_B		0x6CD10
+#define _PORT_TX_DW4_GRP_C		0x6CF10
+#define BXT_PORT_TX_DW4_LN0(port)	_PORT3(port, _PORT_TX_DW4_LN0_A,  \
+						     _PORT_TX_DW4_LN0_B,  \
+						     _PORT_TX_DW4_LN0_C)
+#define BXT_PORT_TX_DW4_GRP(port)	_PORT3(port, _PORT_TX_DW4_GRP_A,  \
+						     _PORT_TX_DW4_GRP_B,  \
+						     _PORT_TX_DW4_GRP_C)
+#define   DEEMPH_SHIFT			24
+#define   DE_EMPHASIS			(0xFF << DEEMPH_SHIFT)
+
 #define _PORT_TX_DW14_LN0_A		0x162538
 #define _PORT_TX_DW14_LN0_B		0x6C538
 #define _PORT_TX_DW14_LN0_C		0x6C938
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 5aa4dab..799f9fc 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -159,6 +159,48 @@ static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
 	{ 0x00004014, 0x00000087 },	/* 0:	800	1000	2   */
 };
 
+struct bxt_ddi_buf_trans {
+	u32 margin;	/* swing value */
+	u32 scale;	/* scale value */
+	u32 enable;	/* scale enable */
+	u32 deemphasis;
+	bool default_index; /* true if the entry represents default value */
+};
+
+/* BSpec does not define separate vswing/pre-emphasis values for eDP.
+ * Using DP values for eDP as well.
+ */
+static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
+					/* Idx	NT mV diff	db  */
+	{ 52,  0,    0, 128, true  },	/* 0:	400		0   */
+	{ 78,  0,    0, 85,  false },	/* 1:	400		3.5 */
+	{ 104, 0,    0, 64,  false },	/* 2:	400		6   */
+	{ 154, 0,    0, 43,  false },	/* 3:	400		9.5 */
+	{ 77,  0,    0, 128, false },	/* 4:	600		0   */
+	{ 116, 0,    0, 85,  false },	/* 5:	600		3.5 */
+	{ 154, 0,    0, 64,  false },	/* 6:	600		6   */
+	{ 102, 0,    0, 128, false },	/* 7:	800		0   */
+	{ 154, 0,    0, 85,  false },	/* 8:	800		3.5 */
+	{ 154, 0x9A, 1, 128, false },  /* 9:	1200		0   */
+};
+
+/* BSpec has 2 recommended values - entries 0 and 8.
+ * Using the entry with higher vswing.
+ */
+static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
+					/* Idx	NT mV diff	db  */
+	{ 52,  0,    0, 128, false },	/* 0:	400		0   */
+	{ 52,  0,    0, 85,  false },	/* 1:	400		3.5 */
+	{ 52,  0,    0, 64,  false },	/* 2:	400		6   */
+	{ 42,  0,    0, 43,  false },	/* 3:	400		9.5 */
+	{ 77,  0,    0, 128, false },	/* 4:	600		0   */
+	{ 77,  0,    0, 85,  false },	/* 5:	600		3.5 */
+	{ 77,  0,    0, 64,  false },	/* 6:	600		6   */
+	{ 102, 0,    0, 128, false },	/* 7:	800		0   */
+	{ 102, 0,    0, 85,  false },	/* 8:	800		3.5 */
+	{ 154, 0x9A, 1, 128, true },	/* 9:	1200		0   */
+};
+
 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
 {
 	struct drm_encoder *encoder = &intel_encoder->base;
@@ -210,7 +252,15 @@ static void intel_prepare_ddi_buffers(struct drm_device *dev,
 	const struct ddi_buf_trans *ddi_translations_hdmi;
 	const struct ddi_buf_trans *ddi_translations;
 
-	if (IS_SKYLAKE(dev)) {
+	if (IS_BROXTON(dev)) {
+		if (!intel_dig_port_supports_hdmi(intel_dig_port))
+			return;
+
+		/* Vswing programming for HDMI */
+		bxt_ddi_vswing_sequence(dev, hdmi_level, port,
+					INTEL_OUTPUT_HDMI);
+		return;
+	} else if (IS_SKYLAKE(dev)) {
 		ddi_translations_fdi = NULL;
 		ddi_translations_dp = skl_ddi_translations_dp;
 		n_dp_entries = ARRAY_SIZE(skl_ddi_translations_dp);
@@ -1666,6 +1716,67 @@ void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
 			   TRANS_CLK_SEL_DISABLED);
 }
 
+void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
+			     enum port port, int type)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	const struct bxt_ddi_buf_trans *ddi_translations;
+	u32 n_entries, i;
+	uint32_t val;
+
+	if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
+		n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
+		ddi_translations = bxt_ddi_translations_dp;
+	} else if (type == INTEL_OUTPUT_HDMI) {
+		n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
+		ddi_translations = bxt_ddi_translations_hdmi;
+	} else {
+		DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
+				type);
+		return;
+	}
+
+	/* Check if default value has to be used */
+	if (level >= n_entries ||
+	    (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) {
+		for (i = 0; i < n_entries; i++) {
+			if (ddi_translations[i].default_index) {
+				level = i;
+				break;
+			}
+		}
+	}
+
+	/*
+	 * While we write to the group register to program all lanes at once we
+	 * can read only lane registers and we pick lanes 0/1 for that.
+	 */
+	val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
+	val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
+	I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
+
+	val = I915_READ(BXT_PORT_TX_DW2_LN0(port));
+	val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
+	val |= ddi_translations[level].margin << MARGIN_000_SHIFT |
+	       ddi_translations[level].scale << UNIQ_TRANS_SCALE_SHIFT;
+	I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
+
+	val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
+	val &= ~UNIQE_TRANGE_EN_METHOD;
+	if (ddi_translations[level].enable)
+		val |= UNIQE_TRANGE_EN_METHOD;
+	I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
+
+	val = I915_READ(BXT_PORT_TX_DW4_LN0(port));
+	val &= ~DE_EMPHASIS;
+	val |= ddi_translations[level].deemphasis << DEEMPH_SHIFT;
+	I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val);
+
+	val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
+	val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT;
+	I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
+}
+
 static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
 {
 	struct drm_encoder *encoder = &intel_encoder->base;
@@ -1674,6 +1785,7 @@ static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
 	struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
 	enum port port = intel_ddi_get_encoder_port(intel_encoder);
 	int type = intel_encoder->type;
+	int hdmi_level;
 
 	if (type == INTEL_OUTPUT_EDP) {
 		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
@@ -1730,6 +1842,12 @@ static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
 	} else if (type == INTEL_OUTPUT_HDMI) {
 		struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 
+		if (IS_BROXTON(dev)) {
+			hdmi_level = dev_priv->vbt.
+				ddi_port_info[port].hdmi_level_shift;
+			bxt_ddi_vswing_sequence(dev, hdmi_level, port,
+					INTEL_OUTPUT_HDMI);
+		}
 		intel_hdmi->set_infoframes(encoder,
 					   crtc->config->has_hdmi_sink,
 					   &crtc->config->base.adjusted_mode);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 4bfbeed..1cb6eb0 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3354,6 +3354,55 @@ intel_hsw_signal_levels(uint8_t train_set)
 	}
 }
 
+static void intel_bxt_signal_levels(struct intel_dp *intel_dp)
+{
+	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
+	enum port port = dport->port;
+	struct drm_device *dev = dport->base.base.dev;
+	struct intel_encoder *encoder = &dport->base;
+	uint8_t train_set = intel_dp->train_set[0];
+	uint32_t level = 0;
+
+	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
+					 DP_TRAIN_PRE_EMPHASIS_MASK);
+	switch (signal_levels) {
+	default:
+		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emph level\n");
+	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
+		level = 0;
+		break;
+	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
+		level = 1;
+		break;
+	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
+		level = 2;
+		break;
+	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
+		level = 3;
+		break;
+	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
+		level = 4;
+		break;
+	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
+		level = 5;
+		break;
+	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
+		level = 6;
+		break;
+	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
+		level = 7;
+		break;
+	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
+		level = 8;
+		break;
+	case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
+		level = 9;
+		break;
+	}
+
+	bxt_ddi_vswing_sequence(dev, level, port, encoder->type);
+}
+
 /* Properly updates "DP" with the correct signal levels. */
 static void
 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
@@ -3364,7 +3413,11 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
 	uint32_t signal_levels, mask;
 	uint8_t train_set = intel_dp->train_set[0];
 
-	if (IS_HASWELL(dev) || IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
+	if (IS_BROXTON(dev)) {
+		signal_levels = 0;
+		intel_bxt_signal_levels(intel_dp);
+		mask = 0;
+	} else if (HAS_DDI(dev)) {
 		signal_levels = intel_hsw_signal_levels(train_set);
 		mask = DDI_BUF_EMP_MASK;
 	} else if (IS_CHERRYVIEW(dev)) {
@@ -3384,7 +3437,14 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
 		mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
 	}
 
-	DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
+	if (mask)
+		DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
+
+	DRM_DEBUG_KMS("Using vswing level %d\n",
+		train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
+	DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
+		(train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
+			DP_TRAIN_PRE_EMPHASIS_SHIFT);
 
 	*DP = (*DP & ~mask) | signal_levels;
 }
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 097fb85..f07a14a 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -874,6 +874,8 @@ void intel_ddi_clock_get(struct intel_encoder *encoder,
 			 struct intel_crtc_state *pipe_config);
 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
 void bxt_select_cdclk_freq(struct drm_device *dev, u32 frequency);
+void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
+				enum port port, int type);
 
 /* intel_frontbuffer.c */
 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
-- 
2.1.0

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[PATCH 49/49] drm/i915/bxt: Update max level of vswing

[Imre Deak]

From: Vandana Kannan <vandana.kannan@intel.com>

Broxton supports 3 voltage swing levels on all DP ports.
Max level of pre-emphasis will be taken care with the existing code.

v2: Patch rebased

v3: (imre)
- keep existing behavior for other platforms
- clarify commit message

Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> (v2)
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 1cb6eb0..019c224 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2832,7 +2832,9 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	enum port port = dp_to_dig_port(intel_dp)->port;
 
-	if (INTEL_INFO(dev)->gen >= 9) {
+	if (IS_BROXTON(dev))
+		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
+	else if (INTEL_INFO(dev)->gen >= 9) {
 		if (dev_priv->vbt.edp_low_vswing && port == PORT_A)
 			return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
 		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
-- 
2.1.0

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Re: [PATCH 10/49] drm/i915/bxt: map GTT as uncached

[Daniel Vetter]

On Tue, Mar 17, 2015 at 11:39:36AM +0200, Imre Deak wrote:
> On Broxton per specification the GTT has to be mapped as uncached.
> This was caught by the PTE write readback warning, which showed a
> corrupted PTE value with using the current write-combine mapping.
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_gem_gtt.c | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 4311292..8edf3cf 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -2065,7 +2065,10 @@ static int ggtt_probe_common(struct drm_device *dev,
>  	gtt_phys_addr = pci_resource_start(dev->pdev, 0) +
>  		(pci_resource_len(dev->pdev, 0) / 2);
>  
> -	dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size);
> +	if (IS_BROXTON(dev))
> +		dev_priv->gtt.gsm = ioremap_nocache(gtt_phys_addr, gtt_size);

This one sucks badly. Do we have a w/a name assigned to this, hsd filed
and some commit that this will be fixed in later revisions?
-Daniel

> +	else
> +		dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size);
>  	if (!dev_priv->gtt.gsm) {
>  		DRM_ERROR("Failed to map the gtt page table\n");
>  		return -ENOMEM;
> -- 
> 2.1.0
> 
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> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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Re: [PATCH 11/49] drm/i915/gen9: fix PIPE_CONTROL flush for VS_INVALIDATE

[Daniel Vetter]

On Tue, Mar 17, 2015 at 11:39:37AM +0200, Imre Deak wrote:
> On GEN9+ per specification a NULL PIPE_CONTROL needs to be emitted
> before any PIPE_CONTROL command with the VS_INVALIDATE flag set.
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Can you please take out the gen9/skl patches from your bxt enabling into a
separate series so that we can fastrack it?

Thanks, Daniel

> ---
>  drivers/gpu/drm/i915/intel_lrc.c | 19 ++++++++++++++++++-
>  1 file changed, 18 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index fcb074b..71aeeb3 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1262,6 +1262,7 @@ static int gen8_emit_flush_render(struct intel_ringbuffer *ringbuf,
>  {
>  	struct intel_engine_cs *ring = ringbuf->ring;
>  	u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
> +	bool vf_flush_wa;
>  	u32 flags = 0;
>  	int ret;
>  
> @@ -1283,10 +1284,26 @@ static int gen8_emit_flush_render(struct intel_ringbuffer *ringbuf,
>  		flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
>  	}
>  
> -	ret = intel_logical_ring_begin(ringbuf, ctx, 6);
> +	/*
> +	 * On GEN9+ Before VF_CACHE_INVALIDATE we need to emit a NULL pipe
> +	 * control.
> +	 */
> +	vf_flush_wa = INTEL_INFO(ring->dev)->gen >= 9 &&
> +		      flags & PIPE_CONTROL_VF_CACHE_INVALIDATE;
> +
> +	ret = intel_logical_ring_begin(ringbuf, ctx, vf_flush_wa ? 12 : 6);
>  	if (ret)
>  		return ret;
>  
> +	if (vf_flush_wa) {
> +		intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
> +		intel_logical_ring_emit(ringbuf, 0);
> +		intel_logical_ring_emit(ringbuf, 0);
> +		intel_logical_ring_emit(ringbuf, 0);
> +		intel_logical_ring_emit(ringbuf, 0);
> +		intel_logical_ring_emit(ringbuf, 0);
> +	}
> +
>  	intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
>  	intel_logical_ring_emit(ringbuf, flags);
>  	intel_logical_ring_emit(ringbuf, scratch_addr);
> -- 
> 2.1.0
> 
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Re: [PATCH 14/49] drm/i915/bxt: add GEN8_SDEUNIT_CLOCK_GATE_DISABLE workaround

[Daniel Vetter]

On Tue, Mar 17, 2015 at 11:39:40AM +0200, Imre Deak wrote:
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 3d4a7c3..d5dd0b3 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -96,7 +96,18 @@ static void skl_init_clock_gating(struct drm_device *dev)
>  
>  static void bxt_init_clock_gating(struct drm_device *dev)
>  {
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +
>  	gen9_init_clock_gating(dev);
> +
> +	/*
> +	 * FIXME:
> +	 * GEN8_SDEUNIT_CLOCK_GATE_DISABLE applies on A0 only.

We have pci revid macros now. Do you have plans to roll similar ones out
for bxt?
-Daniel

> +	 */
> +	 /* WaDisableSDEUnitClockGating:bxt */
> +	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
> +		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
> +
>  }
>  
>  static void i915_pineview_get_mem_freq(struct drm_device *dev)
> -- 
> 2.1.0
> 
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Re: [PATCH 18/49] drm/i915/bxt: add workaround to avoid PTE corruption

[Daniel Vetter]

On Tue, Mar 17, 2015 at 11:39:44AM +0200, Imre Deak wrote:
> From: Robert Beckett <robert.beckett@intel.com>
> 
> Set TLBPF in TILECTL. This fixes an issue with BXT HW seeing
> corrupted pte entries.

Is this for the ggtt or ppgtt ptes?
-Daniel

> 
> v2:
> - move the workaround to bxt_init_clock_gating (imre)
> 
> Signed-off-by: Robert Beckett <robert.beckett@intel.com> (v1)
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 1 +
>  drivers/gpu/drm/i915/intel_pm.c | 2 ++
>  2 files changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 1d074e8..d69d7b9 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1151,6 +1151,7 @@ enum skl_disp_power_wells {
>  /* control register for cpu gtt access */
>  #define TILECTL				0x101000
>  #define   TILECTL_SWZCTL			(1 << 0)
> +#define   TILECTL_TLBPF			(1 << 1)
>  #define   TILECTL_TLB_PREFETCH_DIS	(1 << 2)
>  #define   TILECTL_BACKSNOOP_DIS		(1 << 3)
>  
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 52d3c02..d3f2557 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -110,6 +110,8 @@ static void bxt_init_clock_gating(struct drm_device *dev)
>  		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE |
>  		   GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
>  
> +	/* FIXME: apply on A0 only */
> +	I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
>  }
>  
>  static void i915_pineview_get_mem_freq(struct drm_device *dev)
> -- 
> 2.1.0
> 
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Re: [PATCH 23/49] drm/i915/bxt: Increase DDI buf idle timeout

[Daniel Vetter]

On Tue, Mar 17, 2015 at 11:39:49AM +0200, Imre Deak wrote:
> From: Vandana Kannan <vandana.kannan@intel.com>
> 
> For BXT, DDI buf idle timeout delay needs to be increased to 16us.
> 
> Since this is a timeout value and we return as soon as the condition is
> realized, no penalty incurred for other platforms.
> 
> Suggested-by: Satheeshakrishna M <satheeshakrishna.m@intel.com>
> Cc: Satheeshakrishna M <satheeshakrishna.m@intel.com>
> Cc: Damien Lespiau <damien.lespiau@intel.com>
> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h  | 1 +
>  drivers/gpu/drm/i915/intel_ddi.c | 2 +-
>  2 files changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index d69d7b9..60ff760 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6576,6 +6576,7 @@ enum skl_disp_power_wells {
>  #define  DDI_BUF_EMP_MASK			(0xf<<24)
>  #define  DDI_BUF_PORT_REVERSAL			(1<<16)
>  #define  DDI_BUF_IS_IDLE			(1<<7)
> +#define  DDI_BUF_IDLE_TIMEOUT			16	  /* 16us */

Putting this sw value in the middle of all the hw register definitions is
really confusing. Imo just drop it, just adds indirection.
>  #define  DDI_A_4_LANES				(1<<4)
>  #define  DDI_PORT_WIDTH(width)			(((width) - 1) << 1)
>  #define  DDI_INIT_DISPLAY_DETECTED		(1<<0)
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 8aee7d7..a203d9d 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -322,7 +322,7 @@ static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
>  	uint32_t reg = DDI_BUF_CTL(port);
>  	int i;
>  

Instead please add a wa notice or comment here that bxt needs more timeout
delay. Otherwise someone might frob this again by accident.
-Daniel

> -	for (i = 0; i < 8; i++) {
> +	for (i = 0; i < DDI_BUF_IDLE_TIMEOUT; i++) {
>  		udelay(1);
>  		if (I915_READ(reg) & DDI_BUF_IS_IDLE)
>  			return;
> -- 
> 2.1.0
> 
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Re: [PATCH 24/49] drm/i915/bxt: DDI Hotplug interrupt setup

[Daniel Vetter]

On Tue, Mar 17, 2015 at 11:39:50AM +0200, Imre Deak wrote:
> From: Shashank Sharma <shashank.sharma@intel.com>
> 
> In BXT, DDI hotplug control has been moved to CPU from PCH.
> This patch adds a new IRQ setup function for BXT which:
> 1. Checks which HPD ports are requested to be enabled by encoders.
> 2. Enables those ports in the hot plug control register.
> 3. Un-masks these port interrupts in the IMR register.
> 4. Enables these port interrupts in the IER register.
> 
> V3: Kept the default HPD filter count to default (500 us) as per
>     satheesh's comment
> v4: Remove unused HPD filter defines (Damien)
> v5: warn if trying to setup HPD on port A (imre)
> 
> Reviewed-by: Satheeshakrishna M <satheeshakrishna.m@intel.com>
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> Signed-off-by: Shashank Sharma <shashank.sharma@intel.com> (v4)
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_irq.c | 49 ++++++++++++++++++++++++++++++++++++++++-
>  drivers/gpu/drm/i915/i915_reg.h | 25 +++++++++++++++++++++
>  2 files changed, 73 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 49ad5fb..a51c00e 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -88,6 +88,12 @@ static const u32 hpd_status_i915[HPD_NUM_PINS] = { /* i915 and valleyview are th
>  	[HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
>  };
>  
> +/* BXT hpd list */
> +static const u32 hpd_bxt[] = {
> +	[HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
> +	[HPD_PORT_C] = BXT_DE_PORT_HP_DDIC
> +};
> +
>  /* IIR can theoretically queue up two events. Be paranoid. */
>  #define GEN8_IRQ_RESET_NDX(type, which) do { \
>  	I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
> @@ -3235,6 +3241,44 @@ static void ibx_hpd_irq_setup(struct drm_device *dev)
>  	I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
>  }
>  
> +static void bxt_hpd_irq_setup(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct drm_mode_config *mode_config = &dev->mode_config;
> +	struct intel_encoder *intel_encoder;
> +	u32 hotplug_port = 0;
> +	u32 hotplug_ctrl;
> +
> +	/* Now, enable HPD */
> +	list_for_each_entry(intel_encoder, &mode_config->encoder_list,
> +		base.head) {
> +		if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark
> +				== HPD_ENABLED)
> +			hotplug_port |= hpd_bxt[intel_encoder->hpd_pin];
> +	}
> +
> +	/* Mask all HPD control bits */
> +	hotplug_ctrl = I915_READ(BXT_HOTPLUG_CTL) & ~BXT_HOTPLUG_CTL_MASK;
> +
> +	/* Enable requested port in hotplug control */
> +	/* TODO: implement (short) HPD support on port A */
> +	WARN_ON_ONCE(hotplug_port & BXT_DE_PORT_HP_DDIA);
> +	if (hotplug_port & BXT_DE_PORT_HP_DDIB)
> +		hotplug_ctrl |= BXT_DDIB_HPD_ENABLE;
> +	if (hotplug_port & BXT_DE_PORT_HP_DDIC)
> +		hotplug_ctrl |= BXT_DDIC_HPD_ENABLE;
> +	I915_WRITE(BXT_HOTPLUG_CTL, hotplug_ctrl);
> +
> +	/* Unmask DDI hotplug in IMR */
> +	hotplug_ctrl = I915_READ(GEN8_DE_PORT_IMR) & ~hotplug_port;
> +	I915_WRITE(GEN8_DE_PORT_IMR, hotplug_ctrl);
> +
> +	/* Enable DDI hotplug in IER */
> +	hotplug_ctrl = I915_READ(GEN8_DE_PORT_IER) | hotplug_port;
> +	I915_WRITE(GEN8_DE_PORT_IER, hotplug_ctrl);
> +	POSTING_READ(GEN8_DE_PORT_IER);

Out of paranoi I checked the locking here, but we seem to be save already
with dev_priv->irq_lock.

> +}
> +
>  static void ibx_irq_postinstall(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -4355,7 +4399,10 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
>  		dev->driver->irq_uninstall = gen8_irq_uninstall;
>  		dev->driver->enable_vblank = gen8_enable_vblank;
>  		dev->driver->disable_vblank = gen8_disable_vblank;
> -		dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
> +		if (HAS_PCH_SPLIT(dev))
> +			dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
> +		else
> +			dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
>  	} else if (HAS_PCH_SPLIT(dev)) {
>  		dev->driver->irq_handler = ironlake_irq_handler;
>  		dev->driver->irq_preinstall = ironlake_irq_reset;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 60ff760..1efee7d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5247,6 +5247,14 @@ enum skl_disp_power_wells {
>  #define  GEN9_AUX_CHANNEL_B		(1 << 25)
>  #define  GEN8_AUX_CHANNEL_A		(1 << 0)
>  
> +/* Gen 9 BXT DDI Hotplug */
> +#define BXT_DE_PORT_HP_DDIC		(1 << 5)
> +#define BXT_DE_PORT_HP_DDIB		(1 << 4)
> +#define BXT_DE_PORT_HP_DDIA		(1 << 3)
> +#define BXT_DE_PORT_HOTPLUG_MASK	(BXT_DE_PORT_HP_DDIA | \
> +					BXT_DE_PORT_HP_DDIB | \
> +					BXT_DE_PORT_HP_DDIC)

Generally we interleave definitions for different platforms if it's the
same register.
> +
>  #define GEN8_DE_MISC_ISR 0x44460
>  #define GEN8_DE_MISC_IMR 0x44464
>  #define GEN8_DE_MISC_IIR 0x44468
> @@ -5258,6 +5266,23 @@ enum skl_disp_power_wells {
>  #define GEN8_PCU_IIR 0x444e8
>  #define GEN8_PCU_IER 0x444ec
>  
> +/* BXT hotplug control */
> +#define BXT_HOTPLUG_CTL		0xC4030
> +#define BXT_DDIA_HPD_ENABLE		(1 << 28)
> +#define BXT_DDIB_HPD_ENABLE		(1 << 4)
> +#define BXT_DDIC_HPD_ENABLE		(1 << 12)
> +#define BXT_HOTPLUG_CTL_MASK		(BXT_DDIA_HPD_ENABLE | \
> +					BXT_DDIB_HPD_ENABLE | \
> +					BXT_DDIC_HPD_ENABLE)
> +
> +/* Hot plug status */
> +#define BXT_DDIA_HPD_STATUS		(3 << 24)
> +#define BXT_DDIB_HPD_STATUS		(3 << 0)
> +#define BXT_DDIC_HPD_STATUS		(3 << 8)
> +#define BXT_HPD_STATUS_MASK		(BXT_DDIA_HPD_STATUS | \
> +					BXT_DDIB_HPD_STATUS | \
> +					BXT_DDIC_HPD_STATUS)
> +
>  #define ILK_DISPLAY_CHICKEN2	0x42004
>  /* Required on all Ironlake and Sandybridge according to the B-Spec. */
>  #define  ILK_ELPIN_409_SELECT	(1 << 25)
> -- 
> 2.1.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [PATCH 25/49] drm/i915/bxt: Add DDI hpd handler

[Daniel Vetter]

On Tue, Mar 17, 2015 at 11:39:51AM +0200, Imre Deak wrote:
> From: Shashank Sharma <shashank.sharma@intel.com>
> 
> This patch adds a hot plug interrupt handler function for BXT.
> What this function typically does is:
> 1. Check if hot plug is enabled from hot plug control register.
> 2. Call hpd_irq_handler with appropriate trigger to detect a
>    plug storm and schedule a bottom half.
> 3. Clear sticky status bits in hot plug control register..
> 
> Reviewed-by: Satheeshakrishna M <satheeshakrishna.m@intel.com>
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_irq.c | 45 +++++++++++++++++++++++++++++++++++++++--
>  1 file changed, 43 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index a51c00e..4a2f85b 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2227,6 +2227,38 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg)
>  	return ret;
>  }
>  
> +static void bxt_hpd_handler(struct drm_device *dev, uint32_t iir_status)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	uint32_t hp_control;
> +	uint32_t hp_trigger;
> +
> +	/* Get the status */
> +	hp_trigger = iir_status & BXT_DE_PORT_HOTPLUG_MASK;
> +	hp_control = I915_READ(BXT_HOTPLUG_CTL);
> +
> +	/* Hotplug not enabled ? */
> +	if (unlikely(!(hp_control & BXT_HOTPLUG_CTL_MASK))) {
> +		DRM_ERROR("Interrupt when HPD disabled\n");
> +		return;
> +	}
> +
> +	DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
> +		hp_control & BXT_HOTPLUG_CTL_MASK);
> +
> +	/* Check for HPD storm and schedule bottom half */
> +	intel_hpd_irq_handler(dev, hp_trigger, hp_control, hpd_bxt);
> +
> +	/*
> +	 * Todo: Save the hot plug status for bottom half before
> +	 * clearing the sticky status bits, else the status will be
> +	 * lost.
> +	 */

This seems to be ok, but code to handle long/short pulse in
intel_hpd_irq_handler seems to be missing. And we absolutely need that for
mst ports (I guess bxt has those?).
-Daniel

> +
> +	/* Clear sticky bits in hpd status */
> +	I915_WRITE(BXT_HOTPLUG_CTL, hp_control);
> +}
> +
>  static irqreturn_t gen8_irq_handler(int irq, void *arg)
>  {
>  	struct drm_device *dev = arg;
> @@ -2236,6 +2268,7 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
>  	uint32_t tmp = 0;
>  	enum pipe pipe;
>  	u32 aux_mask = GEN8_AUX_CHANNEL_A;
> +	bool found = false;
>  
>  	if (!intel_irqs_enabled(dev_priv))
>  		return IRQ_NONE;
> @@ -2276,9 +2309,17 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
>  			I915_WRITE(GEN8_DE_PORT_IIR, tmp);
>  			ret = IRQ_HANDLED;
>  
> -			if (tmp & aux_mask)
> +			if (tmp & aux_mask) {
>  				dp_aux_irq_handler(dev);
> -			else
> +				found = true;
> +			}
> +
> +			if (tmp & BXT_DE_PORT_HOTPLUG_MASK) {
> +				bxt_hpd_handler(dev, tmp);
> +				found = true;
> +			}
> +
> +			if (!found)
>  				DRM_ERROR("Unexpected DE Port interrupt\n");
>  		}
>  		else
> -- 
> 2.1.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
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Re: [PATCH 29/49] drm/i915: Rename vlv_cdclk_freq to cdclk_freq

[Daniel Vetter]

On Tue, Mar 17, 2015 at 11:39:55AM +0200, Imre Deak wrote:
> From: Vandana Kannan <vandana.kannan@intel.com>
> 
> Rename vlv_cdclk_freq to cdclk_freq so that it can be used for all
> platforms as required. Needed by the next patch.

Nah, we name functions by the first platform that introduces them, not
just drop the prefix when it's used for a bit longer. cdclock goes back as
a concept since forever, so this is definitely way too generic a name.
-Daniel

> 
> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
> Signed-off-by: A.Sunil Kamath <sunil.kamath@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h      |  2 +-
>  drivers/gpu/drm/i915/intel_display.c | 18 ++++++++++--------
>  2 files changed, 11 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 52e5f18..1b2a294 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1659,7 +1659,7 @@ struct drm_i915_private {
>  	int num_fence_regs; /* 8 on pre-965, 16 otherwise */
>  
>  	unsigned int fsb_freq, mem_freq, is_ddr3;
> -	unsigned int vlv_cdclk_freq;
> +	unsigned int cdclk_freq;
>  	unsigned int hpll_freq;
>  
>  	/**
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index e54e948..b91862e 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4879,16 +4879,16 @@ static void vlv_update_cdclk(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  
> -	dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
> +	dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
>  	DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
> -			 dev_priv->vlv_cdclk_freq);
> +			 dev_priv->cdclk_freq);
>  
>  	/*
>  	 * Program the gmbus_freq based on the cdclk frequency.
>  	 * BSpec erroneously claims we should aim for 4MHz, but
>  	 * in fact 1MHz is the correct frequency.
>  	 */
> -	I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
> +	I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
>  }
>  
>  /* Adjust CDclk dividers to allow high res or save power if possible */
> @@ -4897,7 +4897,8 @@ static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	u32 val, cmd;
>  
> -	WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
> +	WARN_ON(dev_priv->display.get_display_clock_speed(dev)
> +					!= dev_priv->cdclk_freq);
>  
>  	if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
>  		cmd = 2;
> @@ -4961,7 +4962,8 @@ static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	u32 val, cmd;
>  
> -	WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
> +	WARN_ON(dev_priv->display.get_display_clock_speed(dev)
> +						!= dev_priv->cdclk_freq);
>  
>  	switch (cdclk) {
>  	case 333333:
> @@ -5050,7 +5052,7 @@ static void valleyview_modeset_global_pipes(struct drm_device *dev,
>  	int max_pixclk = intel_mode_max_pixclk(dev_priv);
>  
>  	if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
> -	    dev_priv->vlv_cdclk_freq)
> +	    dev_priv->cdclk_freq)
>  		return;
>  
>  	/* disable/enable all currently active pipes while we change cdclk */
> @@ -5068,7 +5070,7 @@ static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
>  	else
>  		default_credits = PFI_CREDIT(8);
>  
> -	if (DIV_ROUND_CLOSEST(dev_priv->vlv_cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
> +	if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
>  		/* CHV suggested value is 31 or 63 */
>  		if (IS_CHERRYVIEW(dev_priv))
>  			credits = PFI_CREDIT_31;
> @@ -5101,7 +5103,7 @@ static void valleyview_modeset_global_resources(struct drm_device *dev)
>  	int max_pixclk = intel_mode_max_pixclk(dev_priv);
>  	int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
>  
> -	if (req_cdclk != dev_priv->vlv_cdclk_freq) {
> +	if (req_cdclk != dev_priv->cdclk_freq) {
>  		/*
>  		 * FIXME: We can end up here with all power domains off, yet
>  		 * with a CDCLK frequency other than the minimum. To account
> -- 
> 2.1.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
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Re: [PATCH 10/49] drm/i915/bxt: map GTT as uncached

[Imre Deak]

On ti, 2015-03-17 at 11:33 +0100, Daniel Vetter wrote:
> On Tue, Mar 17, 2015 at 11:39:36AM +0200, Imre Deak wrote:
> > On Broxton per specification the GTT has to be mapped as uncached.
> > This was caught by the PTE write readback warning, which showed a
> > corrupted PTE value with using the current write-combine mapping.
> > 
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_gem_gtt.c | 5 ++++-
> >  1 file changed, 4 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > index 4311292..8edf3cf 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > @@ -2065,7 +2065,10 @@ static int ggtt_probe_common(struct drm_device *dev,
> >  	gtt_phys_addr = pci_resource_start(dev->pdev, 0) +
> >  		(pci_resource_len(dev->pdev, 0) / 2);
> >  
> > -	dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size);
> > +	if (IS_BROXTON(dev))
> > +		dev_priv->gtt.gsm = ioremap_nocache(gtt_phys_addr, gtt_size);
> 
> This one sucks badly. Do we have a w/a name assigned to this, hsd filed
> and some commit that this will be fixed in later revisions?

We filed an HSD for this, it's closed now with the explanation from HW
people that WC mapping for the GTT is invalid: "Writes larger than QW to
GTTMMADR space will get dropped on BXT."
"Writes" here refers to the 64 byte burst write from the WC buffer.

Based on the above this isn't a w/a, so no name for it. I think Jesse is
about to file a feature request to support WC mappings in the future.

--Imre


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Re: [PATCH 14/49] drm/i915/bxt: add GEN8_SDEUNIT_CLOCK_GATE_DISABLE workaround

[Imre Deak]

On ti, 2015-03-17 at 11:35 +0100, Daniel Vetter wrote:
> On Tue, Mar 17, 2015 at 11:39:40AM +0200, Imre Deak wrote:
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_pm.c | 11 +++++++++++
> >  1 file changed, 11 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 3d4a7c3..d5dd0b3 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -96,7 +96,18 @@ static void skl_init_clock_gating(struct drm_device *dev)
> >  
> >  static void bxt_init_clock_gating(struct drm_device *dev)
> >  {
> > +	struct drm_i915_private *dev_priv = dev->dev_private;
> > +
> >  	gen9_init_clock_gating(dev);
> > +
> > +	/*
> > +	 * FIXME:
> > +	 * GEN8_SDEUNIT_CLOCK_GATE_DISABLE applies on A0 only.
> 
> We have pci revid macros now. Do you have plans to roll similar ones out
> for bxt?

Yes. It may be that for BXT we also need to look at the PCI_REVISION_ID
field besides PCI_CLASS_REVISION, I still have to figure out the exact
mapping. (And also understand the meaning/difference between SOC vs. GT
revision IDs).

--Imre

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Re: [PATCH 29/49] drm/i915: Rename vlv_cdclk_freq to cdclk_freq

[Ville Syrjälä]

On Tue, Mar 17, 2015 at 11:54:52AM +0100, Daniel Vetter wrote:
> On Tue, Mar 17, 2015 at 11:39:55AM +0200, Imre Deak wrote:
> > From: Vandana Kannan <vandana.kannan@intel.com>
> > 
> > Rename vlv_cdclk_freq to cdclk_freq so that it can be used for all
> > platforms as required. Needed by the next patch.
> 
> Nah, we name functions by the first platform that introduces them, not
> just drop the prefix when it's used for a bit longer. cdclock goes back as
> a concept since forever, so this is definitely way too generic a name.

I might go on to point people at my cdclk series:
http://lists.freedesktop.org/archives/intel-gfx/2014-November/055640.html

> -Daniel
> 
> > 
> > Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
> > Signed-off-by: A.Sunil Kamath <sunil.kamath@intel.com>
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_drv.h      |  2 +-
> >  drivers/gpu/drm/i915/intel_display.c | 18 ++++++++++--------
> >  2 files changed, 11 insertions(+), 9 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 52e5f18..1b2a294 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1659,7 +1659,7 @@ struct drm_i915_private {
> >  	int num_fence_regs; /* 8 on pre-965, 16 otherwise */
> >  
> >  	unsigned int fsb_freq, mem_freq, is_ddr3;
> > -	unsigned int vlv_cdclk_freq;
> > +	unsigned int cdclk_freq;
> >  	unsigned int hpll_freq;
> >  
> >  	/**
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index e54e948..b91862e 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -4879,16 +4879,16 @@ static void vlv_update_cdclk(struct drm_device *dev)
> >  {
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> >  
> > -	dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
> > +	dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
> >  	DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
> > -			 dev_priv->vlv_cdclk_freq);
> > +			 dev_priv->cdclk_freq);
> >  
> >  	/*
> >  	 * Program the gmbus_freq based on the cdclk frequency.
> >  	 * BSpec erroneously claims we should aim for 4MHz, but
> >  	 * in fact 1MHz is the correct frequency.
> >  	 */
> > -	I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
> > +	I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
> >  }
> >  
> >  /* Adjust CDclk dividers to allow high res or save power if possible */
> > @@ -4897,7 +4897,8 @@ static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> >  	u32 val, cmd;
> >  
> > -	WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
> > +	WARN_ON(dev_priv->display.get_display_clock_speed(dev)
> > +					!= dev_priv->cdclk_freq);
> >  
> >  	if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
> >  		cmd = 2;
> > @@ -4961,7 +4962,8 @@ static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> >  	u32 val, cmd;
> >  
> > -	WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
> > +	WARN_ON(dev_priv->display.get_display_clock_speed(dev)
> > +						!= dev_priv->cdclk_freq);
> >  
> >  	switch (cdclk) {
> >  	case 333333:
> > @@ -5050,7 +5052,7 @@ static void valleyview_modeset_global_pipes(struct drm_device *dev,
> >  	int max_pixclk = intel_mode_max_pixclk(dev_priv);
> >  
> >  	if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
> > -	    dev_priv->vlv_cdclk_freq)
> > +	    dev_priv->cdclk_freq)
> >  		return;
> >  
> >  	/* disable/enable all currently active pipes while we change cdclk */
> > @@ -5068,7 +5070,7 @@ static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
> >  	else
> >  		default_credits = PFI_CREDIT(8);
> >  
> > -	if (DIV_ROUND_CLOSEST(dev_priv->vlv_cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
> > +	if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
> >  		/* CHV suggested value is 31 or 63 */
> >  		if (IS_CHERRYVIEW(dev_priv))
> >  			credits = PFI_CREDIT_31;
> > @@ -5101,7 +5103,7 @@ static void valleyview_modeset_global_resources(struct drm_device *dev)
> >  	int max_pixclk = intel_mode_max_pixclk(dev_priv);
> >  	int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
> >  
> > -	if (req_cdclk != dev_priv->vlv_cdclk_freq) {
> > +	if (req_cdclk != dev_priv->cdclk_freq) {
> >  		/*
> >  		 * FIXME: We can end up here with all power domains off, yet
> >  		 * with a CDCLK frequency other than the minimum. To account
> > -- 
> > 2.1.0
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 18/49] drm/i915/bxt: add workaround to avoid PTE corruption

[Imre Deak]

On ti, 2015-03-17 at 11:36 +0100, Daniel Vetter wrote:
> On Tue, Mar 17, 2015 at 11:39:44AM +0200, Imre Deak wrote:
> > From: Robert Beckett <robert.beckett@intel.com>
> > 
> > Set TLBPF in TILECTL. This fixes an issue with BXT HW seeing
> > corrupted pte entries.
> 
> Is this for the ggtt or ppgtt ptes?

Robert, did you see how this problem manifests? I just copied the w/a
from your branch and checked it against BSpec, but haven't seen the
actual problem.

Thanks,
Imre


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Re: [PATCH 10/49] drm/i915/bxt: map GTT as uncached

[Daniel Vetter]

On Tue, Mar 17, 2015 at 02:31:29PM +0200, Imre Deak wrote:
> On ti, 2015-03-17 at 11:33 +0100, Daniel Vetter wrote:
> > On Tue, Mar 17, 2015 at 11:39:36AM +0200, Imre Deak wrote:
> > > On Broxton per specification the GTT has to be mapped as uncached.
> > > This was caught by the PTE write readback warning, which showed a
> > > corrupted PTE value with using the current write-combine mapping.
> > > 
> > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/i915_gem_gtt.c | 5 ++++-
> > >  1 file changed, 4 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > > index 4311292..8edf3cf 100644
> > > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> > > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > > @@ -2065,7 +2065,10 @@ static int ggtt_probe_common(struct drm_device *dev,
> > >  	gtt_phys_addr = pci_resource_start(dev->pdev, 0) +
> > >  		(pci_resource_len(dev->pdev, 0) / 2);
> > >  
> > > -	dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size);
> > > +	if (IS_BROXTON(dev))
> > > +		dev_priv->gtt.gsm = ioremap_nocache(gtt_phys_addr, gtt_size);
> > 
> > This one sucks badly. Do we have a w/a name assigned to this, hsd filed
> > and some commit that this will be fixed in later revisions?
> 
> We filed an HSD for this, it's closed now with the explanation from HW
> people that WC mapping for the GTT is invalid: "Writes larger than QW to
> GTTMMADR space will get dropped on BXT."
> "Writes" here refers to the 64 byte burst write from the WC buffer.
> 
> Based on the above this isn't a w/a, so no name for it. I think Jesse is
> about to file a feature request to support WC mappings in the future.

I guess then we need a big comment for this :(
-Daniel
-- 
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Re: [PATCH 35/49] drm/i915/bxt: fix panel fitter setup in crtc disable/enable

[Daniel Vetter]

On Tue, Mar 17, 2015 at 11:40:01AM +0200, Imre Deak wrote:
> From: Jesse Barnes <jbarnes@virtuousgeek.org>
> 
> Broxton has the same panel fitter registers as Skylake.
> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index ba2d1ae..95ce0a8 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4532,7 +4532,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
>  
>  	intel_ddi_enable_pipe_clock(intel_crtc);
>  
> -	if (IS_SKYLAKE(dev))
> +	if (INTEL_INFO(dev)->gen == 9)

Shouldn't we go with gen >= 9 here while at it?
-Daniel

>  		skylake_pfit_enable(intel_crtc);
>  	else
>  		ironlake_pfit_enable(intel_crtc);
> @@ -4695,7 +4695,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
>  
>  	intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
>  
> -	if (IS_SKYLAKE(dev))
> +	if (INTEL_INFO(dev)->gen == 9)
>  		skylake_pfit_disable(intel_crtc);
>  	else
>  		ironlake_pfit_disable(intel_crtc);
> @@ -8504,7 +8504,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
>  
>  	pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
>  	if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
> -		if (IS_SKYLAKE(dev))
> +		if (INTEL_INFO(dev)->gen == 9)
>  			skylake_get_pfit_config(crtc, pipe_config);
>  		else
>  			ironlake_get_pfit_config(crtc, pipe_config);
> -- 
> 2.1.0
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

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Re: [PATCH 35/49] drm/i915/bxt: fix panel fitter setup in crtc disable/enable

[Imre Deak]

On ti, 2015-03-17 at 14:51 +0100, Daniel Vetter wrote:
> On Tue, Mar 17, 2015 at 11:40:01AM +0200, Imre Deak wrote:
> > From: Jesse Barnes <jbarnes@virtuousgeek.org>
> > 
> > Broxton has the same panel fitter registers as Skylake.
> > 
> > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_display.c | 6 +++---
> >  1 file changed, 3 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index ba2d1ae..95ce0a8 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -4532,7 +4532,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
> >  
> >  	intel_ddi_enable_pipe_clock(intel_crtc);
> >  
> > -	if (IS_SKYLAKE(dev))
> > +	if (INTEL_INFO(dev)->gen == 9)
> 
> Shouldn't we go with gen >= 9 here while at it?

== 9 looks like the right choice based on bspec.

--Imre


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Re: [PATCH 24/49] drm/i915/bxt: DDI Hotplug interrupt setup

[Imre Deak]

On ti, 2015-03-17 at 11:48 +0100, Daniel Vetter wrote:
> On Tue, Mar 17, 2015 at 11:39:50AM +0200, Imre Deak wrote:
> > From: Shashank Sharma <shashank.sharma@intel.com>
> > 
> > In BXT, DDI hotplug control has been moved to CPU from PCH.
> > This patch adds a new IRQ setup function for BXT which:
> > 1. Checks which HPD ports are requested to be enabled by encoders.
> > 2. Enables those ports in the hot plug control register.
> > 3. Un-masks these port interrupts in the IMR register.
> > 4. Enables these port interrupts in the IER register.
> > 
> > V3: Kept the default HPD filter count to default (500 us) as per
> >     satheesh's comment
> > v4: Remove unused HPD filter defines (Damien)
> > v5: warn if trying to setup HPD on port A (imre)
> > 
> > Reviewed-by: Satheeshakrishna M <satheeshakrishna.m@intel.com>
> > Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> > Signed-off-by: Shashank Sharma <shashank.sharma@intel.com> (v4)
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_irq.c | 49 ++++++++++++++++++++++++++++++++++++++++-
> >  drivers/gpu/drm/i915/i915_reg.h | 25 +++++++++++++++++++++
> >  2 files changed, 73 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> > index 49ad5fb..a51c00e 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -88,6 +88,12 @@ static const u32 hpd_status_i915[HPD_NUM_PINS] = { /* i915 and valleyview are th
> >  	[HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
> >  };
> >  
> > +/* BXT hpd list */
> > +static const u32 hpd_bxt[] = {
> > +	[HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
> > +	[HPD_PORT_C] = BXT_DE_PORT_HP_DDIC
> > +};
> > +
> >  /* IIR can theoretically queue up two events. Be paranoid. */
> >  #define GEN8_IRQ_RESET_NDX(type, which) do { \
> >  	I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
> > @@ -3235,6 +3241,44 @@ static void ibx_hpd_irq_setup(struct drm_device *dev)
> >  	I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
> >  }
> >  
> > +static void bxt_hpd_irq_setup(struct drm_device *dev)
> > +{
> > +	struct drm_i915_private *dev_priv = dev->dev_private;
> > +	struct drm_mode_config *mode_config = &dev->mode_config;
> > +	struct intel_encoder *intel_encoder;
> > +	u32 hotplug_port = 0;
> > +	u32 hotplug_ctrl;
> > +
> > +	/* Now, enable HPD */
> > +	list_for_each_entry(intel_encoder, &mode_config->encoder_list,
> > +		base.head) {
> > +		if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark
> > +				== HPD_ENABLED)
> > +			hotplug_port |= hpd_bxt[intel_encoder->hpd_pin];
> > +	}
> > +
> > +	/* Mask all HPD control bits */
> > +	hotplug_ctrl = I915_READ(BXT_HOTPLUG_CTL) & ~BXT_HOTPLUG_CTL_MASK;
> > +
> > +	/* Enable requested port in hotplug control */
> > +	/* TODO: implement (short) HPD support on port A */
> > +	WARN_ON_ONCE(hotplug_port & BXT_DE_PORT_HP_DDIA);
> > +	if (hotplug_port & BXT_DE_PORT_HP_DDIB)
> > +		hotplug_ctrl |= BXT_DDIB_HPD_ENABLE;
> > +	if (hotplug_port & BXT_DE_PORT_HP_DDIC)
> > +		hotplug_ctrl |= BXT_DDIC_HPD_ENABLE;
> > +	I915_WRITE(BXT_HOTPLUG_CTL, hotplug_ctrl);
> > +
> > +	/* Unmask DDI hotplug in IMR */
> > +	hotplug_ctrl = I915_READ(GEN8_DE_PORT_IMR) & ~hotplug_port;
> > +	I915_WRITE(GEN8_DE_PORT_IMR, hotplug_ctrl);
> > +
> > +	/* Enable DDI hotplug in IER */
> > +	hotplug_ctrl = I915_READ(GEN8_DE_PORT_IER) | hotplug_port;
> > +	I915_WRITE(GEN8_DE_PORT_IER, hotplug_ctrl);
> > +	POSTING_READ(GEN8_DE_PORT_IER);
> 
> Out of paranoi I checked the locking here, but we seem to be save already
> with dev_priv->irq_lock.
> 
> > +}
> > +
> >  static void ibx_irq_postinstall(struct drm_device *dev)
> >  {
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> > @@ -4355,7 +4399,10 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
> >  		dev->driver->irq_uninstall = gen8_irq_uninstall;
> >  		dev->driver->enable_vblank = gen8_enable_vblank;
> >  		dev->driver->disable_vblank = gen8_disable_vblank;
> > -		dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
> > +		if (HAS_PCH_SPLIT(dev))
> > +			dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
> > +		else
> > +			dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
> >  	} else if (HAS_PCH_SPLIT(dev)) {
> >  		dev->driver->irq_handler = ironlake_irq_handler;
> >  		dev->driver->irq_preinstall = ironlake_irq_reset;
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 60ff760..1efee7d 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -5247,6 +5247,14 @@ enum skl_disp_power_wells {
> >  #define  GEN9_AUX_CHANNEL_B		(1 << 25)
> >  #define  GEN8_AUX_CHANNEL_A		(1 << 0)
> >  
> > +/* Gen 9 BXT DDI Hotplug */
> > +#define BXT_DE_PORT_HP_DDIC		(1 << 5)
> > +#define BXT_DE_PORT_HP_DDIB		(1 << 4)
> > +#define BXT_DE_PORT_HP_DDIA		(1 << 3)
> > +#define BXT_DE_PORT_HOTPLUG_MASK	(BXT_DE_PORT_HP_DDIA | \
> > +					BXT_DE_PORT_HP_DDIB | \
> > +					BXT_DE_PORT_HP_DDIC)
> 
> Generally we interleave definitions for different platforms if it's the
> same register.

The list was already a bit mis-ordered, but agreed, will clean this up.

> > +
> >  #define GEN8_DE_MISC_ISR 0x44460
> >  #define GEN8_DE_MISC_IMR 0x44464
> >  #define GEN8_DE_MISC_IIR 0x44468
> > @@ -5258,6 +5266,23 @@ enum skl_disp_power_wells {
> >  #define GEN8_PCU_IIR 0x444e8
> >  #define GEN8_PCU_IER 0x444ec
> >  
> > +/* BXT hotplug control */
> > +#define BXT_HOTPLUG_CTL		0xC4030
> > +#define BXT_DDIA_HPD_ENABLE		(1 << 28)
> > +#define BXT_DDIB_HPD_ENABLE		(1 << 4)
> > +#define BXT_DDIC_HPD_ENABLE		(1 << 12)
> > +#define BXT_HOTPLUG_CTL_MASK		(BXT_DDIA_HPD_ENABLE | \
> > +					BXT_DDIB_HPD_ENABLE | \
> > +					BXT_DDIC_HPD_ENABLE)
> > +
> > +/* Hot plug status */
> > +#define BXT_DDIA_HPD_STATUS		(3 << 24)
> > +#define BXT_DDIB_HPD_STATUS		(3 << 0)
> > +#define BXT_DDIC_HPD_STATUS		(3 << 8)
> > +#define BXT_HPD_STATUS_MASK		(BXT_DDIA_HPD_STATUS | \
> > +					BXT_DDIB_HPD_STATUS | \
> > +					BXT_DDIC_HPD_STATUS)
> > +
> >  #define ILK_DISPLAY_CHICKEN2	0x42004
> >  /* Required on all Ironlake and Sandybridge according to the B-Spec. */
> >  #define  ILK_ELPIN_409_SELECT	(1 << 25)
> > -- 
> > 2.1.0
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 


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Re: [PATCH 25/49] drm/i915/bxt: Add DDI hpd handler

[Imre Deak]

On ti, 2015-03-17 at 11:52 +0100, Daniel Vetter wrote:
> On Tue, Mar 17, 2015 at 11:39:51AM +0200, Imre Deak wrote:
> > From: Shashank Sharma <shashank.sharma@intel.com>
> > 
> > This patch adds a hot plug interrupt handler function for BXT.
> > What this function typically does is:
> > 1. Check if hot plug is enabled from hot plug control register.
> > 2. Call hpd_irq_handler with appropriate trigger to detect a
> >    plug storm and schedule a bottom half.
> > 3. Clear sticky status bits in hot plug control register..
> > 
> > Reviewed-by: Satheeshakrishna M <satheeshakrishna.m@intel.com>
> > Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> > Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_irq.c | 45 +++++++++++++++++++++++++++++++++++++++--
> >  1 file changed, 43 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> > index a51c00e..4a2f85b 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -2227,6 +2227,38 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg)
> >  	return ret;
> >  }
> >  
> > +static void bxt_hpd_handler(struct drm_device *dev, uint32_t iir_status)
> > +{
> > +	struct drm_i915_private *dev_priv = dev->dev_private;
> > +	uint32_t hp_control;
> > +	uint32_t hp_trigger;
> > +
> > +	/* Get the status */
> > +	hp_trigger = iir_status & BXT_DE_PORT_HOTPLUG_MASK;
> > +	hp_control = I915_READ(BXT_HOTPLUG_CTL);
> > +
> > +	/* Hotplug not enabled ? */
> > +	if (unlikely(!(hp_control & BXT_HOTPLUG_CTL_MASK))) {
> > +		DRM_ERROR("Interrupt when HPD disabled\n");
> > +		return;
> > +	}
> > +
> > +	DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
> > +		hp_control & BXT_HOTPLUG_CTL_MASK);
> > +
> > +	/* Check for HPD storm and schedule bottom half */
> > +	intel_hpd_irq_handler(dev, hp_trigger, hp_control, hpd_bxt);
> > +
> > +	/*
> > +	 * Todo: Save the hot plug status for bottom half before
> > +	 * clearing the sticky status bits, else the status will be
> > +	 * lost.
> > +	 */
> 
> This seems to be ok, but code to handle long/short pulse in
> intel_hpd_irq_handler seems to be missing.

Oops. Yea, that's completely missing, we need at least a new
bxt_port_to_hotplug_shift(). Will follow up with this. Why always
shuffling around the bits??:)

> And we absolutely need that for
> mst ports (I guess bxt has those?).

Yea, port B and C.

--Imre


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Re: [PATCH 02/49] drm/i915/bxt: BXT FBC enablement

[Rodrigo Vivi]

Does BXT really has fbc? And same implementation and registers as HSW?

On Tue, Mar 17, 2015 at 2:39 AM, Imre Deak <imre.deak@intel.com> wrote:
> From: Daisy Sun <daisy.sun@intel.com>
>
> Enable FBC feature on Broxton
>
> Issue: VIZ-3784
> Signed-off-by: Daisy Sun <daisy.sun@intel.com>
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 4d50785..48434cb6 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -388,6 +388,7 @@ static const struct intel_device_info intel_broxton_info = {
>         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
>         .num_pipes = 3,
>         .has_ddi = 1,
> +       .has_fbc = 1,
>         GEN_DEFAULT_PIPEOFFSETS,
>         IVB_CURSOR_OFFSETS,
>  };
> --
> 2.1.0
>
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



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Re: [PATCH 49/49] drm/i915/bxt: Update max level of vswing

[shuang.he]

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 5978
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                 -1              268/268              267/268
ILK                 -1              303/303              302/303
SNB                                  283/283              283/283
IVB                 -1              343/343              342/343
BYT                                  287/287              287/287
HSW                 -4              319/319              315/319
BDW                                  308/308              308/308
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
*PNV  igt_gem_userptr_blits_minor-normal-sync      PASS(3)      DMESG_WARN(1)PASS(1)
*ILK  igt_drv_suspend_fence-restore-untiled      PASS(2)      DMESG_WARN(1)PASS(1)
*IVB  igt_gem_storedw_batches_loop_normal      PASS(2)      DMESG_WARN(1)PASS(1)
*HSW  igt_pm_rpm_cursor      PASS(2)      TIMEOUT(1)PASS(1)
*HSW  igt_pm_rpm_cursor-dpms      PASS(2)      TIMEOUT(2)
*HSW  igt_pm_rpm_debugfs-forcewake-user      PASS(2)      TIMEOUT(1)
*HSW  igt_pm_rpm_debugfs-read      PASS(2)      TIMEOUT(1)
Note: You need to pay more attention to line start with '*'
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Re: [PATCH 35/49] drm/i915/bxt: fix panel fitter setup in crtc disable/enable

[Daniel Vetter]

On Tue, Mar 17, 2015 at 04:22:33PM +0200, Imre Deak wrote:
> On ti, 2015-03-17 at 14:51 +0100, Daniel Vetter wrote:
> > On Tue, Mar 17, 2015 at 11:40:01AM +0200, Imre Deak wrote:
> > > From: Jesse Barnes <jbarnes@virtuousgeek.org>
> > > 
> > > Broxton has the same panel fitter registers as Skylake.
> > > 
> > > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/intel_display.c | 6 +++---
> > >  1 file changed, 3 insertions(+), 3 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > > index ba2d1ae..95ce0a8 100644
> > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > @@ -4532,7 +4532,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
> > >  
> > >  	intel_ddi_enable_pipe_clock(intel_crtc);
> > >  
> > > -	if (IS_SKYLAKE(dev))
> > > +	if (INTEL_INFO(dev)->gen == 9)
> > 
> > Shouldn't we go with gen >= 9 here while at it?
> 
> == 9 looks like the right choice based on bspec.

Then maybe add a else if (gen > 9) MISSING_CASE(gen); afterwards? Just
trying to avoid surprises when enabling skl/bxt+1 ...
-Daniel
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Re: [PATCH 35/49] drm/i915/bxt: fix panel fitter setup in crtc disable/enable

[Imre Deak]

On ke, 2015-03-18 at 09:37 +0100, Daniel Vetter wrote:
> On Tue, Mar 17, 2015 at 04:22:33PM +0200, Imre Deak wrote:
> > On ti, 2015-03-17 at 14:51 +0100, Daniel Vetter wrote:
> > > On Tue, Mar 17, 2015 at 11:40:01AM +0200, Imre Deak wrote:
> > > > From: Jesse Barnes <jbarnes@virtuousgeek.org>
> > > > 
> > > > Broxton has the same panel fitter registers as Skylake.
> > > > 
> > > > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> > > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > > ---
> > > >  drivers/gpu/drm/i915/intel_display.c | 6 +++---
> > > >  1 file changed, 3 insertions(+), 3 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > > > index ba2d1ae..95ce0a8 100644
> > > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > > @@ -4532,7 +4532,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
> > > >  
> > > >  	intel_ddi_enable_pipe_clock(intel_crtc);
> > > >  
> > > > -	if (IS_SKYLAKE(dev))
> > > > +	if (INTEL_INFO(dev)->gen == 9)
> > > 
> > > Shouldn't we go with gen >= 9 here while at it?
> > 
> > == 9 looks like the right choice based on bspec.
> 
> Then maybe add a else if (gen > 9) MISSING_CASE(gen); afterwards? Just
> trying to avoid surprises when enabling skl/bxt+1 ...

Yea, makes sense. I'll update the patch.

--Imre


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Re: [PATCH 12/49] drm/i915/bxt: HardWare WorkAround ring initialisation for Broxton

[Nick Hoath]

On 17/03/2015 09:39, Imre Deak wrote:
> From: Nick Hoath <nicholas.hoath@intel.com>
>
> Adds framework for Broxton HW WAs
>
> Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Reviewed-by: Nick Hoath <nicholas.hoath@intel.com>

> ---
>   drivers/gpu/drm/i915/intel_ringbuffer.c | 12 ++++++++++--
>   1 file changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 441e250..abe062a 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -1027,6 +1027,13 @@ static int skl_init_workarounds(struct intel_engine_cs *ring)
>   	return skl_tune_iz_hashing(ring);
>   }
>
> +static int bxt_init_workarounds(struct intel_engine_cs *ring)
> +{
> +	gen9_init_workarounds(ring);
> +
> +	return 0;
> +}
> +
>   int init_workarounds_ring(struct intel_engine_cs *ring)
>   {
>   	struct drm_device *dev = ring->dev;
> @@ -1044,8 +1051,9 @@ int init_workarounds_ring(struct intel_engine_cs *ring)
>
>   	if (IS_SKYLAKE(dev))
>   		return skl_init_workarounds(ring);
> -	else if (IS_GEN9(dev))
> -		return gen9_init_workarounds(ring);
> +
> +	if (IS_BROXTON(dev))
> +		return bxt_init_workarounds(ring);
>
>   	return 0;
>   }
>

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Re: [PATCH 13/49] drm/i915/bxt: add bxt_init_clock_gating

[Nick Hoath]

On 17/03/2015 09:39, Imre Deak wrote:
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_pm.c | 12 +++++++++++-
>   1 file changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index b89ab4d..3d4a7c3 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -94,6 +94,11 @@ static void skl_init_clock_gating(struct drm_device *dev)
>   			   GEN8_LQSC_RO_PERF_DIS);
>   }
>
> +static void bxt_init_clock_gating(struct drm_device *dev)
> +{
> +	gen9_init_clock_gating(dev);
> +}
> +
>   static void i915_pineview_get_mem_freq(struct drm_device *dev)
>   {
>   	struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -6503,7 +6508,12 @@ void intel_init_pm(struct drm_device *dev)
>   	if (INTEL_INFO(dev)->gen >= 9) {
>   		skl_setup_wm_latency(dev);
>
> -		dev_priv->display.init_clock_gating = skl_init_clock_gating;
> +		if (IS_BROXTON(dev))
> +			dev_priv->display.init_clock_gating =
> +				bxt_init_clock_gating;
> +		else
> +			dev_priv->display.init_clock_gating =
> +				skl_init_clock_gating;

This doesn't match the style in: "HardWare WorkAround ring 
initialisation for Broxton", where we explicitly check the IS_BROXTON 
and IS_SKYLAKE state.

>   		dev_priv->display.update_wm = skl_update_wm;
>   		dev_priv->display.update_sprite_wm = skl_update_sprite_wm;
>   	} else if (HAS_PCH_SPLIT(dev)) {
>

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Re: [PATCH 28/49] drm/i915/bxt: Define BXT power domains

[Ville Syrjälä]

On Tue, Mar 17, 2015 at 11:39:54AM +0200, Imre Deak wrote:
> From: Satheeshakrishna M <satheeshakrishna.m@intel.com>
> 
> Add BXT power domains
> 
> v2: Use DOMAIN_PLLS instead of a new CDCLK one, whitespace fixes
>     (Damien)
> v3: add VGA, TRANSCODER_A power domains (imre)
> 
> Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> (v1)
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> (v2)
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 55 +++++++++++++++++++++++++++++++++
>  1 file changed, 55 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index ce00e69..ff5cce3 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -319,6 +319,38 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv,
>  	SKL_DISPLAY_MISC_IO_POWER_DOMAINS)) |		\
>  	BIT(POWER_DOMAIN_INIT))
>  
> +#define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS (		\
> +	BIT(POWER_DOMAIN_TRANSCODER_A) |		\
> +	BIT(POWER_DOMAIN_PIPE_B) |			\
> +	BIT(POWER_DOMAIN_TRANSCODER_B) |		\
> +	BIT(POWER_DOMAIN_PIPE_C) |			\
> +	BIT(POWER_DOMAIN_TRANSCODER_C) |		\
> +	BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |		\
> +	BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |		\
> +	BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |		\
> +	BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |		\
> +	BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |		\
> +	BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |		\
> +	BIT(POWER_DOMAIN_AUX_B) |			\
> +	BIT(POWER_DOMAIN_AUX_C) |			\
> +	BIT(POWER_DOMAIN_AUDIO) |			\
> +	BIT(POWER_DOMAIN_VGA) |				\
> +	BIT(POWER_DOMAIN_INIT))
> +#define BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS (		\
> +	BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS |		\
> +	BIT(POWER_DOMAIN_PIPE_A) |			\
> +	BIT(POWER_DOMAIN_TRANSCODER_EDP) |		\
> +	BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) |		\
> +	BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) |		\
> +	BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) |		\
> +	BIT(POWER_DOMAIN_AUX_A) |			\
> +	BIT(POWER_DOMAIN_PLLS) |			\
> +	BIT(POWER_DOMAIN_INIT))
> +#define BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS (		\
> +	(POWER_DOMAIN_MASK & ~(BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS |	\
> +	BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) |	\
> +	BIT(POWER_DOMAIN_INIT))
> +
>  static void skl_set_power_well(struct drm_i915_private *dev_priv,
>  			struct i915_power_well *power_well, bool enable)
>  {
> @@ -1313,6 +1345,27 @@ static struct i915_power_well skl_power_wells[] = {
>  	},
>  };
>  
> +static struct i915_power_well bxt_power_wells[] = {
> +	{
> +		.name = "always-on",
> +		.always_on = 1,
> +		.domains = BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS,
> +		.ops = &i9xx_always_on_power_well_ops,
> +	},
> +	{
> +		.name = "power well 1",
> +		.domains = BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS,
> +		.ops = &skl_power_well_ops,
> +		.data = SKL_DISP_PW_1,
> +	},
> +	{
> +		.name = "power well 2",
> +		.domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
> +		.ops = &skl_power_well_ops,
> +		.data = SKL_DISP_PW_2,
> +	}
> +};
> +
>  #define set_power_wells(power_domains, __power_wells) ({		\
>  	(power_domains)->power_wells = (__power_wells);			\
>  	(power_domains)->power_well_count = ARRAY_SIZE(__power_wells);	\
> @@ -1341,6 +1394,8 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
>  		set_power_wells(power_domains, bdw_power_wells);
>  	} else if (IS_SKYLAKE(dev_priv->dev)) {
>  		set_power_wells(power_domains, skl_power_wells);
> +	} else if (IS_BROXTON(dev_priv->dev)) {
> +		set_power_wells(power_domains, bxt_power_wells);
>  	} else if (IS_CHERRYVIEW(dev_priv->dev)) {
>  		set_power_wells(power_domains, chv_power_wells);
>  	} else if (IS_VALLEYVIEW(dev_priv->dev)) {
> -- 
> 2.1.0
> 
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-- 
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Re: [PATCH 31/49] drm/i915/bxt: add description about the BXT PHYs

[Ville Syrjälä]

On Tue, Mar 17, 2015 at 11:39:57AM +0200, Imre Deak wrote:
> Extend the VLV/CHV DPIO (PHY) documentation with the BXT specifics.
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  Documentation/DocBook/drm.tmpl  |  4 ++--
>  drivers/gpu/drm/i915/i915_reg.h | 10 +++++++---
>  2 files changed, 9 insertions(+), 5 deletions(-)
> 
> diff --git a/Documentation/DocBook/drm.tmpl b/Documentation/DocBook/drm.tmpl
> index 7a45775..327757f 100644
> --- a/Documentation/DocBook/drm.tmpl
> +++ b/Documentation/DocBook/drm.tmpl
> @@ -4067,7 +4067,7 @@ int num_ioctls;</synopsis>
>          <title>DPIO</title>
>  !Pdrivers/gpu/drm/i915/i915_reg.h DPIO
>  	<table id="dpiox2">
> -	  <title>Dual channel PHY (VLV/CHV)</title>
> +	  <title>Dual channel PHY (VLV/CHV/BXT)</title>
>  	  <tgroup cols="8">
>  	    <colspec colname="c0" />
>  	    <colspec colname="c1" />
> @@ -4118,7 +4118,7 @@ int num_ioctls;</synopsis>
>  	  </tgroup>
>  	</table>
>  	<table id="dpiox1">
> -	  <title>Single channel PHY (CHV)</title>
> +	  <title>Single channel PHY (CHV/BXT)</title>
>  	  <tgroup cols="4">
>  	    <colspec colname="c0" />
>  	    <colspec colname="c1" />
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a3579c0..95532b4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -718,7 +718,7 @@ enum skl_disp_power_wells {
>  /**
>   * DOC: DPIO
>   *
> - * VLV and CHV have slightly peculiar display PHYs for driving DP/HDMI
> + * VLV, CHV and BXT have slightly peculiar display PHYs for driving DP/HDMI
>   * ports. DPIO is the name given to such a display PHY. These PHYs
>   * don't follow the standard programming model using direct MMIO
>   * registers, and instead their registers must be accessed trough IOSF
> @@ -773,9 +773,13 @@ enum skl_disp_power_wells {
>   *
>   * Note: digital port B is DDI0, digital port C is DDI1,
>   * digital port D is DDI2
> + *
> + * On BXT the above mappings apply for both the dual and single channel PHY,
> + * with the difference that any of the three ports can connect to any of the
> + * three pipes. Also the single channel PHY is used for port A (DDI2/EDP).

I think we might need to split the VLV/CHV vs. BXT descriptions a bit
more. The pipe->CMN/PLL/REF port->PCS/TX rule doesn't seem to hold
anymore due to the more flexible pipe<->port mapping.

So maybe something like:
"
Generally on VLV/CHV the common lane...
...
 port D == PCS/TX CH0

On BXT the entire PHY channel corresponds to the port. That means
the PLL is also now associated with the port rather than the pipe,
and so the clock needs to be routed to the appropriate transcoder.
Port A PLL is directly connected to transcoder EDP and port B/C
PLLs can be routed to any transcoder A/B/C.
"

Also maybe reverse the DDI<->port mapping note to make it simpler. Eg:

"Note: DDI0 is digital port B, DDI1 is digital port C, and
DDI2 is digital port D (CHV) or port A (BXT)."


>   */
>  /*
> - * Dual channel PHY (VLV/CHV)
> + * Dual channel PHY (VLV/CHV/BXT)
>   * ---------------------------------
>   * |      CH0      |      CH1      |
>   * |  CMN/PLL/REF  |  CMN/PLL/REF  |
> @@ -787,7 +791,7 @@ enum skl_disp_power_wells {
>   * |     DDI0      |     DDI1      | DP/HDMI ports
>   * ---------------------------------
>   *
> - * Single channel PHY (CHV)
> + * Single channel PHY (CHV/BXT)
>   * -----------------
>   * |      CH0      |
>   * |  CMN/PLL/REF  |
> -- 
> 2.1.0
> 
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Re: [PATCH 30/49] drm/i915/bxt: add display initialize/uninitialize sequence

[Ville Syrjälä]

On Tue, Mar 17, 2015 at 11:39:56AM +0200, Imre Deak wrote:
<snip>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index b91862e..ba2d1ae 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -8284,6 +8284,75 @@ void hsw_disable_pc8(struct drm_i915_private *dev_priv)
>  	intel_prepare_ddi(dev);
>  }
>  
> +static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
> +				int max_pixclk)
> +{
> +	/*
> +	 * CDclks are supported:
> +	 *   144MHz
> +	 *   288MHz
> +	 *   384MHz
> +	 *   576MHz
> +	 *   624MHz
> +	 * Check to see whether we're above 90% of the lower bin and
> +	 * adjust if needed.
> +	 */
> +
> +	/* If max_pixclk is greater than the max allowed clock, return 0.
> +	 * FIXME:- The max clock allowed needs to be provided by GOP/VBIOS
> +	 * via a scratch pad register. Till that is enabled, use 624MHz as max.
> +	 */
> +	if (max_pixclk > 624000)
> +		return 0;
> +	else if (max_pixclk > 576000*9/10)
> +		return 624000;
> +	else if (max_pixclk > 384000*9/10)
> +		return 576000;
> +	else if (max_pixclk > 288000*9/10)
> +		return 384000;
> +	else if (max_pixclk > 144000*9/10)

Does BXT really need a 10% guarband for CDCLK? Other HSW+ platforms need no
guardband IIRC (assuming we ignore 64bpp and scaling).

I'm not seeing anything specific about BXT max pixel rate in BSpec.
The SKL section says EXCLUDE(BXT). Art, can you clarify?

> +		return 288000;
> +	else
> +		return 144000;
> +}
> +

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Re: [PATCH 36/49] drm/i915/bxt: Define bxt DDI PLLs and implement enable/disable sequence

[Jesse Barnes]

On 03/17/2015 02:40 AM, Imre Deak wrote:
> +	/*
> +	 * FIXME: program PORT_PLL_9/i_lockthresh according to the latest
> +	 * specification update.
> +	 */
> +

Current spec says "write 5 to i_lockthresh", but I guess that's not
needed for functionality so it can be added later.

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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Re: [PATCH 37/49] drm/i915: factor out vlv_PLL_is_optimal

[Jesse Barnes]

On 03/17/2015 02:40 AM, Imre Deak wrote:
> Factor out the logic to decide whether the newly calculated dividers are
> better than the best found so far. Do this for clarity and to prepare
> for the upcoming BXT helper needing the same.
> 
> No functional change.
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 50 ++++++++++++++++++++++++++----------
>  1 file changed, 36 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 95ce0a8..7feb047 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -776,6 +776,33 @@ g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
>  	return found;
>  }
>  
> +/*
> + * Check if the calculated PLL configuration is more optimal compared to the
> + * best configuration and error found so far. Return the calculated error.
> + */
> +static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
> +			       const intel_clock_t *calculated_clock,
> +			       const intel_clock_t *best_clock,
> +			       unsigned int best_error_ppm,
> +			       unsigned int *error_ppm)
> +{
> +	*error_ppm = div_u64(1000000ULL *
> +				abs(target_freq - calculated_clock->dot),
> +			     target_freq);
> +	/*
> +	 * Prefer a better P value over a better (smaller) error if the error
> +	 * is small. Ensure this preference for future configurations too by
> +	 * setting the error to 0.
> +	 */
> +	if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
> +		*error_ppm = 0;
> +
> +		return true;
> +	}
> +
> +	return *error_ppm + 10 < best_error_ppm;
> +}
> +
>  static bool
>  vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
>  		   int target, int refclk, intel_clock_t *match_clock,
> @@ -800,7 +827,7 @@ vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
>  				clock.p = clock.p1 * clock.p2;
>  				/* based on hardware requirement, prefer bigger m1,m2 values */
>  				for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
> -					unsigned int ppm, diff;
> +					unsigned int ppm;
>  
>  					clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
>  								     refclk * clock.m1);
> @@ -811,20 +838,15 @@ vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
>  								&clock))
>  						continue;
>  
> -					diff = abs(clock.dot - target);
> -					ppm = div_u64(1000000ULL * diff, target);
> +					if (!vlv_PLL_is_optimal(dev, target,
> +								&clock,
> +								best_clock,
> +								bestppm, &ppm))
> +						continue;
>  
> -					if (ppm < 100 && clock.p > best_clock->p) {
> -						bestppm = 0;
> -						*best_clock = clock;
> -						found = true;
> -					}
> -
> -					if (bestppm >= 10 && ppm < bestppm - 10) {
> -						bestppm = ppm;
> -						*best_clock = clock;
> -						found = true;
> -					}
> +					*best_clock = clock;
> +					bestppm = ppm;
> +					found = true;
>  				}
>  			}
>  		}
> 

Did a double take because of the logic reversal, but I think it's correct.

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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Re: [PATCH 38/49] drm/i915: check for div-by-zero in vlv_PLL_is_optimal

[Jesse Barnes]

On 03/17/2015 02:40 AM, Imre Deak wrote:
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 7feb047..5874512 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -786,6 +786,9 @@ static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
>  			       unsigned int best_error_ppm,
>  			       unsigned int *error_ppm)
>  {
> +	if (WARN_ON_ONCE(!target_freq))
> +		return false;
> +
>  	*error_ppm = div_u64(1000000ULL *
>  				abs(target_freq - calculated_clock->dot),
>  			     target_freq);
> 

Thank you.  This one bites a lot in debug.

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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Re: [PATCH 36/49] drm/i915/bxt: Define bxt DDI PLLs and implement enable/disable sequence

[Imre Deak]

On Thu, 2015-03-19 at 13:27 -0700, Jesse Barnes wrote:
> On 03/17/2015 02:40 AM, Imre Deak wrote:
> > +	/*
> > +	 * FIXME: program PORT_PLL_9/i_lockthresh according to the latest
> > +	 * specification update.
> > +	 */
> > +
> 
> Current spec says "write 5 to i_lockthresh", but I guess that's not
> needed for functionality so it can be added later.
> 
> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

Yea, my thought was to keep things close to what we tried on the
power-on and fix things once we get the HW.

--Imre

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Re: [PATCH 39/49] drm/i915/chv: use vlv_PLL_is_optimal in chv_find_best_dpll

[Jesse Barnes]

On 03/17/2015 02:40 AM, Imre Deak wrote:
> Prepare chv_find_best_dpll to be used for BXT too, where we want to
> consider the error between target and calculated frequency too when
> choosing a better PLL configuration.
> 
> No functional change.
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 26 ++++++++++++++++++++------
>  1 file changed, 20 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 5874512..9ca84a2 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -786,6 +786,16 @@ static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
>  			       unsigned int best_error_ppm,
>  			       unsigned int *error_ppm)
>  {
> +	/*
> +	 * For CHV ignore the error and consider only the P value.
> +	 * Prefer a bigger P value based on HW requirements.
> +	 */
> +	if (IS_CHERRYVIEW(dev)) {
> +		*error_ppm = 0;
> +
> +		return calculated_clock->p > best_clock->p;
> +	}
> +
>  	if (WARN_ON_ONCE(!target_freq))
>  		return false;
>  
> @@ -864,11 +874,13 @@ chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
>  		   intel_clock_t *best_clock)
>  {
>  	struct drm_device *dev = crtc->base.dev;
> +	unsigned int best_error_ppm;
>  	intel_clock_t clock;
>  	uint64_t m2;
>  	int found = false;
>  
>  	memset(best_clock, 0, sizeof(*best_clock));
> +	best_error_ppm = 1000000;
>  
>  	/*
>  	 * Based on hardware doc, the n always set to 1, and m1 always
> @@ -882,6 +894,7 @@ chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
>  		for (clock.p2 = limit->p2.p2_fast;
>  				clock.p2 >= limit->p2.p2_slow;
>  				clock.p2 -= clock.p2 > 10 ? 2 : 1) {
> +			unsigned int error_ppm;
>  
>  			clock.p = clock.p1 * clock.p2;
>  
> @@ -898,12 +911,13 @@ chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
>  			if (!intel_PLL_is_valid(dev, limit, &clock))
>  				continue;
>  
> -			/* based on hardware requirement, prefer bigger p
> -			 */
> -			if (clock.p > best_clock->p) {
> -				*best_clock = clock;
> -				found = true;
> -			}
> +			if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
> +						best_error_ppm, &error_ppm))
> +				continue;
> +
> +			*best_clock = clock;
> +			best_error_ppm = error_ppm;
> +			found = true;
>  		}
>  	}
>  
> 

Looking at it again, maybe vlv_PLL_is_better() might be a better name.

Also, could you just make the ppm variable a scratch one and ignore it?
 It just gets set to 0 no matter what, right?

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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Re: [PATCH 40/49] drm/i915/bxt: add bxt_find_best_dpll

[Jesse Barnes]

On 03/17/2015 02:40 AM, Imre Deak wrote:
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 32 ++++++++++++++++++++++++++++----
>  drivers/gpu/drm/i915/intel_drv.h     |  2 ++
>  2 files changed, 30 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 9ca84a2..3606366 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -102,6 +102,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
>  			    const struct intel_crtc_state *pipe_config);
>  static void intel_begin_crtc_commit(struct drm_crtc *crtc);
>  static void intel_finish_crtc_commit(struct drm_crtc *crtc);
> +static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors);
>  
>  static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
>  {
> @@ -399,6 +400,18 @@ static const intel_limit_t intel_limits_chv = {
>  	.p2 = {	.p2_slow = 1, .p2_fast = 14 },
>  };
>  
> +static const intel_limit_t intel_limits_bxt = {
> +	/* FIXME: find real dot limits */
> +	.dot = { .min = 0, .max = INT_MAX },
> +	.vco = { .min = 4800000, .max = 6480000 },
> +	.n = { .min = 1, .max = 1 },
> +	.m1 = { .min = 2, .max = 2 },
> +	/* FIXME: find real m2 limits */
> +	.m2 = { .min = 2 << 22, .max = 255 << 22 },
> +	.p1 = { .min = 2, .max = 4 },
> +	.p2 = { .p2_slow = 1, .p2_fast = 20 },
> +};
> +
>  static void vlv_clock(int refclk, intel_clock_t *clock)
>  {
>  	clock->m = clock->m1 * clock->m2;
> @@ -492,7 +505,9 @@ static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
>  	struct drm_device *dev = crtc->base.dev;
>  	const intel_limit_t *limit;
>  
> -	if (HAS_PCH_SPLIT(dev))
> +	if (IS_BROXTON(dev))
> +		limit = &intel_limits_bxt;
> +	else if (HAS_PCH_SPLIT(dev))
>  		limit = intel_ironlake_limit(crtc, refclk);
>  	else if (IS_G4X(dev)) {
>  		limit = intel_g4x_limit(crtc);
> @@ -577,11 +592,11 @@ static bool intel_PLL_is_valid(struct drm_device *dev,
>  	if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
>  		INTELPllInvalid("m1 out of range\n");
>  
> -	if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
> +	if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
>  		if (clock->m1 <= clock->m2)
>  			INTELPllInvalid("m1 <= m2\n");
>  
> -	if (!IS_VALLEYVIEW(dev)) {
> +	if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
>  		if (clock->p < limit->p.min || limit->p.max < clock->p)
>  			INTELPllInvalid("p out of range\n");
>  		if (clock->m < limit->m.min || limit->m.max < clock->m)
> @@ -924,6 +939,15 @@ chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
>  	return found;
>  }
>  
> +bool bxt_find_best_dpll(struct intel_crtc *crtc, int target_clock,
> +			intel_clock_t *best_clock)
> +{
> +	int refclk = i9xx_get_refclk(crtc, 0);
> +
> +	return chv_find_best_dpll(intel_limit(crtc, refclk), crtc, target_clock,
> +				  refclk, NULL, best_clock);
> +}
> +
>  bool intel_crtc_active(struct drm_crtc *crtc)
>  {
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> @@ -5913,7 +5937,7 @@ static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	int refclk;
>  
> -	if (IS_VALLEYVIEW(dev)) {
> +	if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
>  		refclk = 100000;
>  	} else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
>  	    intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 262314b..56a5cc9 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1033,6 +1033,8 @@ int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
>  void
>  ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
>  				int dotclock);
> +bool bxt_find_best_dpll(struct intel_crtc *crtc, int target_clock,
> +			intel_clock_t *best_clock);
>  bool intel_crtc_active(struct drm_crtc *crtc);
>  void hsw_enable_ips(struct intel_crtc *crtc);
>  void hsw_disable_ips(struct intel_crtc *crtc);
> 

Do we have a JIRA on getting the final pixel clock and M2 params?  If
not, can you create one so we don't forget to add the real limits?

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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Re: [PATCH 41/49] drm/i915/bxt: BXT clock divider calculation

[Jesse Barnes]

On 03/17/2015 02:40 AM, Imre Deak wrote:
> From: Satheeshakrishna M <satheeshakrishna.m@intel.com>
> 
> Calculate and cache clock parameters. Follow bspec algorithm for HDMI.
> Use precalculated values for DisplayPort linkrates.
> 
> v2: (imre)
> - rebase against upstream crtc_state change
> - use the existing CHV based helper instead of handrolling the same
> 
> Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> (v1)
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 129 +++++++++++++++++++++++++++++++++++++++
>  1 file changed, 129 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index bbc3da5..fa4f8f4 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1204,6 +1204,132 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
>  	return true;
>  }
>  
> +/* bxt clock parameters */
> +struct bxt_clk_div {
> +	uint32_t p1;
> +	uint32_t p2;
> +	uint32_t m2_int;
> +	uint32_t m2_frac;
> +	bool m2_frac_en;
> +	uint32_t n;
> +	uint32_t prop_coef;
> +	uint32_t int_coef;
> +	uint32_t gain_ctl;
> +	uint32_t targ_cnt;
> +	uint32_t lanestagger;
> +};
> +
> +/* pre-calculated values for DP linkrates */
> +static struct bxt_clk_div bxt_dp_clk_val[7] = {
> +	/* 162 */ {4, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
> +	/* 270 */ {4, 1, 27,       0, 0, 1, 3,  8, 1, 9, 0xd},
> +	/* 540 */ {2, 1, 27,       0, 0, 1, 3,  8, 1, 9, 0x18},
> +	/* 216 */ {3, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
> +	/* 243 */ {4, 1, 24, 1258291, 1, 1, 5, 11, 2, 9, 0xd},
> +	/* 324 */ {4, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
> +	/* 432 */ {3, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0x18}
> +};
> +
> +static bool
> +bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
> +		   struct intel_crtc_state *crtc_state,
> +		   struct intel_encoder *intel_encoder,
> +		   int clock)
> +{
> +	struct intel_shared_dpll *pll;
> +	struct bxt_clk_div clk_div = {0};
> +
> +	if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
> +		intel_clock_t best_clock;
> +
> +		/* Calculate HDMI div */
> +		/*
> +		 * FIXME: tie the following calculation into
> +		 * i9xx_crtc_compute_clock
> +		 */
> +		if (!bxt_find_best_dpll(intel_crtc, clock, &best_clock)) {
> +			DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n",
> +					 clock, pipe_name(intel_crtc->pipe));
> +			return false;
> +		}
> +
> +		clk_div.p1 = best_clock.p1;
> +		clk_div.p2 = best_clock.p2;
> +		WARN_ON(best_clock.m1 != 2);
> +		clk_div.n = best_clock.n;
> +		clk_div.m2_int = best_clock.m2 >> 22;
> +		clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1);
> +		clk_div.m2_frac_en = clk_div.m2_frac != 0;
> +
> +		/* FIXME: set coef, gain, targcnt based on freq band */
> +		clk_div.prop_coef = 5;
> +		clk_div.int_coef = 11;
> +		clk_div.gain_ctl = 2;
> +		clk_div.targ_cnt = 9;
> +		if (clock > 270000)
> +			clk_div.lanestagger = 0x18;
> +		else if (clock > 135000)
> +			clk_div.lanestagger = 0x0d;
> +		else if (clock > 67000)
> +			clk_div.lanestagger = 0x07;
> +		else if (clock > 33000)
> +			clk_div.lanestagger = 0x04;
> +		else
> +			clk_div.lanestagger = 0x02;
> +	} else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
> +			intel_encoder->type == INTEL_OUTPUT_EDP) {
> +		struct drm_encoder *encoder = &intel_encoder->base;
> +		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +
> +		switch (intel_dp->link_bw) {
> +		case DP_LINK_BW_1_62:
> +			clk_div = bxt_dp_clk_val[0];
> +			break;
> +		case DP_LINK_BW_2_7:
> +			clk_div = bxt_dp_clk_val[1];
> +			break;
> +		case DP_LINK_BW_5_4:
> +			clk_div = bxt_dp_clk_val[2];
> +			break;
> +		default:
> +			clk_div = bxt_dp_clk_val[0];
> +			DRM_ERROR("Unknown link rate\n");
> +		}
> +	}
> +
> +	crtc_state->dpll_hw_state.ebb0 =
> +		PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2);
> +	crtc_state->dpll_hw_state.pll0 = clk_div.m2_int;
> +	crtc_state->dpll_hw_state.pll1 = PORT_PLL_N(clk_div.n);
> +	crtc_state->dpll_hw_state.pll2 = clk_div.m2_frac;
> +
> +	if (clk_div.m2_frac_en)
> +		crtc_state->dpll_hw_state.pll3 =
> +			PORT_PLL_M2_FRAC_ENABLE;
> +
> +	crtc_state->dpll_hw_state.pll6 =
> +		clk_div.prop_coef | PORT_PLL_INT_COEFF(clk_div.int_coef);
> +	crtc_state->dpll_hw_state.pll6 |=
> +		PORT_PLL_GAIN_CTL(clk_div.gain_ctl);
> +
> +	crtc_state->dpll_hw_state.pll8 = clk_div.targ_cnt;
> +
> +	crtc_state->dpll_hw_state.pcsdw12 =
> +		LANESTAGGER_STRAP_OVRD | clk_div.lanestagger;
> +
> +	pll = intel_get_shared_dpll(intel_crtc, crtc_state);
> +	if (pll == NULL) {
> +		DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
> +			pipe_name(intel_crtc->pipe));
> +		return false;
> +	}
> +
> +	/* shared DPLL id 0 is DPLL A */
> +	crtc_state->ddi_pll_sel = pll->id;
> +
> +	return true;
> +}
> +
>  /*
>   * Tries to find a *shared* PLL for the CRTC and store it in
>   * intel_crtc->ddi_pll_sel.
> @@ -1222,6 +1348,9 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
>  	if (IS_SKYLAKE(dev))
>  		return skl_ddi_pll_select(intel_crtc, crtc_state,
>  					  intel_encoder, clock);
> +	else if (IS_BROXTON(dev))
> +		return bxt_ddi_pll_select(intel_crtc, crtc_state,
> +					  intel_encoder, clock);
>  	else
>  		return hsw_ddi_pll_select(intel_crtc, crtc_state,
>  					  intel_encoder, clock);
> 

Should probably have a JIRA on the proper coeff etc values as well.
They're in the bspec, we just have to add the code for the frequency bands.

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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Re: [PATCH 42/49] drm/i915/bxt: Assign PLL for pipe

[Jesse Barnes]

On 03/17/2015 02:40 AM, Imre Deak wrote:
> From: Satheeshakrishna M <satheeshakrishna.m@intel.com>
> 
> Assign PLL for pipe (dependent on port attached to the pipe)
> 
> v2:
> - fix incorrect encoder vs. new_encoder check for crtc (imre)
> 
> v3:
> - warn and return error if no encoder is attached (imre)
> 
> Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> (v2)
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ddi.c     | 21 ------------------
>  drivers/gpu/drm/i915/intel_display.c | 41 ++++++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_drv.h     |  1 +
>  3 files changed, 42 insertions(+), 21 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index fa4f8f4..0a5d71e 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -491,27 +491,6 @@ intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
>  	return ret;
>  }
>  
> -static struct intel_encoder *
> -intel_ddi_get_crtc_new_encoder(struct intel_crtc *crtc)
> -{
> -	struct drm_device *dev = crtc->base.dev;
> -	struct intel_encoder *intel_encoder, *ret = NULL;
> -	int num_encoders = 0;
> -
> -	for_each_intel_encoder(dev, intel_encoder) {
> -		if (intel_encoder->new_crtc == crtc) {
> -			ret = intel_encoder;
> -			num_encoders++;
> -		}
> -	}
> -
> -	WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
> -	     pipe_name(crtc->pipe));
> -
> -	BUG_ON(ret == NULL);
> -	return ret;
> -}
> -
>  #define LC_FREQ 2700
>  #define LC_FREQ_2K U64_C(LC_FREQ * 2000)
>  
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 3606366..411bf50 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4037,6 +4037,27 @@ void intel_put_shared_dpll(struct intel_crtc *crtc)
>  	crtc->config->shared_dpll = DPLL_ID_PRIVATE;
>  }
>  
> +struct intel_encoder *
> +intel_ddi_get_crtc_new_encoder(struct intel_crtc *crtc)
> +{
> +	struct drm_device *dev = crtc->base.dev;
> +	struct intel_encoder *intel_encoder, *ret = NULL;
> +	int num_encoders = 0;
> +
> +	for_each_intel_encoder(dev, intel_encoder) {
> +		if (intel_encoder->new_crtc == crtc) {
> +			ret = intel_encoder;
> +			num_encoders++;
> +		}
> +	}
> +
> +	WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
> +	     pipe_name(crtc->pipe));
> +
> +	BUG_ON(ret == NULL);
> +	return ret;
> +}
> +
>  struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
>  						struct intel_crtc_state *crtc_state)
>  {
> @@ -4057,6 +4078,26 @@ struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
>  		goto found;
>  	}
>  
> +	if (IS_BROXTON(dev_priv->dev)) {
> +		/* PLL is attached to port in bxt */
> +		struct intel_encoder *encoder;
> +		struct intel_digital_port *intel_dig_port;
> +
> +		encoder = intel_ddi_get_crtc_new_encoder(crtc);
> +		if (WARN_ON(!encoder))
> +			return NULL;
> +
> +		intel_dig_port = enc_to_dig_port(&encoder->base);
> +		/* 1:1 mapping between ports and PLLs */
> +		i = (enum intel_dpll_id)intel_dig_port->port;
> +		pll = &dev_priv->shared_dplls[i];
> +		DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
> +			crtc->base.base.id, pll->name);
> +		WARN_ON(pll->new_config->crtc_mask);
> +
> +		goto found;
> +	}
> +
>  	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
>  		pll = &dev_priv->shared_dplls[i];
>  
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 56a5cc9..097fb85 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -991,6 +991,7 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv,
>  			bool state);
>  #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
>  #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
> +struct intel_encoder *intel_ddi_get_crtc_new_encoder(struct intel_crtc *crtc);
>  struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
>  						struct intel_crtc_state *state);
>  void intel_put_shared_dpll(struct intel_crtc *crtc);
> 

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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Re: [PATCH 43/49] drm/i915/bxt: Determine PLL attached to pipe

[Jesse Barnes]

On 03/17/2015 02:40 AM, Imre Deak wrote:
> From: Satheeshakrishna M <satheeshakrishna.m@intel.com>
> 
> Determine PLL attached to pipe (which is same as DDI PLL)
> 
> v2:
> - rebased on upstream s/crtc_config/crtc_state/ (imre)
> 
> Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> (v1)
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 24 ++++++++++++++++++++++++
>  1 file changed, 24 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 411bf50..c060496 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -8468,6 +8468,28 @@ static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
>  	return 0;
>  }
>  
> +static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
> +				enum port port,
> +				struct intel_crtc_state *pipe_config)
> +{
> +	switch (port) {
> +	case PORT_A:
> +		pipe_config->ddi_pll_sel = SKL_DPLL0;
> +		pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
> +		break;
> +	case PORT_B:
> +		pipe_config->ddi_pll_sel = SKL_DPLL1;
> +		pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
> +		break;
> +	case PORT_C:
> +		pipe_config->ddi_pll_sel = SKL_DPLL2;
> +		pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
> +		break;
> +	default:
> +		DRM_ERROR("Incorrect port type\n");
> +	}
> +}
> +
>  static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
>  				enum port port,
>  				struct intel_crtc_state *pipe_config)
> @@ -8530,6 +8552,8 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
>  
>  	if (IS_SKYLAKE(dev))
>  		skylake_get_ddi_pll(dev_priv, port, pipe_config);
> +	else if (IS_BROXTON(dev))
> +		bxt_get_ddi_pll(dev_priv, port, pipe_config);
>  	else
>  		haswell_get_ddi_pll(dev_priv, port, pipe_config);
>  
> 

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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Re: [PATCH 44/49] drm/i915/bxt: Determine programmed frequency

[Jesse Barnes]

On 03/17/2015 02:40 AM, Imre Deak wrote:
> From: Satheeshakrishna M <satheeshakrishna.m@intel.com>
> 
> Add placeholder function for calculating programmed pixel clock.
> Note: Formula to back calculate link clock from dividers not
> available currently.
> 
> v2:
> - rebased on upstream s/crtc_config/crtc_state/ change (imre)
> 
> Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> (v1)
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 30 +++++++++++++++++++++++++++++-
>  drivers/gpu/drm/i915/intel_dp.c  |  2 ++
>  2 files changed, 31 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 0a5d71e..ff62054 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -851,6 +851,32 @@ static void hsw_ddi_clock_get(struct intel_encoder *encoder,
>  		pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
>  }
>  
> +static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
> +				enum intel_dpll_id dpll)
> +{
> +	/* FIXME formula not available in bspec */
> +	return 0;
> +}
> +
> +static void bxt_ddi_clock_get(struct intel_encoder *encoder,
> +				struct intel_crtc_state *pipe_config)
> +{
> +	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> +	enum port port = intel_ddi_get_encoder_port(encoder);
> +	uint32_t dpll = port;
> +
> +	pipe_config->port_clock =
> +		bxt_calc_pll_link(dev_priv, dpll);
> +
> +	if (pipe_config->has_dp_encoder)
> +		pipe_config->base.adjusted_mode.crtc_clock =
> +			intel_dotclock_calculate(pipe_config->port_clock,
> +							&pipe_config->dp_m_n);
> +	else
> +		pipe_config->base.adjusted_mode.crtc_clock =
> +							pipe_config->port_clock;
> +}
> +
>  void intel_ddi_clock_get(struct intel_encoder *encoder,
>  			 struct intel_crtc_state *pipe_config)
>  {
> @@ -858,8 +884,10 @@ void intel_ddi_clock_get(struct intel_encoder *encoder,
>  
>  	if (INTEL_INFO(dev)->gen <= 8)
>  		hsw_ddi_clock_get(encoder, pipe_config);
> -	else
> +	else if (IS_SKYLAKE(dev))
>  		skl_ddi_clock_get(encoder, pipe_config);
> +	else if (IS_BROXTON(dev))
> +		bxt_ddi_clock_get(encoder, pipe_config);
>  }
>  
>  static void
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index ca60060..4bfbeed 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1416,6 +1416,8 @@ found:
>  
>  	if (IS_SKYLAKE(dev) && is_edp(intel_dp))
>  		skl_edp_set_pll_config(pipe_config, supported_rates[clock]);
> +	else if (IS_BROXTON(dev))
> +		/* handled in ddi */;
>  	else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
>  		hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
>  	else
> 

Another one for JIRA.  Looks like the formulas are in there now:
Actual Output = M2 * 400 / (P1 * P2)  // Actual differs from desired due
to limited M2 fractional precision

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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Re: [PATCH 45/49] drm/i915: suppress false PLL state warnings on non-GMCH platforms

[Jesse Barnes]

On 03/17/2015 02:40 AM, Imre Deak wrote:
> The checks for PLL enabled state on CPU ports are valid only on GMCH
> platforms but atm we'd also call them on non-PCH-split/non-GMCH
> platforms like BXT, triggering false warnings. Until the proper check is
> implented for these platforms simply disable the check.
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index c060496..ff26752 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2099,7 +2099,7 @@ static void intel_enable_pipe(struct intel_crtc *crtc)
>  	 * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
>  	 * need the check.
>  	 */
> -	if (!HAS_PCH_SPLIT(dev_priv->dev))
> +	if (HAS_GMCH_DISPLAY(dev_priv->dev))
>  		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
>  			assert_dsi_pll_enabled(dev_priv);
>  		else
> @@ -4376,7 +4376,7 @@ static void intel_crtc_load_lut(struct drm_crtc *crtc)
>  	if (!crtc->state->enable || !intel_crtc->active)
>  		return;
>  
> -	if (!HAS_PCH_SPLIT(dev_priv->dev)) {
> +	if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
>  		if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
>  			assert_dsi_pll_enabled(dev_priv);
>  		else
> 

It looks like we're doing dsi calls, so this must at least apply to BYT,
right?  We might need more granularity here...

Jesse
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Re: [PATCH 39/49] drm/i915/chv: use vlv_PLL_is_optimal in chv_find_best_dpll

[Imre Deak]

On Thu, 2015-03-19 at 13:34 -0700, Jesse Barnes wrote:
> On 03/17/2015 02:40 AM, Imre Deak wrote:
> > Prepare chv_find_best_dpll to be used for BXT too, where we want to
> > consider the error between target and calculated frequency too when
> > choosing a better PLL configuration.
> > 
> > No functional change.
> > 
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_display.c | 26 ++++++++++++++++++++------
> >  1 file changed, 20 insertions(+), 6 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 5874512..9ca84a2 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -786,6 +786,16 @@ static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
> >  			       unsigned int best_error_ppm,
> >  			       unsigned int *error_ppm)
> >  {
> > +	/*
> > +	 * For CHV ignore the error and consider only the P value.
> > +	 * Prefer a bigger P value based on HW requirements.
> > +	 */
> > +	if (IS_CHERRYVIEW(dev)) {
> > +		*error_ppm = 0;
> > +
> > +		return calculated_clock->p > best_clock->p;
> > +	}
> > +
> >  	if (WARN_ON_ONCE(!target_freq))
> >  		return false;
> >  
> > @@ -864,11 +874,13 @@ chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
> >  		   intel_clock_t *best_clock)
> >  {
> >  	struct drm_device *dev = crtc->base.dev;
> > +	unsigned int best_error_ppm;
> >  	intel_clock_t clock;
> >  	uint64_t m2;
> >  	int found = false;
> >  
> >  	memset(best_clock, 0, sizeof(*best_clock));
> > +	best_error_ppm = 1000000;
> >  
> >  	/*
> >  	 * Based on hardware doc, the n always set to 1, and m1 always
> > @@ -882,6 +894,7 @@ chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
> >  		for (clock.p2 = limit->p2.p2_fast;
> >  				clock.p2 >= limit->p2.p2_slow;
> >  				clock.p2 -= clock.p2 > 10 ? 2 : 1) {
> > +			unsigned int error_ppm;
> >  
> >  			clock.p = clock.p1 * clock.p2;
> >  
> > @@ -898,12 +911,13 @@ chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
> >  			if (!intel_PLL_is_valid(dev, limit, &clock))
> >  				continue;
> >  
> > -			/* based on hardware requirement, prefer bigger p
> > -			 */
> > -			if (clock.p > best_clock->p) {
> > -				*best_clock = clock;
> > -				found = true;
> > -			}
> > +			if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
> > +						best_error_ppm, &error_ppm))
> > +				continue;
> > +
> > +			*best_clock = clock;
> > +			best_error_ppm = error_ppm;
> > +			found = true;
> >  		}
> >  	}
> >  
> > 
> 
> Looking at it again, maybe vlv_PLL_is_better() might be a better name.

Ok, will change it.

> Also, could you just make the ppm variable a scratch one and ignore it?
>  It just gets set to 0 no matter what, right?

For CHV yes. But the next patch takes the same function into use in BXT
too, where error_ppm will be set to the actual error, the same way as on
VLV.

> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>


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Re: [PATCH 39/49] drm/i915/chv: use vlv_PLL_is_optimal in chv_find_best_dpll

[Jesse Barnes]

On 03/19/2015 01:55 PM, Imre Deak wrote:
> On Thu, 2015-03-19 at 13:34 -0700, Jesse Barnes wrote:
>> On 03/17/2015 02:40 AM, Imre Deak wrote:
>>> Prepare chv_find_best_dpll to be used for BXT too, where we want to
>>> consider the error between target and calculated frequency too when
>>> choosing a better PLL configuration.
>>>
>>> No functional change.
>>>
>>> Signed-off-by: Imre Deak <imre.deak@intel.com>
>>> ---
>>>  drivers/gpu/drm/i915/intel_display.c | 26 ++++++++++++++++++++------
>>>  1 file changed, 20 insertions(+), 6 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>>> index 5874512..9ca84a2 100644
>>> --- a/drivers/gpu/drm/i915/intel_display.c
>>> +++ b/drivers/gpu/drm/i915/intel_display.c
>>> @@ -786,6 +786,16 @@ static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
>>>  			       unsigned int best_error_ppm,
>>>  			       unsigned int *error_ppm)
>>>  {
>>> +	/*
>>> +	 * For CHV ignore the error and consider only the P value.
>>> +	 * Prefer a bigger P value based on HW requirements.
>>> +	 */
>>> +	if (IS_CHERRYVIEW(dev)) {
>>> +		*error_ppm = 0;
>>> +
>>> +		return calculated_clock->p > best_clock->p;
>>> +	}
>>> +
>>>  	if (WARN_ON_ONCE(!target_freq))
>>>  		return false;
>>>  
>>> @@ -864,11 +874,13 @@ chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
>>>  		   intel_clock_t *best_clock)
>>>  {
>>>  	struct drm_device *dev = crtc->base.dev;
>>> +	unsigned int best_error_ppm;
>>>  	intel_clock_t clock;
>>>  	uint64_t m2;
>>>  	int found = false;
>>>  
>>>  	memset(best_clock, 0, sizeof(*best_clock));
>>> +	best_error_ppm = 1000000;
>>>  
>>>  	/*
>>>  	 * Based on hardware doc, the n always set to 1, and m1 always
>>> @@ -882,6 +894,7 @@ chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
>>>  		for (clock.p2 = limit->p2.p2_fast;
>>>  				clock.p2 >= limit->p2.p2_slow;
>>>  				clock.p2 -= clock.p2 > 10 ? 2 : 1) {
>>> +			unsigned int error_ppm;
>>>  
>>>  			clock.p = clock.p1 * clock.p2;
>>>  
>>> @@ -898,12 +911,13 @@ chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
>>>  			if (!intel_PLL_is_valid(dev, limit, &clock))
>>>  				continue;
>>>  
>>> -			/* based on hardware requirement, prefer bigger p
>>> -			 */
>>> -			if (clock.p > best_clock->p) {
>>> -				*best_clock = clock;
>>> -				found = true;
>>> -			}
>>> +			if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
>>> +						best_error_ppm, &error_ppm))
>>> +				continue;
>>> +
>>> +			*best_clock = clock;
>>> +			best_error_ppm = error_ppm;
>>> +			found = true;
>>>  		}
>>>  	}
>>>  
>>>
>>
>> Looking at it again, maybe vlv_PLL_is_better() might be a better name.
> 
> Ok, will change it.
> 
>> Also, could you just make the ppm variable a scratch one and ignore it?
>>  It just gets set to 0 no matter what, right?
> 
> For CHV yes. But the next patch takes the same function into use in BXT
> too, where error_ppm will be set to the actual error, the same way as on
> VLV.

Oh right it's a patch *series*.  Ignore the noise. :)

The rename is optional too; I just had to think about it when I saw
>>> +		return calculated_clock->p > best_clock->p;
since in that case we're really checking whether the new calculated p
value is better (higher) than the last one.  The _is_optimal() name made
me think it should be >= or something.  But it's not a big deal.

Thanks,
Jesse
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Re: [PATCH 45/49] drm/i915: suppress false PLL state warnings on non-GMCH platforms

[Imre Deak]

On Thu, 2015-03-19 at 13:53 -0700, Jesse Barnes wrote:
> On 03/17/2015 02:40 AM, Imre Deak wrote:
> > The checks for PLL enabled state on CPU ports are valid only on GMCH
> > platforms but atm we'd also call them on non-PCH-split/non-GMCH
> > platforms like BXT, triggering false warnings. Until the proper check is
> > implented for these platforms simply disable the check.
> > 
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_display.c | 4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index c060496..ff26752 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -2099,7 +2099,7 @@ static void intel_enable_pipe(struct intel_crtc *crtc)
> >  	 * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
> >  	 * need the check.
> >  	 */
> > -	if (!HAS_PCH_SPLIT(dev_priv->dev))
> > +	if (HAS_GMCH_DISPLAY(dev_priv->dev))
> >  		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
> >  			assert_dsi_pll_enabled(dev_priv);
> >  		else
> > @@ -4376,7 +4376,7 @@ static void intel_crtc_load_lut(struct drm_crtc *crtc)
> >  	if (!crtc->state->enable || !intel_crtc->active)
> >  		return;
> >  
> > -	if (!HAS_PCH_SPLIT(dev_priv->dev)) {
> > +	if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
> >  		if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
> >  			assert_dsi_pll_enabled(dev_priv);
> >  		else
> > 
> 
> It looks like we're doing dsi calls, so this must at least apply to BYT,
> right?  We might need more granularity here...

Yea, but VLV is covered by the GMCH check.

> 
> Jesse


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Re: [PATCH 45/49] drm/i915: suppress false PLL state warnings on non-GMCH platforms

[Jesse Barnes]

On 03/19/2015 01:57 PM, Imre Deak wrote:
> On Thu, 2015-03-19 at 13:53 -0700, Jesse Barnes wrote:
>> On 03/17/2015 02:40 AM, Imre Deak wrote:
>>> The checks for PLL enabled state on CPU ports are valid only on GMCH
>>> platforms but atm we'd also call them on non-PCH-split/non-GMCH
>>> platforms like BXT, triggering false warnings. Until the proper check is
>>> implented for these platforms simply disable the check.
>>>
>>> Signed-off-by: Imre Deak <imre.deak@intel.com>
>>> ---
>>>  drivers/gpu/drm/i915/intel_display.c | 4 ++--
>>>  1 file changed, 2 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>>> index c060496..ff26752 100644
>>> --- a/drivers/gpu/drm/i915/intel_display.c
>>> +++ b/drivers/gpu/drm/i915/intel_display.c
>>> @@ -2099,7 +2099,7 @@ static void intel_enable_pipe(struct intel_crtc *crtc)
>>>  	 * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
>>>  	 * need the check.
>>>  	 */
>>> -	if (!HAS_PCH_SPLIT(dev_priv->dev))
>>> +	if (HAS_GMCH_DISPLAY(dev_priv->dev))
>>>  		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
>>>  			assert_dsi_pll_enabled(dev_priv);
>>>  		else
>>> @@ -4376,7 +4376,7 @@ static void intel_crtc_load_lut(struct drm_crtc *crtc)
>>>  	if (!crtc->state->enable || !intel_crtc->active)
>>>  		return;
>>>  
>>> -	if (!HAS_PCH_SPLIT(dev_priv->dev)) {
>>> +	if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
>>>  		if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
>>>  			assert_dsi_pll_enabled(dev_priv);
>>>  		else
>>>
>>
>> It looks like we're doing dsi calls, so this must at least apply to BYT,
>> right?  We might need more granularity here...
> 
> Yea, but VLV is covered by the GMCH check.

Ah ok, in that case it's fine.

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

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Re: [PATCH 16/49] drm/i915/bxt: add WaDisableMaskBasedCammingInRCC workaround

[Nick Hoath]

On 17/03/2015 09:39, Imre Deak wrote:
> From: Ben Widawsky <benjamin.widawsky@intel.com>
>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_reg.h         | 4 ++++
>   drivers/gpu/drm/i915/intel_ringbuffer.c | 9 +++++++++
>   2 files changed, 13 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b7ba061..1d074e8 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5346,6 +5346,10 @@ enum skl_disp_power_wells {
>   #define  HDC_FORCE_NON_COHERENT			(1<<4)
>   #define  HDC_BARRIER_PERFORMANCE_DISABLE	(1<<10)
>
> +/* GEN9 chicken */
> +#define SLICE_ECO_CHICKEN0			0x7308
> +#define   PIXEL_MASK_CAMMING_DISABLE		(1 << 14)
> +
>   /* WaCatErrorRejectionIssue */
>   #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		0x9030
>   #define  GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB	(1<<11)
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index abe062a..e23cbdc 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -966,6 +966,15 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
>   	WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
>   			  GEN9_CCS_TLB_PREFETCH_ENABLE);
>
> +	/*
> +	 * FIXME: don't apply the following on BXT for stepping C. On BXT A0
> +	 * the flag reads back as 0.
> +	 */

I've just posted a patch with the stepping macros. You can use these in 
the same way as for Skylake.

> +	/* WaDisableMaskBasedCammingInRCC:bxtA */
> +	if (IS_BROXTON(dev))
> +		WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
> +				  PIXEL_MASK_CAMMING_DISABLE);
> +
>   	return 0;
>   }
>
>

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Re: [PATCH 17/49] drm/i915/skl: add WaDisableMaskBasedCammingInRCC workaround

[Nick Hoath]

On 17/03/2015 09:39, Imre Deak wrote:
> From: Ben Widawsky <benjamin.widawsky@intel.com>
>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_ringbuffer.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index e23cbdc..000f608 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -970,8 +970,8 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
>   	 * FIXME: don't apply the following on BXT for stepping C. On BXT A0
>   	 * the flag reads back as 0.
>   	 */
> -	/* WaDisableMaskBasedCammingInRCC:bxtA */
> -	if (IS_BROXTON(dev))
> +	/* WaDisableMaskBasedCammingInRCC:sklC,bxtA */
> +	if (INTEL_REVID(dev) == SKL_REVID_C0 || IS_BROXTON(dev))
This looks wrong. (IS_BROXTON && BXT_REVID_C0) || (IS_SKYLAKE && 
SKL_REVID_C0) please.
>   		WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
>   				  PIXEL_MASK_CAMMING_DISABLE);
>
>

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Re: [PATCH 14/49] drm/i915/bxt: add GEN8_SDEUNIT_CLOCK_GATE_DISABLE workaround

[Nick Hoath]

On 17/03/2015 13:06, Imre Deak wrote:
> On ti, 2015-03-17 at 11:35 +0100, Daniel Vetter wrote:
>> On Tue, Mar 17, 2015 at 11:39:40AM +0200, Imre Deak wrote:
>>> Signed-off-by: Imre Deak <imre.deak@intel.com>
>>> ---
>>>   drivers/gpu/drm/i915/intel_pm.c | 11 +++++++++++
>>>   1 file changed, 11 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>>> index 3d4a7c3..d5dd0b3 100644
>>> --- a/drivers/gpu/drm/i915/intel_pm.c
>>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>>> @@ -96,7 +96,18 @@ static void skl_init_clock_gating(struct drm_device *dev)
>>>
>>>   static void bxt_init_clock_gating(struct drm_device *dev)
>>>   {
>>> +	struct drm_i915_private *dev_priv = dev->dev_private;
>>> +
>>>   	gen9_init_clock_gating(dev);
>>> +
>>> +	/*
>>> +	 * FIXME:
>>> +	 * GEN8_SDEUNIT_CLOCK_GATE_DISABLE applies on A0 only.
>>
>> We have pci revid macros now. Do you have plans to roll similar ones out
>> for bxt?
>
> Yes. It may be that for BXT we also need to look at the PCI_REVISION_ID
> field besides PCI_CLASS_REVISION, I still have to figure out the exact
> mapping. (And also understand the meaning/difference between SOC vs. GT
> revision IDs).

I've posted a patch with the Broxton revision ID's from the specs.

>
> --Imre
>
> _______________________________________________
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> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>

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Re: [PATCH 38/49] drm/i915: check for div-by-zero in vlv_PLL_is_optimal

[Daniel Vetter]

On Thu, Mar 19, 2015 at 01:31:44PM -0700, Jesse Barnes wrote:
> On 03/17/2015 02:40 AM, Imre Deak wrote:
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_display.c | 3 +++
> >  1 file changed, 3 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 7feb047..5874512 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -786,6 +786,9 @@ static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
> >  			       unsigned int best_error_ppm,
> >  			       unsigned int *error_ppm)
> >  {
> > +	if (WARN_ON_ONCE(!target_freq))
> > +		return false;
> > +
> >  	*error_ppm = div_u64(1000000ULL *
> >  				abs(target_freq - calculated_clock->dot),
> >  			     target_freq);
> > 
> 
> Thank you.  This one bites a lot in debug.
> 
> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

I went ahead and merged these 2 prep patches to dinq right away.

Thanks, Daniel
-- 
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Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [PATCH 39/49] drm/i915/chv: use vlv_PLL_is_optimal in chv_find_best_dpll

[Daniel Vetter]

On Thu, Mar 19, 2015 at 01:34:49PM -0700, Jesse Barnes wrote:
> On 03/17/2015 02:40 AM, Imre Deak wrote:
> > Prepare chv_find_best_dpll to be used for BXT too, where we want to
> > consider the error between target and calculated frequency too when
> > choosing a better PLL configuration.
> > 
> > No functional change.
> > 
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_display.c | 26 ++++++++++++++++++++------
> >  1 file changed, 20 insertions(+), 6 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 5874512..9ca84a2 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -786,6 +786,16 @@ static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
> >  			       unsigned int best_error_ppm,
> >  			       unsigned int *error_ppm)
> >  {
> > +	/*
> > +	 * For CHV ignore the error and consider only the P value.
> > +	 * Prefer a bigger P value based on HW requirements.
> > +	 */
> > +	if (IS_CHERRYVIEW(dev)) {
> > +		*error_ppm = 0;
> > +
> > +		return calculated_clock->p > best_clock->p;
> > +	}
> > +
> >  	if (WARN_ON_ONCE(!target_freq))
> >  		return false;
> >  
> > @@ -864,11 +874,13 @@ chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
> >  		   intel_clock_t *best_clock)
> >  {
> >  	struct drm_device *dev = crtc->base.dev;
> > +	unsigned int best_error_ppm;
> >  	intel_clock_t clock;
> >  	uint64_t m2;
> >  	int found = false;
> >  
> >  	memset(best_clock, 0, sizeof(*best_clock));
> > +	best_error_ppm = 1000000;
> >  
> >  	/*
> >  	 * Based on hardware doc, the n always set to 1, and m1 always
> > @@ -882,6 +894,7 @@ chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
> >  		for (clock.p2 = limit->p2.p2_fast;
> >  				clock.p2 >= limit->p2.p2_slow;
> >  				clock.p2 -= clock.p2 > 10 ? 2 : 1) {
> > +			unsigned int error_ppm;
> >  
> >  			clock.p = clock.p1 * clock.p2;
> >  
> > @@ -898,12 +911,13 @@ chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
> >  			if (!intel_PLL_is_valid(dev, limit, &clock))
> >  				continue;
> >  
> > -			/* based on hardware requirement, prefer bigger p
> > -			 */
> > -			if (clock.p > best_clock->p) {
> > -				*best_clock = clock;
> > -				found = true;
> > -			}
> > +			if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
> > +						best_error_ppm, &error_ppm))
> > +				continue;
> > +
> > +			*best_clock = clock;
> > +			best_error_ppm = error_ppm;
> > +			found = true;
> >  		}
> >  	}
> >  
> > 
> 
> Looking at it again, maybe vlv_PLL_is_better() might be a better name.
> 
> Also, could you just make the ppm variable a scratch one and ignore it?
>  It just gets set to 0 no matter what, right?
> 
> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

Also merged to dinq. If there's other refactorings to existing platform
code then I need to get that in in the next few days for it to make the
4.1 cutoff. Otherwise we can't pull the usual "separate branch&late pull"
trick for new platforms.

Thanks, Daniel
-- 
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Re: [PATCH 13/49] drm/i915/bxt: add bxt_init_clock_gating

[Imre Deak]

On Thu, 2015-03-19 at 16:50 +0000, Nick Hoath wrote:
> On 17/03/2015 09:39, Imre Deak wrote:
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> >   drivers/gpu/drm/i915/intel_pm.c | 12 +++++++++++-
> >   1 file changed, 11 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index b89ab4d..3d4a7c3 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -94,6 +94,11 @@ static void skl_init_clock_gating(struct drm_device *dev)
> >   			   GEN8_LQSC_RO_PERF_DIS);
> >   }
> >
> > +static void bxt_init_clock_gating(struct drm_device *dev)
> > +{
> > +	gen9_init_clock_gating(dev);
> > +}
> > +
> >   static void i915_pineview_get_mem_freq(struct drm_device *dev)
> >   {
> >   	struct drm_i915_private *dev_priv = dev->dev_private;
> > @@ -6503,7 +6508,12 @@ void intel_init_pm(struct drm_device *dev)
> >   	if (INTEL_INFO(dev)->gen >= 9) {
> >   		skl_setup_wm_latency(dev);
> >
> > -		dev_priv->display.init_clock_gating = skl_init_clock_gating;
> > +		if (IS_BROXTON(dev))
> > +			dev_priv->display.init_clock_gating =
> > +				bxt_init_clock_gating;
> > +		else
> > +			dev_priv->display.init_clock_gating =
> > +				skl_init_clock_gating;
> 
> This doesn't match the style in: "HardWare WorkAround ring 
> initialisation for Broxton", where we explicitly check the IS_BROXTON 
> and IS_SKYLAKE state.

Ok, will fix this to set skl_init_clock_gating only for IS_SKYLAKE.


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Re: [PATCH 16/49] drm/i915/bxt: add WaDisableMaskBasedCammingInRCC workaround

[Imre Deak]

On Fri, 2015-03-20 at 09:05 +0000, Nick Hoath wrote:
> On 17/03/2015 09:39, Imre Deak wrote:
> > From: Ben Widawsky <benjamin.widawsky@intel.com>
> >
> > Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> >   drivers/gpu/drm/i915/i915_reg.h         | 4 ++++
> >   drivers/gpu/drm/i915/intel_ringbuffer.c | 9 +++++++++
> >   2 files changed, 13 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index b7ba061..1d074e8 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -5346,6 +5346,10 @@ enum skl_disp_power_wells {
> >   #define  HDC_FORCE_NON_COHERENT			(1<<4)
> >   #define  HDC_BARRIER_PERFORMANCE_DISABLE	(1<<10)
> >
> > +/* GEN9 chicken */
> > +#define SLICE_ECO_CHICKEN0			0x7308
> > +#define   PIXEL_MASK_CAMMING_DISABLE		(1 << 14)
> > +
> >   /* WaCatErrorRejectionIssue */
> >   #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		0x9030
> >   #define  GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB	(1<<11)
> > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > index abe062a..e23cbdc 100644
> > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > @@ -966,6 +966,15 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
> >   	WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
> >   			  GEN9_CCS_TLB_PREFETCH_ENABLE);
> >
> > +	/*
> > +	 * FIXME: don't apply the following on BXT for stepping C. On BXT A0
> > +	 * the flag reads back as 0.
> > +	 */
> 
> I've just posted a patch with the stepping macros. You can use these in 
> the same way as for Skylake.

I'm not so happy to make these changes at this point. Without them we
still have a correct - even if conservative - behavior on other
steppings. There are quite a few places marked with FIXME that need
improvement in a similar way and I'd leave them as-is for now to keep as
close as possible to the good known working state (as of the power-on)
and to make merging of this initial patchset fast.

> 
> > +	/* WaDisableMaskBasedCammingInRCC:bxtA */
> > +	if (IS_BROXTON(dev))
> > +		WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
> > +				  PIXEL_MASK_CAMMING_DISABLE);
> > +
> >   	return 0;
> >   }
> >
> >
> 


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Re: [PATCH 17/49] drm/i915/skl: add WaDisableMaskBasedCammingInRCC workaround

[Imre Deak]

On Fri, 2015-03-20 at 09:07 +0000, Nick Hoath wrote:
> On 17/03/2015 09:39, Imre Deak wrote:
> > From: Ben Widawsky <benjamin.widawsky@intel.com>
> >
> > Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> >   drivers/gpu/drm/i915/intel_ringbuffer.c | 4 ++--
> >   1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > index e23cbdc..000f608 100644
> > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > @@ -970,8 +970,8 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
> >   	 * FIXME: don't apply the following on BXT for stepping C. On BXT A0
> >   	 * the flag reads back as 0.
> >   	 */
> > -	/* WaDisableMaskBasedCammingInRCC:bxtA */
> > -	if (IS_BROXTON(dev))
> > +	/* WaDisableMaskBasedCammingInRCC:sklC,bxtA */
> > +	if (INTEL_REVID(dev) == SKL_REVID_C0 || IS_BROXTON(dev))
> This looks wrong. (IS_BROXTON && BXT_REVID_C0) || (IS_SKYLAKE && 
> SKL_REVID_C0) please.

It's correct though. gen9_init_workarounds() is called for Skylake or
Broxton, so the condition is true either on Broxton regardless of the
stepping, or on Skylake if the revid matches.

Also on Broxton we have to _exclude_ the workaround on C0, so if we add
the revid check for Broxton too, then we have to rewrite the condition
to:

(IS_BROXTON && INTEL_REVID != BXT_REVID_C0) || (IS_SKYLAKE &&
INTEL_REVID == SKL_REVID_C0)

> >   		WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
> >   				  PIXEL_MASK_CAMMING_DISABLE);
> >
> >
> 


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Re: [PATCH 14/49] drm/i915/bxt: add GEN8_SDEUNIT_CLOCK_GATE_DISABLE workaround

[Imre Deak]

On Fri, 2015-03-20 at 09:08 +0000, Nick Hoath wrote:
> On 17/03/2015 13:06, Imre Deak wrote:
> > On ti, 2015-03-17 at 11:35 +0100, Daniel Vetter wrote:
> >> On Tue, Mar 17, 2015 at 11:39:40AM +0200, Imre Deak wrote:
> >>> Signed-off-by: Imre Deak <imre.deak@intel.com>
> >>> ---
> >>>   drivers/gpu/drm/i915/intel_pm.c | 11 +++++++++++
> >>>   1 file changed, 11 insertions(+)
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> >>> index 3d4a7c3..d5dd0b3 100644
> >>> --- a/drivers/gpu/drm/i915/intel_pm.c
> >>> +++ b/drivers/gpu/drm/i915/intel_pm.c
> >>> @@ -96,7 +96,18 @@ static void skl_init_clock_gating(struct drm_device *dev)
> >>>
> >>>   static void bxt_init_clock_gating(struct drm_device *dev)
> >>>   {
> >>> +	struct drm_i915_private *dev_priv = dev->dev_private;
> >>> +
> >>>   	gen9_init_clock_gating(dev);
> >>> +
> >>> +	/*
> >>> +	 * FIXME:
> >>> +	 * GEN8_SDEUNIT_CLOCK_GATE_DISABLE applies on A0 only.
> >>
> >> We have pci revid macros now. Do you have plans to roll similar ones out
> >> for bxt?
> >
> > Yes. It may be that for BXT we also need to look at the PCI_REVISION_ID
> > field besides PCI_CLASS_REVISION, I still have to figure out the exact
> > mapping. (And also understand the meaning/difference between SOC vs. GT
> > revision IDs).

Ok, the above is red herring. PCI_REVISION_ID is just the 8 low bits of
PCI_CLASS_REVISION, so we can reuse INTEL_REVID as-is.

> I've posted a patch with the Broxton revision ID's from the specs.

It looks ok, but I prefer adding them as a follow-up to this patchset.


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Re: [PATCH 30/49] drm/i915/bxt: add display initialize/uninitialize sequence

[Ville Syrjälä]

On Tue, Mar 17, 2015 at 11:39:56AM +0200, Imre Deak wrote:
> From: Vandana Kannan <vandana.kannan@intel.com>
> 
> Add display clock/PHY initialization sequence as per BSpec.

This should really be two patches I think. I'll go over the cdclk bits
first...

> 
> Until GOP/VBIOS provides an upper limit value for CDCLK, comparing clock
> value with 624 MHz and returning 0 in case it exceeds.
> 
> Note that the CD clock and PHY initialization/uninitialization are done
> at their current place only for simplicity, in a future patch - when more
> of the runtime PM features will be enabled - these will be moved to
> power well#1 and modeset encoder enabling/disabling hooks respectively.
> This also means that atm dynamic power gating power well #2 is
> effectively disabled.
> 
> v1: Added function definitions in header files
> v2: Imre's review comments addressed
> - Moved CDCLK related definitions to i915_reg.h
> - Removed defintions for CDCLK frequency
> - Split uninit_cdclk() by adding a phy_uninit function
> - Calculate freq and decimal based on input frequency
> - Program SSA precharge based on input frequency
> - Use wait_for 1ms instead 200us udelay for DE PLL locking
> - Removed initial value for divider, freq, decimal, ratio.
> - Replaced polling loops with wait_for
> - Parameterized latency optim setting
> - Fix the parts where DE PLL has to be disabled.
> - Call CDCLK selection from mode set
> 
> v3: (imre)
> - add note about the plan to move the cdclk/phy init to a better place
> - take rps.hw_lock around pcode access
> - fix DDI PHY timeout value
> - squash in Vandana's "PORT_CL2CM_DW6_A BUN fix",
>   "DDI PHY programming register defn", "Do ddi_phy_init always",
>   "Check CDCLK upper limit" patches
> - move PHY register macros next to the corresponding CHV/VLV macros
> - move DE PLL register macros here from another patch since they are
>   used here first
> - add BXT_ prefix to CDCLK flags
> - s/COMMON_RESET/COMMON_RESET_DIS/ and clarify related code comments
> - fix incorrect read value for the RMW of BXT_PHY_CTL_FAMILY_DDI
> - fix using GT_DISPLAY_EDP_POWER_ON vs. GT_DISPLAY_DDI_POWER_ON
>   when powering on DDI ports
> - fix incorrect port when setting BXT_PORT_TX_DW14_LN for DDI ports
> - add missing masking when programming CDCLK_FREQ_DECIMAL
> - add missing powering on for DDI-C port, rename OCL2_LDOFUSE_PWR_EN
>   to OCL2_LDOFUSE_PWR_DIS to reduce confusion
> - add note about mismatch with bspec in the PORT_REF_DW6 fields
> - factor out PHY init code to a new function, so we can call it for
>   PHY_A and PHY_BC, instead of open-coding the same
> 
> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> (v2)
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h      | 126 +++++++++++++++
>  drivers/gpu/drm/i915/intel_ddi.c     | 291 +++++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_display.c |  75 +++++++++
>  drivers/gpu/drm/i915/intel_drv.h     |   4 +
>  4 files changed, 496 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b4474d3..a3579c0 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
<snip>
> @@ -5326,6 +5430,9 @@ enum skl_disp_power_wells {
>  #define  DISP_FBC_WM_DIS		(1<<15)
>  #define DISP_ARB_CTL2	0x45004
>  #define  DISP_DATA_PARTITION_5_6	(1<<6)
> +#define DBUF_CTL	0x45008
> +#define  DBUF_POWER_REQUEST		(1<<31)
> +#define  DBUF_POWER_STATE		(1<<30)
>  #define GEN7_MSG_CTL	0x45010
>  #define  WAIT_FOR_PCH_RESET_ACK		(1<<1)
>  #define  WAIT_FOR_PCH_FLR_ACK		(1<<0)
> @@ -6271,6 +6378,7 @@ enum skl_disp_power_wells {
>  #define   GEN6_PCODE_WRITE_D_COMP		0x11
>  #define   GEN6_ENCODE_RC6_VID(mv)		(((mv) - 245) / 5)
>  #define   GEN6_DECODE_RC6_VID(vids)		(((vids) * 5) + 245)
> +#define   DISPLAY_PCU_CONTROL			0x17

I called this HSW_PCODE_DE_WRITE_FREQ_REQ in my HSW/BDW cdclk
patches, which matches the name in Bspec for HSW/BDW.

Given our established practice of naming things based on the oldest
platform supporting them, I'd go with the HSW/BDW name.

>  #define   DISPLAY_IPS_CONTROL			0x19
>  #define	  HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL	0x1A
>  #define GEN6_PCODE_DATA				0x138128
> @@ -6748,6 +6856,13 @@ enum skl_disp_power_wells {
>  #define  CDCLK_FREQ_675_617		(3<<26)
>  #define  CDCLK_FREQ_DECIMAL_MASK	(0x7ff)
>  
> +#define  BXT_CDCLK_CD2X_DIV_SEL_MASK	(3<<22)
> +#define  BXT_CDCLK_CD2X_DIV_SEL_1	(0<<22)
> +#define  BXT_CDCLK_CD2X_DIV_SEL_1_5	(1<<22)
> +#define  BXT_CDCLK_CD2X_DIV_SEL_2	(2<<22)
> +#define  BXT_CDCLK_CD2X_DIV_SEL_4	(3<<22)
> +#define  BXT_CDCLK_SSA_PRECHARGE_ENABLE	(1<<16)
> +
>  /* LCPLL_CTL */
>  #define LCPLL1_CTL		0x46010
>  #define LCPLL2_CTL		0x46014
> @@ -6812,6 +6927,17 @@ enum skl_disp_power_wells {
>  #define GET_CFG_CR1_REG(id) (DPLL1_CFGCR1 + (id - SKL_DPLL1) * 8)
>  #define GET_CFG_CR2_REG(id) (DPLL1_CFGCR2 + (id - SKL_DPLL1) * 8)
>  
> +/* BXT display engine PLL */
> +#define BXT_DE_PLL_CTL			0x6d000
> +#define   BXT_DE_PLL_RATIO_1152		0x3c
> +#define   BXT_DE_PLL_RATIO_1248		0x41
> +#define   BXT_DE_PLL_RATIO_DEFAULT	0x64

These are just 60,65,100 decimal in hex. So I might make this
something like:
#define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */

> +#define   BXT_DE_PLL_RATIO_MASK		0x7f

0xff

> +
> +#define BXT_DE_PLL_ENABLE		0x46070
> +#define   BXT_DE_PLL_PLL_ENABLE		(1 << 31)
> +#define   BXT_DE_PLL_LOCK		(1 << 30)
> +
>  /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
>   * since on HSW we can't write to it using I915_WRITE. */
>  #define D_COMP_HSW			(MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index a203d9d..789682d 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1957,6 +1957,294 @@ static void skl_shared_dplls_init(struct drm_i915_private *dev_priv)
<snip>
> +
> +/*
> + * It is the responsibility of the caller to ensure that
> + * criteria for changing the CD clk frequency is met.

Not sure that note helps anything. It applies to all platforms anyway,
not just BXT.

> + *
> + * This function only changes CD clock frequency.
> + * TODO:- 1. Add functions to change only the divider and
> + *	  2. call impacted functions like backlight, WiDi, watermark.

This TODO can be dropped. We'll do all that stuff naturally as part of
the crtc enable, so nothing needed here I think.

> +*/
> +void bxt_select_cdclk_freq(struct drm_device *dev, u32 frequency)

We call it foo_set_cdclk() on other platforms. Also we usually use just
a plain old int for most frequency variables.

Also I'd put the code into intel_display.c as that's where we have the
rest of the cdclk stuff, and that's where I was going to put the HSW/BDW
code too.

If people are into that code movement stuff someone could extract all the
cdclk stuff to some new file to reduce intel_display.c a bit.

> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	uint32_t cdclk_ctl, decimal, ratio;
> +	uint32_t divider, freq, current_freq;
> +	int ret;
> +
> +	freq = (frequency / 1000 - 1) * 2;

This will lose <1MHz bits. So rewrite as

(frequency - 1000) / 500
or
((frequency - 1000) << 1) / 1000
if you want to advertize the .1 fixed point fact a bit more.

or maybe
frequency / 500 - (1 << 1)
or
(frequency << 1) / 1000 - (1 << 1)

> +	decimal = DIV_ROUND_UP(frequency, 25000);

I'd call this pcu_freq or somesuch. 'decimal' doesn't really
make much sense.

> +
> +	switch (frequency) {
> +	case 144000:
> +		divider = BXT_CDCLK_CD2X_DIV_SEL_4;
> +		ratio = BXT_DE_PLL_RATIO_1152;
> +		break;
> +	case 288000:
> +		divider = BXT_CDCLK_CD2X_DIV_SEL_2;
> +		ratio = BXT_DE_PLL_RATIO_1152;
> +		break;
> +	case 384000:
> +		divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
> +		ratio = BXT_DE_PLL_RATIO_1152;
> +		break;
> +	case 576000:
> +		divider = BXT_CDCLK_CD2X_DIV_SEL_1;
> +		ratio = BXT_DE_PLL_RATIO_1152;
> +		break;
> +	case 624000:
> +		divider = BXT_CDCLK_CD2X_DIV_SEL_1;
> +		ratio = BXT_DE_PLL_RATIO_1248;
> +		break;
> +	case 0:
> +		/* Incase incoming frequency is 0, only DE PLL has to be
> +		 * disabled, divider/ratio need not be programmed.
> +		 * Hence, initializing to 0.
> +		 */
> +		divider = ratio = 0;
> +		break;
> +	default:
> +		DRM_ERROR("Unsupported cd frequency %d enable request",
> +								frequency);
> +		return;
> +	}
> +
> +	current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
> +	current_freq = ((current_freq / 2) + 1) * 1000;

Again we lose <1MHz bits here.

> +
> +	mutex_lock(&dev_priv->rps.hw_lock);
> +	/* Inform power controller of upcoming frequency change */
> +	ret = sandybridge_pcode_write(dev_priv, DISPLAY_PCU_CONTROL,
> +				      0x80000000);

I can't see any name for the magic value in Bspec. So I guess we'll
leave it as is.

> +	mutex_unlock(&dev_priv->rps.hw_lock);
> +
> +	if (ret) {
> +		DRM_DEBUG_KMS("pcode write failed, leaving CDCLK unchanged (%d)\n",
> +			      ret);

Sounds like DRM_ERROR() would be in order.

> +		return;
> +	}
> +
> +	/* DE PLL has to be disabled when input frequency is 0 or
> +	 * frequency is to be changed to 624MHz or changed from 624 MHz
> +	 */
> +	if (!frequency || current_freq == 624000 || frequency == 624000) {
> +		I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
> +		WARN(wait_for(
> +			!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
> +			1), "DE PLL locked\n");

DRM_ERROR() might be enough here. The backtrace won't give is much more
information I think. Maybe add a note that the timeout required is
at least 200us.

> +	}
> +
> +	if (frequency) {
> +		I915_WRITE(BXT_DE_PLL_CTL, ratio);

The spec says we must not change the other fields in the register, so
perhaps we should do an RMW here? Although the default is documented to
be 0 for everything else, but maybe that could change on some devices.

> +		I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
> +		WARN(wait_for(
> +			I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1),
> +			"DE PLL not locked\n");

Again, not sure the WARN buys us anything extra. Again might mention
that the timeout required is 200us.

> +
> +		cdclk_ctl = I915_READ(CDCLK_CTL);
> +		cdclk_ctl &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
> +		cdclk_ctl |= divider;
> +
> +		/* Disable SSA Precharge when CD clock frequency < 500 MHz,
> +		 * enable otherwise.
> +		 */
> +		cdclk_ctl &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
> +		if (frequency >= 500000)
> +			cdclk_ctl |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
> +
> +		cdclk_ctl &= ~CDCLK_FREQ_DECIMAL_MASK;
> +		cdclk_ctl |= freq;
> +		I915_WRITE(CDCLK_CTL, cdclk_ctl);
> +
> +		mutex_lock(&dev_priv->rps.hw_lock);
> +		ret = sandybridge_pcode_write(dev_priv, DISPLAY_PCU_CONTROL,
> +					      decimal);
> +		mutex_unlock(&dev_priv->rps.hw_lock);
> +
> +		if (ret) {
> +			DRM_DEBUG_KMS("pcode write failed. err = %d decimal = %d\n",
> +				      ret, decimal);

The debug message could be a bit more descriptive of what we were trying
to do here.

> +			return;
> +		}
> +
> +		dev_priv->cdclk_freq = frequency;
> +	} else {
> +		mutex_lock(&dev_priv->rps.hw_lock);
> +		ret = sandybridge_pcode_write(dev_priv, DISPLAY_PCU_CONTROL, 1);
> +		mutex_unlock(&dev_priv->rps.hw_lock);
> +
> +		if (ret)
> +			DRM_DEBUG_KMS("pcode write failed. err = %d decimal = 1\n",
> +				      ret);
> +	}

Looks like we could avoid the duplicated pcode write easily. Also the
spec says that cdclk will actually be 19.2MHz with DE PLL disabled. So
seems like we should use that instead of 0 as the value all around.

If we want to keep the set_cdclk(0) as a handy shorthand for "disable
the DE PLL" we could then have
if (frequency == 0)
	frequency = 19200;
at the start of the function.

> +}
> +
> +void bxt_init_cdclk(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +
> +	/* NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
> +	 * or else the reset will hang because there is no PCH to respond.
> +	 * Move the handshake programming to initialization sequence.
> +	 * Previously was left up to BIOS.
> +	 */
> +	u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
> +
> +	temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
> +	I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
> +
> +	/* Enable PG1 for cdclk */
> +	intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
> +
> +	/* check if cd clock is enabled */
> +	if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
> +		DRM_DEBUG_KMS("Display already initialized\n");
> +		return;
> +	}
> +
> +	/* FIXME:- The initial CDCLK needs to be read from VBT.
> +	 * Need to make this change after VBT has changes for BXT.
> +	 */
> +	bxt_select_cdclk_freq(dev, 624000);

Do we need to initialize this here? It would get initialized at the
first modeset anyway. Or is there some problem with AUX/something
with the low 19.2MHz cdclk we'd have w/o DE PLL?

> +
> +	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
> +	udelay(10);
> +
> +	if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
> +		DRM_ERROR("DBuf power enable timeout!\n");
> +}
> +
> +void bxt_uninit_cdclk(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +
> +	bxt_ddi_phy_uninit(dev);
> +
> +	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
> +	udelay(10);
> +
> +	if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
> +		DRM_ERROR("DBuf power disable timeout!\n");
> +
> +	bxt_select_cdclk_freq(dev, 0);
> +
> +	intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
> +}
> +
>  void intel_ddi_pll_init(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -1973,6 +2261,9 @@ void intel_ddi_pll_init(struct drm_device *dev)
>  	if (IS_SKYLAKE(dev)) {
>  		if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
>  			DRM_ERROR("LCPLL1 is disabled\n");
> +	} else if (IS_BROXTON(dev)) {
> +		bxt_init_cdclk(dev);
> +		bxt_ddi_phy_init(dev);
>  	} else {
>  		/*
>  		 * The LCPLL register should be turned on by the BIOS. For now
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index b91862e..ba2d1ae 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -8284,6 +8284,75 @@ void hsw_disable_pc8(struct drm_i915_private *dev_priv)
>  	intel_prepare_ddi(dev);
>  }
>  
> +static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
> +				int max_pixclk)
> +{
> +	/*
> +	 * CDclks are supported:
> +	 *   144MHz
> +	 *   288MHz
> +	 *   384MHz
> +	 *   576MHz
> +	 *   624MHz
> +	 * Check to see whether we're above 90% of the lower bin and
> +	 * adjust if needed.
> +	 */
> +
> +	/* If max_pixclk is greater than the max allowed clock, return 0.
> +	 * FIXME:- The max clock allowed needs to be provided by GOP/VBIOS
> +	 * via a scratch pad register. Till that is enabled, use 624MHz as max.
> +	 */
> +	if (max_pixclk > 624000)
> +		return 0;

I think we can just ignore the max limit for now. That's what we do for
VLV/CHV. Once we get my cdclk series in we'll have max_cdclk and can
check such limits on all platforms, and in the apprpriate place where we
can still fail the operation / reject the mode.

This will avoid having the !req_cdclk special cases below.

> +	else if (max_pixclk > 576000*9/10)
> +		return 624000;
> +	else if (max_pixclk > 384000*9/10)
> +		return 576000;
> +	else if (max_pixclk > 288000*9/10)
> +		return 384000;
> +	else if (max_pixclk > 144000*9/10)
> +		return 288000;

Art confirmed that we don't need any guardband here, so the 9/10 factor
should be removed, and the comment adjusted.

> +	else
> +		return 144000;

Can we drop to DE PLL disabled/19.2MHz when there are no active pipes?
If so we should add such check here. So something like:
...
else if (max_pixclk > 0)
	return 144000;
else
	return 19200;

> +}
> +
> +static void broxton_modeset_global_pipes(struct drm_device *dev,
> +					    unsigned *prepare_pipes)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct intel_crtc *intel_crtc;
> +	int max_pixclk = intel_mode_max_pixclk(dev_priv);
> +	int req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
> +
> +	if (!req_cdclk) {
> +		DRM_ERROR("CDCLK exceeds maximum allowable value\n");
> +		return;
> +	}
> +
> +	if (req_cdclk == dev_priv->cdclk_freq)
> +		return;
> +
> +	/* disable/enable all currently active pipes while we change cdclk */
> +	for_each_intel_crtc(dev, intel_crtc)
> +		if (intel_crtc->base.enabled)
> +			*prepare_pipes |= (1 << intel_crtc->pipe);
> +}

Might make sense to combine this with the VLV/CHV function so that
we don't have to add essentially duplicated blocks of code in
__intel_set_mode().

> +
> +static void broxton_modeset_global_resources(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	int max_pixclk = intel_mode_max_pixclk(dev_priv);
> +	int req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
> +
> +	if (!req_cdclk) {
> +		DRM_ERROR("CDCLK exceeds maximum allowable value\n");
> +		return;
> +	}
> +
> +	if (req_cdclk != dev_priv->cdclk_freq)
> +		bxt_select_cdclk_freq(dev, req_cdclk);
> +}
> +
>  static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
>  				      struct intel_crtc_state *crtc_state)
>  {
> @@ -11239,6 +11308,9 @@ static int __intel_set_mode(struct drm_crtc *crtc,
>  
>  		/* may have added more to prepare_pipes than we should */
>  		prepare_pipes &= ~disable_pipes;
> +	} else if (IS_BROXTON(dev)) {
> +		broxton_modeset_global_pipes(dev, &prepare_pipes);
> +		prepare_pipes &= ~disable_pipes;
>  	}
>  
>  	ret = __intel_set_mode_setup_plls(dev, modeset_pipes, disable_pipes);
> @@ -13133,6 +13205,9 @@ static void intel_init_display(struct drm_device *dev)
>  	} else if (IS_VALLEYVIEW(dev)) {
>  		dev_priv->display.modeset_global_resources =
>  			valleyview_modeset_global_resources;
> +	} else if (IS_BROXTON(dev)) {
> +		dev_priv->display.modeset_global_resources =
> +			broxton_modeset_global_resources;
>  	}
>  
>  	switch (INTEL_INFO(dev)->gen) {
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index c77128c..4bc2041 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -873,6 +873,7 @@ void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
>  void intel_ddi_clock_get(struct intel_encoder *encoder,
>  			 struct intel_crtc_state *pipe_config);
>  void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
> +void bxt_select_cdclk_freq(struct drm_device *dev, u32 frequency);
>  
>  /* intel_frontbuffer.c */
>  void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
> @@ -1020,6 +1021,9 @@ void intel_prepare_reset(struct drm_device *dev);
>  void intel_finish_reset(struct drm_device *dev);
>  void hsw_enable_pc8(struct drm_i915_private *dev_priv);
>  void hsw_disable_pc8(struct drm_i915_private *dev_priv);
> +void bxt_init_cdclk(struct drm_device *dev);
> +void bxt_uninit_cdclk(struct drm_device *dev);
> +void bxt_ddi_phy_init(struct drm_device *dev);
>  void intel_dp_get_m_n(struct intel_crtc *crtc,
>  		      struct intel_crtc_state *pipe_config);
>  void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
> -- 
> 2.1.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
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Re: [PATCH 30/49] drm/i915/bxt: add display initialize/uninitialize sequence

[Imre Deak]

On Fri, 2015-03-20 at 16:10 +0200, Ville Syrjälä wrote:
> On Tue, Mar 17, 2015 at 11:39:56AM +0200, Imre Deak wrote:
> > From: Vandana Kannan <vandana.kannan@intel.com>
> > 
> > Add display clock/PHY initialization sequence as per BSpec.
> 
> This should really be two patches I think. I'll go over the cdclk bits
> first...

Yes, that would've been a better split. Other patches again like the
related register definitions needed to be squashed.
 
> > Until GOP/VBIOS provides an upper limit value for CDCLK, comparing clock
> > value with 624 MHz and returning 0 in case it exceeds.
> > 
> > Note that the CD clock and PHY initialization/uninitialization are done
> > at their current place only for simplicity, in a future patch - when more
> > of the runtime PM features will be enabled - these will be moved to
> > power well#1 and modeset encoder enabling/disabling hooks respectively.
> > This also means that atm dynamic power gating power well #2 is
> > effectively disabled.
> > 
> > v1: Added function definitions in header files
> > v2: Imre's review comments addressed
> > - Moved CDCLK related definitions to i915_reg.h
> > - Removed defintions for CDCLK frequency
> > - Split uninit_cdclk() by adding a phy_uninit function
> > - Calculate freq and decimal based on input frequency
> > - Program SSA precharge based on input frequency
> > - Use wait_for 1ms instead 200us udelay for DE PLL locking
> > - Removed initial value for divider, freq, decimal, ratio.
> > - Replaced polling loops with wait_for
> > - Parameterized latency optim setting
> > - Fix the parts where DE PLL has to be disabled.
> > - Call CDCLK selection from mode set
> > 
> > v3: (imre)
> > - add note about the plan to move the cdclk/phy init to a better place
> > - take rps.hw_lock around pcode access
> > - fix DDI PHY timeout value
> > - squash in Vandana's "PORT_CL2CM_DW6_A BUN fix",
> >   "DDI PHY programming register defn", "Do ddi_phy_init always",
> >   "Check CDCLK upper limit" patches
> > - move PHY register macros next to the corresponding CHV/VLV macros
> > - move DE PLL register macros here from another patch since they are
> >   used here first
> > - add BXT_ prefix to CDCLK flags
> > - s/COMMON_RESET/COMMON_RESET_DIS/ and clarify related code comments
> > - fix incorrect read value for the RMW of BXT_PHY_CTL_FAMILY_DDI
> > - fix using GT_DISPLAY_EDP_POWER_ON vs. GT_DISPLAY_DDI_POWER_ON
> >   when powering on DDI ports
> > - fix incorrect port when setting BXT_PORT_TX_DW14_LN for DDI ports
> > - add missing masking when programming CDCLK_FREQ_DECIMAL
> > - add missing powering on for DDI-C port, rename OCL2_LDOFUSE_PWR_EN
> >   to OCL2_LDOFUSE_PWR_DIS to reduce confusion
> > - add note about mismatch with bspec in the PORT_REF_DW6 fields
> > - factor out PHY init code to a new function, so we can call it for
> >   PHY_A and PHY_BC, instead of open-coding the same
> > 
> > Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> (v2)
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h      | 126 +++++++++++++++
> >  drivers/gpu/drm/i915/intel_ddi.c     | 291 +++++++++++++++++++++++++++++++++++
> >  drivers/gpu/drm/i915/intel_display.c |  75 +++++++++
> >  drivers/gpu/drm/i915/intel_drv.h     |   4 +
> >  4 files changed, 496 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index b4474d3..a3579c0 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> <snip>
> > @@ -5326,6 +5430,9 @@ enum skl_disp_power_wells {
> >  #define  DISP_FBC_WM_DIS		(1<<15)
> >  #define DISP_ARB_CTL2	0x45004
> >  #define  DISP_DATA_PARTITION_5_6	(1<<6)
> > +#define DBUF_CTL	0x45008
> > +#define  DBUF_POWER_REQUEST		(1<<31)
> > +#define  DBUF_POWER_STATE		(1<<30)
> >  #define GEN7_MSG_CTL	0x45010
> >  #define  WAIT_FOR_PCH_RESET_ACK		(1<<1)
> >  #define  WAIT_FOR_PCH_FLR_ACK		(1<<0)
> > @@ -6271,6 +6378,7 @@ enum skl_disp_power_wells {
> >  #define   GEN6_PCODE_WRITE_D_COMP		0x11
> >  #define   GEN6_ENCODE_RC6_VID(mv)		(((mv) - 245) / 5)
> >  #define   GEN6_DECODE_RC6_VID(vids)		(((vids) * 5) + 245)
> > +#define   DISPLAY_PCU_CONTROL			0x17
> 
> I called this HSW_PCODE_DE_WRITE_FREQ_REQ in my HSW/BDW cdclk
> patches, which matches the name in Bspec for HSW/BDW.
>
> Given our established practice of naming things based on the oldest
> platform supporting them, I'd go with the HSW/BDW name.

Ok, will change it.

> 
> >  #define   DISPLAY_IPS_CONTROL			0x19
> >  #define	  HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL	0x1A
> >  #define GEN6_PCODE_DATA				0x138128
> > @@ -6748,6 +6856,13 @@ enum skl_disp_power_wells {
> >  #define  CDCLK_FREQ_675_617		(3<<26)
> >  #define  CDCLK_FREQ_DECIMAL_MASK	(0x7ff)
> >  
> > +#define  BXT_CDCLK_CD2X_DIV_SEL_MASK	(3<<22)
> > +#define  BXT_CDCLK_CD2X_DIV_SEL_1	(0<<22)
> > +#define  BXT_CDCLK_CD2X_DIV_SEL_1_5	(1<<22)
> > +#define  BXT_CDCLK_CD2X_DIV_SEL_2	(2<<22)
> > +#define  BXT_CDCLK_CD2X_DIV_SEL_4	(3<<22)
> > +#define  BXT_CDCLK_SSA_PRECHARGE_ENABLE	(1<<16)
> > +
> >  /* LCPLL_CTL */
> >  #define LCPLL1_CTL		0x46010
> >  #define LCPLL2_CTL		0x46014
> > @@ -6812,6 +6927,17 @@ enum skl_disp_power_wells {
> >  #define GET_CFG_CR1_REG(id) (DPLL1_CFGCR1 + (id - SKL_DPLL1) * 8)
> >  #define GET_CFG_CR2_REG(id) (DPLL1_CFGCR2 + (id - SKL_DPLL1) * 8)
> >  
> > +/* BXT display engine PLL */
> > +#define BXT_DE_PLL_CTL			0x6d000
> > +#define   BXT_DE_PLL_RATIO_1152		0x3c
> > +#define   BXT_DE_PLL_RATIO_1248		0x41
> > +#define   BXT_DE_PLL_RATIO_DEFAULT	0x64
> 
> These are just 60,65,100 decimal in hex. So I might make this
> something like:
> #define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */

Makes sense.

> > +#define   BXT_DE_PLL_RATIO_MASK		0x7f
> 
> 0xff

Oops, this wasn't used fortunately, but with your RMW change it will
be.

> > +
> > +#define BXT_DE_PLL_ENABLE		0x46070
> > +#define   BXT_DE_PLL_PLL_ENABLE		(1 << 31)
> > +#define   BXT_DE_PLL_LOCK		(1 << 30)
> > +
> >  /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
> >   * since on HSW we can't write to it using I915_WRITE. */
> >  #define D_COMP_HSW			(MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> > index a203d9d..789682d 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -1957,6 +1957,294 @@ static void skl_shared_dplls_init(struct drm_i915_private *dev_priv)
> <snip>
> > +
> > +/*
> > + * It is the responsibility of the caller to ensure that
> > + * criteria for changing the CD clk frequency is met.
> 
> Not sure that note helps anything. It applies to all platforms anyway,
> not just BXT.
> 
> > + *
> > + * This function only changes CD clock frequency.
> > + * TODO:- 1. Add functions to change only the divider and
> > + *	  2. call impacted functions like backlight, WiDi, watermark.
> 
> This TODO can be dropped. We'll do all that stuff naturally as part of
> the crtc enable, so nothing needed here I think.
> 
> > +*/

Ok, will remove this comment block.

> > +void bxt_select_cdclk_freq(struct drm_device *dev, u32 frequency)
> 
> We call it foo_set_cdclk() on other platforms. Also we usually use just
> a plain old int for most frequency variables.
> 
> Also I'd put the code into intel_display.c as that's where we have the
> rest of the cdclk stuff, and that's where I was going to put the HSW/BDW
> code too.

Ok, will rename/move stuff.

> 
> If people are into that code movement stuff someone could extract all the
> cdclk stuff to some new file to reduce intel_display.c a bit.
> 
> > +{
> > +	struct drm_i915_private *dev_priv = dev->dev_private;
> > +	uint32_t cdclk_ctl, decimal, ratio;
> > +	uint32_t divider, freq, current_freq;
> > +	int ret;
> > +
> > +	freq = (frequency / 1000 - 1) * 2;
> 
> This will lose <1MHz bits. So rewrite as
> 
> (frequency - 1000) / 500
> or
> ((frequency - 1000) << 1) / 1000
> if you want to advertize the .1 fixed point fact a bit more.
> 
> or maybe
> frequency / 500 - (1 << 1)
> or
> (frequency << 1) / 1000 - (1 << 1)

Right, but on Broxton all supported frequencies programmed via CDCLK_CTL
are MHz aligned so the above wouldn't change things in practice. But I
guess it makes sense to rewrite this if you want to unify more the
different platforms in the future.

> > +	decimal = DIV_ROUND_UP(frequency, 25000);
> 
> I'd call this pcu_freq or somesuch. 'decimal' doesn't really
> make much sense.

Ok, will use pcu_freq.

> > +
> > +	switch (frequency) {
> > +	case 144000:
> > +		divider = BXT_CDCLK_CD2X_DIV_SEL_4;
> > +		ratio = BXT_DE_PLL_RATIO_1152;
> > +		break;
> > +	case 288000:
> > +		divider = BXT_CDCLK_CD2X_DIV_SEL_2;
> > +		ratio = BXT_DE_PLL_RATIO_1152;
> > +		break;
> > +	case 384000:
> > +		divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
> > +		ratio = BXT_DE_PLL_RATIO_1152;
> > +		break;
> > +	case 576000:
> > +		divider = BXT_CDCLK_CD2X_DIV_SEL_1;
> > +		ratio = BXT_DE_PLL_RATIO_1152;
> > +		break;
> > +	case 624000:
> > +		divider = BXT_CDCLK_CD2X_DIV_SEL_1;
> > +		ratio = BXT_DE_PLL_RATIO_1248;
> > +		break;
> > +	case 0:
> > +		/* Incase incoming frequency is 0, only DE PLL has to be
> > +		 * disabled, divider/ratio need not be programmed.
> > +		 * Hence, initializing to 0.
> > +		 */
> > +		divider = ratio = 0;
> > +		break;
> > +	default:
> > +		DRM_ERROR("Unsupported cd frequency %d enable request",
> > +								frequency);
> > +		return;
> > +	}
> > +
> > +	current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
> > +	current_freq = ((current_freq / 2) + 1) * 1000;
> 
> Again we lose <1MHz bits here.

Yep, but not in practice.

> > +
> > +	mutex_lock(&dev_priv->rps.hw_lock);
> > +	/* Inform power controller of upcoming frequency change */
> > +	ret = sandybridge_pcode_write(dev_priv, DISPLAY_PCU_CONTROL,
> > +				      0x80000000);
> 
> I can't see any name for the magic value in Bspec. So I guess we'll
> leave it as is.

I haven't found any description either.

> 
> > +	mutex_unlock(&dev_priv->rps.hw_lock);
> > +
> > +	if (ret) {
> > +		DRM_DEBUG_KMS("pcode write failed, leaving CDCLK unchanged (%d)\n",
> > +			      ret);
> 
> Sounds like DRM_ERROR() would be in order.

Ok for this and the other DRM_ERROR/WARN changes.

> 
> > +		return;
> > +	}
> > +
> > +	/* DE PLL has to be disabled when input frequency is 0 or
> > +	 * frequency is to be changed to 624MHz or changed from 624 MHz
> > +	 */
> > +	if (!frequency || current_freq == 624000 || frequency == 624000) {
> > +		I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
> > +		WARN(wait_for(
> > +			!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
> > +			1), "DE PLL locked\n");
> 
> DRM_ERROR() might be enough here. The backtrace won't give is much more
> information I think. Maybe add a note that the timeout required is
> at least 200us.
> 
> > +	}
> > +
> > +	if (frequency) {
> > +		I915_WRITE(BXT_DE_PLL_CTL, ratio);
> 
> The spec says we must not change the other fields in the register, so
> perhaps we should do an RMW here? Although the default is documented to
> be 0 for everything else, but maybe that could change on some devices.

Yea, it's better to do RMW.

> > +		I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
> > +		WARN(wait_for(
> > +			I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1),
> > +			"DE PLL not locked\n");
> 
> Again, not sure the WARN buys us anything extra. Again might mention
> that the timeout required is 200us.
> 
> > +
> > +		cdclk_ctl = I915_READ(CDCLK_CTL);
> > +		cdclk_ctl &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
> > +		cdclk_ctl |= divider;
> > +
> > +		/* Disable SSA Precharge when CD clock frequency < 500 MHz,
> > +		 * enable otherwise.
> > +		 */
> > +		cdclk_ctl &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
> > +		if (frequency >= 500000)
> > +			cdclk_ctl |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
> > +
> > +		cdclk_ctl &= ~CDCLK_FREQ_DECIMAL_MASK;
> > +		cdclk_ctl |= freq;
> > +		I915_WRITE(CDCLK_CTL, cdclk_ctl);
> > +
> > +		mutex_lock(&dev_priv->rps.hw_lock);
> > +		ret = sandybridge_pcode_write(dev_priv, DISPLAY_PCU_CONTROL,
> > +					      decimal);
> > +		mutex_unlock(&dev_priv->rps.hw_lock);
> > +
> > +		if (ret) {
> > +			DRM_DEBUG_KMS("pcode write failed. err = %d decimal = %d\n",
> > +				      ret, decimal);
> 
> The debug message could be a bit more descriptive of what we were trying
> to do here.
> 
> > +			return;
> > +		}
> > +
> > +		dev_priv->cdclk_freq = frequency;
> > +	} else {
> > +		mutex_lock(&dev_priv->rps.hw_lock);
> > +		ret = sandybridge_pcode_write(dev_priv, DISPLAY_PCU_CONTROL, 1);
> > +		mutex_unlock(&dev_priv->rps.hw_lock);
> > +
> > +		if (ret)
> > +			DRM_DEBUG_KMS("pcode write failed. err = %d decimal = 1\n",
> > +				      ret);
> > +	}
> 
> Looks like we could avoid the duplicated pcode write easily. Also the
> spec says that cdclk will actually be 19.2MHz with DE PLL disabled. So
> seems like we should use that instead of 0 as the value all around.
> 
> If we want to keep the set_cdclk(0) as a handy shorthand for "disable
> the DE PLL" we could then have
> if (frequency == 0)
> 	frequency = 19200;
> at the start of the function.

Yes, it simplifies the code, I can rewrite it.

> > +}
> > +
> > +void bxt_init_cdclk(struct drm_device *dev)
> > +{
> > +	struct drm_i915_private *dev_priv = dev->dev_private;
> > +
> > +	/* NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
> > +	 * or else the reset will hang because there is no PCH to respond.
> > +	 * Move the handshake programming to initialization sequence.
> > +	 * Previously was left up to BIOS.
> > +	 */
> > +	u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
> > +
> > +	temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
> > +	I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
> > +
> > +	/* Enable PG1 for cdclk */
> > +	intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
> > +
> > +	/* check if cd clock is enabled */
> > +	if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
> > +		DRM_DEBUG_KMS("Display already initialized\n");
> > +		return;
> > +	}
> > +
> > +	/* FIXME:- The initial CDCLK needs to be read from VBT.
> > +	 * Need to make this change after VBT has changes for BXT.
> > +	 */
> > +	bxt_select_cdclk_freq(dev, 624000);
> 
> Do we need to initialize this here? It would get initialized at the
> first modeset anyway. Or is there some problem with AUX/something
> with the low 19.2MHz cdclk we'd have w/o DE PLL?

This is required by the "Broxton Sequences to Initialize Display" in
bspec, without specifying the actual clock rate. This whole sequence is
done now during driver loading which is not ideal and should be moved to
power well enable/modesetting time, but I thought we would do it once we
get the HW to test things on.

> > +
> > +	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
> > +	udelay(10);
> > +
> > +	if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
> > +		DRM_ERROR("DBuf power enable timeout!\n");
> > +}
> > +
> > +void bxt_uninit_cdclk(struct drm_device *dev)
> > +{
> > +	struct drm_i915_private *dev_priv = dev->dev_private;
> > +
> > +	bxt_ddi_phy_uninit(dev);
> > +
> > +	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
> > +	udelay(10);
> > +
> > +	if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
> > +		DRM_ERROR("DBuf power disable timeout!\n");
> > +
> > +	bxt_select_cdclk_freq(dev, 0);
> > +
> > +	intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
> > +}
> > +
> >  void intel_ddi_pll_init(struct drm_device *dev)
> >  {
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> > @@ -1973,6 +2261,9 @@ void intel_ddi_pll_init(struct drm_device *dev)
> >  	if (IS_SKYLAKE(dev)) {
> >  		if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
> >  			DRM_ERROR("LCPLL1 is disabled\n");
> > +	} else if (IS_BROXTON(dev)) {
> > +		bxt_init_cdclk(dev);
> > +		bxt_ddi_phy_init(dev);
> >  	} else {
> >  		/*
> >  		 * The LCPLL register should be turned on by the BIOS. For now
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index b91862e..ba2d1ae 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -8284,6 +8284,75 @@ void hsw_disable_pc8(struct drm_i915_private *dev_priv)
> >  	intel_prepare_ddi(dev);
> >  }
> >  
> > +static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
> > +				int max_pixclk)
> > +{
> > +	/*
> > +	 * CDclks are supported:
> > +	 *   144MHz
> > +	 *   288MHz
> > +	 *   384MHz
> > +	 *   576MHz
> > +	 *   624MHz
> > +	 * Check to see whether we're above 90% of the lower bin and
> > +	 * adjust if needed.
> > +	 */
> > +
> > +	/* If max_pixclk is greater than the max allowed clock, return 0.
> > +	 * FIXME:- The max clock allowed needs to be provided by GOP/VBIOS
> > +	 * via a scratch pad register. Till that is enabled, use 624MHz as max.
> > +	 */
> > +	if (max_pixclk > 624000)
> > +		return 0;
> 
> I think we can just ignore the max limit for now. That's what we do for
> VLV/CHV. Once we get my cdclk series in we'll have max_cdclk and can
> check such limits on all platforms, and in the apprpriate place where we
> can still fail the operation / reject the mode.
> 
> This will avoid having the !req_cdclk special cases below.

Ok, will remove the check.

> 
> > +	else if (max_pixclk > 576000*9/10)
> > +		return 624000;
> > +	else if (max_pixclk > 384000*9/10)
> > +		return 576000;
> > +	else if (max_pixclk > 288000*9/10)
> > +		return 384000;
> > +	else if (max_pixclk > 144000*9/10)
> > +		return 288000;
> 
> Art confirmed that we don't need any guardband here, so the 9/10 factor
> should be removed, and the comment adjusted.

Thanks for catching this. Again I'd fix this up once we can test it and
for now just add a note here.

> > +	else
> > +		return 144000;
> 
> Can we drop to DE PLL disabled/19.2MHz when there are no active pipes?
> If so we should add such check here. So something like:
> ...
> else if (max_pixclk > 0)
> 	return 144000;
> else
> 	return 19200;

Yea, makes sense to disable the PLL here. Again I'd add a note for now
and fix it up later. 

> 
> > +}
> > +
> > +static void broxton_modeset_global_pipes(struct drm_device *dev,
> > +					    unsigned *prepare_pipes)
> > +{
> > +	struct drm_i915_private *dev_priv = dev->dev_private;
> > +	struct intel_crtc *intel_crtc;
> > +	int max_pixclk = intel_mode_max_pixclk(dev_priv);
> > +	int req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
> > +
> > +	if (!req_cdclk) {
> > +		DRM_ERROR("CDCLK exceeds maximum allowable value\n");
> > +		return;
> > +	}
> > +
> > +	if (req_cdclk == dev_priv->cdclk_freq)
> > +		return;
> > +
> > +	/* disable/enable all currently active pipes while we change cdclk */
> > +	for_each_intel_crtc(dev, intel_crtc)
> > +		if (intel_crtc->base.enabled)
> > +			*prepare_pipes |= (1 << intel_crtc->pipe);
> > +}
> 
> Might make sense to combine this with the VLV/CHV function so that
> we don't have to add essentially duplicated blocks of code in
> __intel_set_mode().

Ok, will do.

> > +
> > +static void broxton_modeset_global_resources(struct drm_device *dev)
> > +{
> > +	struct drm_i915_private *dev_priv = dev->dev_private;
> > +	int max_pixclk = intel_mode_max_pixclk(dev_priv);
> > +	int req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
> > +
> > +	if (!req_cdclk) {
> > +		DRM_ERROR("CDCLK exceeds maximum allowable value\n");
> > +		return;
> > +	}
> > +
> > +	if (req_cdclk != dev_priv->cdclk_freq)
> > +		bxt_select_cdclk_freq(dev, req_cdclk);
> > +}
> > +
> >  static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
> >  				      struct intel_crtc_state *crtc_state)
> >  {
> > @@ -11239,6 +11308,9 @@ static int __intel_set_mode(struct drm_crtc *crtc,
> >  
> >  		/* may have added more to prepare_pipes than we should */
> >  		prepare_pipes &= ~disable_pipes;
> > +	} else if (IS_BROXTON(dev)) {
> > +		broxton_modeset_global_pipes(dev, &prepare_pipes);
> > +		prepare_pipes &= ~disable_pipes;
> >  	}
> >  
> >  	ret = __intel_set_mode_setup_plls(dev, modeset_pipes, disable_pipes);
> > @@ -13133,6 +13205,9 @@ static void intel_init_display(struct drm_device *dev)
> >  	} else if (IS_VALLEYVIEW(dev)) {
> >  		dev_priv->display.modeset_global_resources =
> >  			valleyview_modeset_global_resources;
> > +	} else if (IS_BROXTON(dev)) {
> > +		dev_priv->display.modeset_global_resources =
> > +			broxton_modeset_global_resources;
> >  	}
> >  
> >  	switch (INTEL_INFO(dev)->gen) {
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> > index c77128c..4bc2041 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -873,6 +873,7 @@ void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
> >  void intel_ddi_clock_get(struct intel_encoder *encoder,
> >  			 struct intel_crtc_state *pipe_config);
> >  void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
> > +void bxt_select_cdclk_freq(struct drm_device *dev, u32 frequency);
> >  
> >  /* intel_frontbuffer.c */
> >  void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
> > @@ -1020,6 +1021,9 @@ void intel_prepare_reset(struct drm_device *dev);
> >  void intel_finish_reset(struct drm_device *dev);
> >  void hsw_enable_pc8(struct drm_i915_private *dev_priv);
> >  void hsw_disable_pc8(struct drm_i915_private *dev_priv);
> > +void bxt_init_cdclk(struct drm_device *dev);
> > +void bxt_uninit_cdclk(struct drm_device *dev);
> > +void bxt_ddi_phy_init(struct drm_device *dev);
> >  void intel_dp_get_m_n(struct intel_crtc *crtc,
> >  		      struct intel_crtc_state *pipe_config);
> >  void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
> > -- 
> > 2.1.0
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 


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Re: [PATCH 03/49] drm/i915/bxt: Add IS_BROXTON macro

[Sivakumar Thulasimani]

Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>

On 3/17/2015 3:09 PM, Imre Deak wrote:
> From: Satheeshakrishna M <satheeshakrishna.m@intel.com>
>
> Adding IS_BROXTON macro for broxton specific implementation.
>
> Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com>
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_drv.h | 1 +
>   1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 81f60b4..eba53c3 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2305,6 +2305,7 @@ struct drm_i915_cmd_table {
>   #define IS_HASWELL(dev)	(INTEL_INFO(dev)->is_haswell)
>   #define IS_BROADWELL(dev)	(!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
>   #define IS_SKYLAKE(dev)	(INTEL_INFO(dev)->is_skylake)
> +#define IS_BROXTON(dev)	(!INTEL_INFO(dev)->is_skylake && IS_GEN9(dev))
>   #define IS_MOBILE(dev)		(INTEL_INFO(dev)->is_mobile)
>   #define IS_HSW_EARLY_SDV(dev)	(IS_HASWELL(dev) && \
>   				 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)

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Re: [PATCH 01/49] drm/i915/bxt: Add BXT PCI ids

[Antti Koskipää]

Reviewed-by: Antti Koskipää <antti.koskipaa@linux.intel.com>

On 03/17/2015 11:39 AM, Imre Deak wrote:
> From: Damien Lespiau <damien.lespiau@intel.com>
> 
> v2: Switch to info->ring_mask and add VEBOX support.
> v3: Fold in update from Damien.
> v4: Add GEN_DEFAULT_PIPEOFFSETS and IVB_CURSOR_OFFSETS
> v5: set no-LLC (imre)
> 
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> (v1,v4)
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (v4)
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.c | 14 +++++++++++++-
>  include/drm/i915_pciids.h       |  6 ++++++
>  2 files changed, 19 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 82f8be4..4d50785 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -381,6 +381,17 @@ static const struct intel_device_info intel_skylake_gt3_info = {
>  	IVB_CURSOR_OFFSETS,
>  };
>  
> +static const struct intel_device_info intel_broxton_info = {
> +	.is_preliminary = 1,
> +	.gen = 9,
> +	.need_gfx_hws = 1, .has_hotplug = 1,
> +	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
> +	.num_pipes = 3,
> +	.has_ddi = 1,
> +	GEN_DEFAULT_PIPEOFFSETS,
> +	IVB_CURSOR_OFFSETS,
> +};
> +
>  /*
>   * Make sure any device matches here are from most specific to most
>   * general.  For example, since the Quanta match is based on the subsystem
> @@ -420,7 +431,8 @@ static const struct intel_device_info intel_skylake_gt3_info = {
>  	INTEL_CHV_IDS(&intel_cherryview_info),	\
>  	INTEL_SKL_GT1_IDS(&intel_skylake_info),	\
>  	INTEL_SKL_GT2_IDS(&intel_skylake_info),	\
> -	INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info)	\
> +	INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),	\
> +	INTEL_BXT_IDS(&intel_broxton_info)
>  
>  static const struct pci_device_id pciidlist[] = {		/* aka */
>  	INTEL_PCI_IDS,
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index 6133723..bd0d644 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -287,4 +287,10 @@
>  	INTEL_SKL_GT3_IDS(info)
>  
>  
> +#define INTEL_BXT_IDS(info) \
> +	INTEL_VGA_DEVICE(0x0A84, info), \
> +	INTEL_VGA_DEVICE(0x0A85, info), \
> +	INTEL_VGA_DEVICE(0x0A86, info), \
> +	INTEL_VGA_DEVICE(0x0A87, info)
> +
>  #endif /* _I915_PCIIDS_H */
> 

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Re: [PATCH 04/49] drm/i915/bxt: Broxton uses the same GMS values as Skylake

[Antti Koskipää]

Reviewed-by: Antti Koskipää <antti.koskipaa@linux.intel.com>

On 03/17/2015 11:39 AM, Imre Deak wrote:
> From: Damien Lespiau <damien.lespiau@intel.com>
> 
> v2: Rebase on top of the early-quirks rework from Ville.
> 
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> (v1)
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
>  arch/x86/kernel/early-quirks.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
> index fe9f0b7..ab470e4 100644
> --- a/arch/x86/kernel/early-quirks.c
> +++ b/arch/x86/kernel/early-quirks.c
> @@ -546,6 +546,7 @@ static const struct pci_device_id intel_stolen_ids[] __initconst = {
>  	INTEL_BDW_D_IDS(&gen8_stolen_funcs),
>  	INTEL_CHV_IDS(&chv_stolen_funcs),
>  	INTEL_SKL_IDS(&gen9_stolen_funcs),
> +	INTEL_BXT_IDS(&gen9_stolen_funcs),
>  };
>  
>  static void __init intel_graphics_stolen(int num, int slot, int func)
> 

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Re: [PATCH 05/49] drm/i915/bxt: Enable PTE encoding

[Antti Koskipää]

Reviewed-by: Antti Koskipää <antti.koskipaa@linux.intel.com>

On 03/17/2015 11:39 AM, Imre Deak wrote:
> From: Sumit Singh <sumit.k.singh@intel.com>
> 
> The caching options for page table entries have remained the same as
> Cherryview. This patch fixes it so the right code path is taken on BXT.
> 
> v2: Fix up commit message (Mike)
> 
> Signed-off-by: Sumit Singh <sumit.k.singh@intel.com>
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_gem_gtt.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index f1b9ea6..4311292 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -1506,7 +1506,7 @@ void i915_gem_restore_gtt_mappings(struct drm_device *dev)
>  
>  
>  	if (INTEL_INFO(dev)->gen >= 8) {
> -		if (IS_CHERRYVIEW(dev))
> +		if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
>  			chv_setup_private_ppat(dev_priv);
>  		else
>  			bdw_setup_private_ppat(dev_priv);
> @@ -2187,7 +2187,7 @@ static int gen8_gmch_probe(struct drm_device *dev,
>  
>  	*gtt_total = (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT;
>  
> -	if (IS_CHERRYVIEW(dev))
> +	if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
>  		chv_setup_private_ppat(dev_priv);
>  	else
>  		bdw_setup_private_ppat(dev_priv);
> 

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Re: [PATCH 08/49] drm/i915/bxt: Broxton DDB is 512 blocks

[Antti Koskipää]

Reviewed-by: Antti Koskipää <antti.koskipaa@linux.intel.com>

On 03/17/2015 11:39 AM, Imre Deak wrote:
> From: Damien Lespiau <damien.lespiau@intel.com>
> 
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 288c9d2..b89ab4d 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2538,6 +2538,7 @@ static bool ilk_disable_lp_wm(struct drm_device *dev)
>   */
>  
>  #define SKL_DDB_SIZE		896	/* in blocks */
> +#define BXT_DDB_SIZE		512
>  
>  static void
>  skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
> @@ -2556,7 +2557,10 @@ skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
>  		return;
>  	}
>  
> -	ddb_size = SKL_DDB_SIZE;
> +	if (IS_BROXTON(dev))
> +		ddb_size = BXT_DDB_SIZE;
> +	else
> +		ddb_size = SKL_DDB_SIZE;
>  
>  	ddb_size -= 4; /* 4 blocks for bypass path allocation */
>  
> 

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Re: [PATCH 09/49] drm/i915/bxt: Broxton raises the maximum number of planes to 4

[Antti Koskipää]

Reviewed-by: Antti Koskipää <antti.koskipaa@linux.intel.com>

On 03/17/2015 11:39 AM, Imre Deak wrote:
> From: Damien Lespiau <damien.lespiau@intel.com>
> 
> Pipe A and b have 4 planes.
> 
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index eba53c3..8fb7cc0 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -130,7 +130,7 @@ enum transcoder {
>   *
>   * This value doesn't count the cursor plane.
>   */
> -#define I915_MAX_PLANES	3
> +#define I915_MAX_PLANES	4
>  
>  enum plane {
>  	PLANE_A = 0,
> 

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Re: [PATCH 07/49] drm/i915/bxt: Add the plane4 related interrupt definitions

[Antti Koskipää]

Reviewed-by: Antti Koskipää <antti.koskipaa@linux.intel.com>

On 03/17/2015 11:39 AM, Imre Deak wrote:
> From: Damien Lespiau <damien.lespiau@intel.com>
> 
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index cc8ebab..3369a11 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5216,9 +5216,11 @@ enum skl_disp_power_wells {
>  #define  GEN8_PIPE_VSYNC		(1 << 1)
>  #define  GEN8_PIPE_VBLANK		(1 << 0)
>  #define  GEN9_PIPE_CURSOR_FAULT		(1 << 11)
> +#define  GEN9_PIPE_PLANE4_FAULT		(1 << 10)
>  #define  GEN9_PIPE_PLANE3_FAULT		(1 << 9)
>  #define  GEN9_PIPE_PLANE2_FAULT		(1 << 8)
>  #define  GEN9_PIPE_PLANE1_FAULT		(1 << 7)
> +#define  GEN9_PIPE_PLANE4_FLIP_DONE	(1 << 6)
>  #define  GEN9_PIPE_PLANE3_FLIP_DONE	(1 << 5)
>  #define  GEN9_PIPE_PLANE2_FLIP_DONE	(1 << 4)
>  #define  GEN9_PIPE_PLANE1_FLIP_DONE	(1 << 3)
> @@ -5229,6 +5231,7 @@ enum skl_disp_power_wells {
>  	 GEN8_PIPE_PRIMARY_FAULT)
>  #define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \
>  	(GEN9_PIPE_CURSOR_FAULT | \
> +	 GEN9_PIPE_PLANE4_FAULT | \
>  	 GEN9_PIPE_PLANE3_FAULT | \
>  	 GEN9_PIPE_PLANE2_FAULT | \
>  	 GEN9_PIPE_PLANE1_FAULT)
> 

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Re: [PATCH 06/49] drm/i915/bxt: Broxton has 3 sprite planes on pipe A/B, 2 on pipe C

[Antti Koskipää]

Reviewed-by: Antti Koskipää <antti.koskipaa@linux.intel.com>

On 03/17/2015 11:39 AM, Imre Deak wrote:
> From: Damien Lespiau <damien.lespiau@intel.com>
> 
> v2: Rebase on top of the for_each_pipe() change adding dev_priv as first
>     argument.
> 
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_dma.c | 6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index d49ed68..a94a970 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -585,7 +585,11 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
>  
>  	info = (struct intel_device_info *)&dev_priv->info;
>  
> -	if (IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen == 9)
> +	if (IS_BROXTON(dev)) {
> +		info->num_sprites[PIPE_A] = 3;
> +		info->num_sprites[PIPE_B] = 3;
> +		info->num_sprites[PIPE_C] = 2;
> +	} else if (IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen == 9)
>  		for_each_pipe(dev_priv, pipe)
>  			info->num_sprites[pipe] = 2;
>  	else
> 

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Re: [PATCH 46/49] drm/i915: Iterate through the initialized DDIs to prepare their buffers

[Sivakumar Thulasimani]

On 3/17/2015 3:10 PM, Imre Deak wrote:
> From: Damien Lespiau <damien.lespiau@intel.com>
>
> Not every DDIs is necessarily connected can be strapped off and, in the
> future, we'll have platforms with a different number of default DDI
> ports. So, let's only call intel_prepare_ddi_buffers() on DDI ports that
> are actually detected.
>
> We also use the opportunity to give a struct intel_digital_port to
> intel_prepare_ddi_buffers() as we'll need it in a following patch to
> query if the port supports HMDI or not.
>
> On my HSW machine this removes the initialization of a couple of
> (unused) DDIs.
>
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_drv.h  |  4 ++++
>   drivers/gpu/drm/i915/intel_ddi.c | 16 ++++++++++++----
>   2 files changed, 16 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index e4dd4bba..e6402b0 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -251,6 +251,10 @@ enum hpd_pin {
>   			    &dev->mode_config.connector_list,	\
>   			    base.head)
>   
> +#define for_each_digital_port(dev, digital_port)		\
> +	list_for_each_entry(digital_port,			\
> +			    &dev->mode_config.encoder_list,	\
> +			    base.base.head)
>   
>   #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
>   	list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index ff62054..5c18018 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -189,10 +189,12 @@ enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
>    * in either FDI or DP modes only, as HDMI connections will work with both
>    * of those
>    */
> -static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port)
> +static void intel_prepare_ddi_buffers(struct drm_device *dev,
> +				      struct intel_digital_port *intel_dig_port)
>   {
>   	struct drm_i915_private *dev_priv = dev->dev_private;
>   	u32 reg;
> +	int port = intel_dig_port->port;
>   	int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry,
>   	    size;
>   	int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
> @@ -307,13 +309,19 @@ static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port)
>    */
>   void intel_prepare_ddi(struct drm_device *dev)
>   {
> -	int port;
> +	struct intel_digital_port *intel_dig_port;
> +	bool visited[I915_MAX_PORTS] = { 0, };
>   
>   	if (!HAS_DDI(dev))
>   		return;
>   
> -	for (port = PORT_A; port <= PORT_E; port++)
> -		intel_prepare_ddi_buffers(dev, port);
> +	for_each_digital_port(dev, intel_dig_port) {
> +		if (visited[intel_dig_port->port])
> +			continue;
> +
> +		intel_prepare_ddi_buffers(dev, intel_dig_port);
> +		visited[intel_dig_port->port] = true;
> +	}
>   }
>   
>   static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
is visited[] for handling MST scenarios ?if so looks good to me.
Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>

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Re: [PATCH 47/49] drm/i915: Don't write the HDMI buffer translation entry when not needed

[Sivakumar Thulasimani]

Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>

On 3/17/2015 3:10 PM, Imre Deak wrote:
> From: Damien Lespiau <damien.lespiau@intel.com>
>
> We don't actually need to write the HDMI entry on DDIs that have no
> chance to be used as HDMI ports.
>
> While this patch shouldn't change the current behaviour, it makes
> further enabling work easier as we'll have an eDP table filling the full
> 10 entries.
>
> v2: Rely on the logic from intel_ddi_init() to figure out if the DDI port
>      supports HDMI or not (Paulo).
>
> Suggested-by: Satheeshakrishna M <satheeshakrishna.m@intel.com>
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_ddi.c | 9 +++++++++
>   1 file changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 5c18018..5aa4dab 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -182,6 +182,12 @@ enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
>   	}
>   }
>   
> +static bool
> +intel_dig_port_supports_hdmi(const struct intel_digital_port *intel_dig_port)
> +{
> +	return intel_dig_port->hdmi.hdmi_reg;
> +}
> +
>   /*
>    * Starting with Haswell, DDI port buffers must be programmed with correct
>    * values in advance. The buffer values are different for FDI and DP modes,
> @@ -292,6 +298,9 @@ static void intel_prepare_ddi_buffers(struct drm_device *dev,
>   		reg += 4;
>   	}
>   
> +	if (!intel_dig_port_supports_hdmi(intel_dig_port))
> +		return;
> +
>   	/* Choose a good default if VBT is badly populated */
>   	if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
>   	    hdmi_level >= n_hdmi_entries)

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Re: [PATCH 48/49] drm/i915/bxt: VSwing programming sequence

[Sivakumar Thulasimani]

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On 3/17/2015 3:10 PM, Imre Deak wrote:
> From: Vandana Kannan <vandana.kannan@intel.com>
>
> VSwing programming sequence as specified in the updated BXT BSpec
> ...
> ...
>   
> +void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
> +			     enum port port, int type)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	const struct bxt_ddi_buf_trans *ddi_translations;
> +	u32 n_entries, i;
> +	uint32_t val;
> +
> +	if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
INTEL_OUPPUT_DP_MST might be needed here, please check once. otherwise 
fine with the changes.
Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>


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Re: [PATCH 49/49] drm/i915/bxt: Update max level of vswing

[Sivakumar Thulasimani]

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Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>


On 3/17/2015 3:10 PM, Imre Deak wrote:
> From: Vandana Kannan <vandana.kannan@intel.com>
>
> Broxton supports 3 voltage swing levels on all DP ports.
> Max level of pre-emphasis will be taken care with the existing code.
>
> v2: Patch rebased
>
> v3: (imre)
> - keep existing behavior for other platforms
> - clarify commit message
>
> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> (v2)
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_dp.c | 4 +++-
>   1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 1cb6eb0..019c224 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -2832,7 +2832,9 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
>   	struct drm_i915_private *dev_priv = dev->dev_private;
>   	enum port port = dp_to_dig_port(intel_dp)->port;
>   
> -	if (INTEL_INFO(dev)->gen >= 9) {
> +	if (IS_BROXTON(dev))
> +		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
> +	else if (INTEL_INFO(dev)->gen >= 9) {
>   		if (dev_priv->vbt.edp_low_vswing && port == PORT_A)
>   			return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
>   		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;


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Re: [PATCH 16/49] drm/i915/bxt: add WaDisableMaskBasedCammingInRCC workaround

[Nick Hoath]

On 20/03/2015 10:25, Deak, Imre wrote:
> On Fri, 2015-03-20 at 09:05 +0000, Nick Hoath wrote:
>> On 17/03/2015 09:39, Imre Deak wrote:
>>> From: Ben Widawsky <benjamin.widawsky@intel.com>
>>>
>>> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
>>> Signed-off-by: Imre Deak <imre.deak@intel.com>
>>> ---
>>>    drivers/gpu/drm/i915/i915_reg.h         | 4 ++++
>>>    drivers/gpu/drm/i915/intel_ringbuffer.c | 9 +++++++++
>>>    2 files changed, 13 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>>> index b7ba061..1d074e8 100644
>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>> @@ -5346,6 +5346,10 @@ enum skl_disp_power_wells {
>>>    #define  HDC_FORCE_NON_COHERENT			(1<<4)
>>>    #define  HDC_BARRIER_PERFORMANCE_DISABLE	(1<<10)
>>>
>>> +/* GEN9 chicken */
>>> +#define SLICE_ECO_CHICKEN0			0x7308
>>> +#define   PIXEL_MASK_CAMMING_DISABLE		(1 << 14)
>>> +
>>>    /* WaCatErrorRejectionIssue */
>>>    #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		0x9030
>>>    #define  GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB	(1<<11)
>>> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
>>> index abe062a..e23cbdc 100644
>>> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
>>> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
>>> @@ -966,6 +966,15 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
>>>    	WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
>>>    			  GEN9_CCS_TLB_PREFETCH_ENABLE);
>>>
>>> +	/*
>>> +	 * FIXME: don't apply the following on BXT for stepping C. On BXT A0
>>> +	 * the flag reads back as 0.
>>> +	 */
>>
>> I've just posted a patch with the stepping macros. You can use these in
>> the same way as for Skylake.
>
> I'm not so happy to make these changes at this point. Without them we
> still have a correct - even if conservative - behavior on other
> steppings. There are quite a few places marked with FIXME that need
> improvement in a similar way and I'd leave them as-is for now to keep as
> close as possible to the good known working state (as of the power-on)
> and to make merging of this initial patchset fast.
>

In that case:
Reviewed-by: Nick Hoath <nicholas.hoath@intel.com>

>>
>>> +	/* WaDisableMaskBasedCammingInRCC:bxtA */
>>> +	if (IS_BROXTON(dev))
>>> +		WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
>>> +				  PIXEL_MASK_CAMMING_DISABLE);
>>> +
>>>    	return 0;
>>>    }
>>>
>>>
>>
>
>

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Re: [PATCH 14/49] drm/i915/bxt: add GEN8_SDEUNIT_CLOCK_GATE_DISABLE workaround

[Nick Hoath]

On 20/03/2015 10:37, Deak, Imre wrote:
> On Fri, 2015-03-20 at 09:08 +0000, Nick Hoath wrote:
>> On 17/03/2015 13:06, Imre Deak wrote:
>>> On ti, 2015-03-17 at 11:35 +0100, Daniel Vetter wrote:
>>>> On Tue, Mar 17, 2015 at 11:39:40AM +0200, Imre Deak wrote:
>>>>> Signed-off-by: Imre Deak <imre.deak@intel.com>
>>>>> ---
>>>>>    drivers/gpu/drm/i915/intel_pm.c | 11 +++++++++++
>>>>>    1 file changed, 11 insertions(+)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>>>>> index 3d4a7c3..d5dd0b3 100644
>>>>> --- a/drivers/gpu/drm/i915/intel_pm.c
>>>>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>>>>> @@ -96,7 +96,18 @@ static void skl_init_clock_gating(struct drm_device *dev)
>>>>>
>>>>>    static void bxt_init_clock_gating(struct drm_device *dev)
>>>>>    {
>>>>> +	struct drm_i915_private *dev_priv = dev->dev_private;
>>>>> +
>>>>>    	gen9_init_clock_gating(dev);
>>>>> +
>>>>> +	/*
>>>>> +	 * FIXME:
>>>>> +	 * GEN8_SDEUNIT_CLOCK_GATE_DISABLE applies on A0 only.
>>>>
>>>> We have pci revid macros now. Do you have plans to roll similar ones out
>>>> for bxt?
>>>
>>> Yes. It may be that for BXT we also need to look at the PCI_REVISION_ID
>>> field besides PCI_CLASS_REVISION, I still have to figure out the exact
>>> mapping. (And also understand the meaning/difference between SOC vs. GT
>>> revision IDs).
>
> Ok, the above is red herring. PCI_REVISION_ID is just the 8 low bits of
> PCI_CLASS_REVISION, so we can reuse INTEL_REVID as-is.
>
>> I've posted a patch with the Broxton revision ID's from the specs.
>
> It looks ok, but I prefer adding them as a follow-up to this patchset.
>
>
Reviewed-by: Nick Hoath <nicholas.hoath@intel.com>

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Re: [PATCH 46/49] drm/i915: Iterate through the initialized DDIs to prepare their buffers

[Damien Lespiau]

On Mon, Mar 23, 2015 at 04:21:07PM +0530, Sivakumar Thulasimani wrote:
> >  void intel_prepare_ddi(struct drm_device *dev)
> >  {
> >-	int port;
> >+	struct intel_digital_port *intel_dig_port;
> >+	bool visited[I915_MAX_PORTS] = { 0, };
> >  	if (!HAS_DDI(dev))
> >  		return;
> >-	for (port = PORT_A; port <= PORT_E; port++)
> >-		intel_prepare_ddi_buffers(dev, port);
> >+	for_each_digital_port(dev, intel_dig_port) {
> >+		if (visited[intel_dig_port->port])
> >+			continue;
> >+
> >+		intel_prepare_ddi_buffers(dev, intel_dig_port);
> >+		visited[intel_dig_port->port] = true;
> >+	}
> >  }
> >  static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
> is visited[] for handling MST scenarios ?if so looks good to me.

Yes visited[] is to make sure we don't re-init the DDI for the MST
encoders.

Paulo had another review comment I never had time to address though:

https://freedesktop.org/patch/31026/

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Re: [PATCH 19/49] drm/i915/bxt: don't use unsupported port detection

[Jani Nikula]

On Tue, 17 Mar 2015, Imre Deak <imre.deak@intel.com> wrote:
> From: Vandana Kannan <vandana.kannan@intel.com>
>
> The port detection register flags in SFUSE_STRAP and DDI_BUF_CTL_A are
> not defined for BXT, so don't use them.
>
> Suggested by Satheesh.
>
> v2:
> - DDI_BUF_CTL_A bit 0 is not useful on BXT. Making changes to use this
>   bit when simulator or BXT is not applicable. Code re-arranged as per
>   Damien's suggestion.
>
> v3:
> - clarify commit message, add code comment (imre)
>
> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> (v2)
> Cc: M, Satheeshakrishna <satheeshakrishna.m@intel.com>
> Cc: Lespiau, Damien <damien.lespiau@intel.com>
> Cc: Shankar, Uma <uma.shankar@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/intel_display.c | 11 ++++++++++-
>  1 file changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 90b460c..e54e948 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -12615,7 +12615,16 @@ static void intel_setup_outputs(struct drm_device *dev)
>  	if (intel_crt_present(dev))
>  		intel_crt_init(dev);
>  
> -	if (HAS_DDI(dev)) {
> +	if (IS_BROXTON(dev)) {
> +		/*
> +		 * FIXME: Broxton doesn't support port detection via the
> +		 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
> +		 * detect the ports.
> +		 */
> +		intel_ddi_init(dev, PORT_A);
> +		intel_ddi_init(dev, PORT_B);
> +		intel_ddi_init(dev, PORT_C);
> +	} else if (HAS_DDI(dev)) {
>  		int found;
>  
>  		/*
> -- 
> 2.1.0
>
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Re: [PATCH 20/49] drm/i915/bxt: Add change to support gmbus pin pair for BXT

[Jani Nikula]

On Tue, 17 Mar 2015, Imre Deak <imre.deak@intel.com> wrote:
> From: "A.Sunil Kamath" <sunil.kamath@intel.com>
>
> For BXT gmbus is pulled from GPU to CPU. From implementation
> point of view only pin pair configuration will change. The
> existing implementation supports all platforms previous to GEN8
> and also SKL. But for BXT pin pair configuration
> is completely different than SKL or other previous GEN's.
> This patch introduces the new pin pair configuration structure
> specific to BXT and also ensures every real gmbus port has a
> gpio pin.
>
> Tested on BDW hardware to confirm it doesnt break anything
> in existing platform.
>
> For BDW pin pair config will remain as:
> gmbus[0]: Name = i915 gmbus ssc, gpio_reg = c5014, reg0 = 1
> gmbus[1]: Name = i915 gmbus vga, gpio_reg = c5010, reg0 = 2
> gmbus[2]: Name = i915 gmbus panel, gpio_reg = c5018, reg0 = 3
> gmbus[3]: Name = i915 gmbus dpc, gpio_reg = c501c, reg0 = 4
> gmbus[4]: Name = i915 gmbus dpb, gpio_reg = c5020, reg0 = 5
> gmbus[5]: Name = i915 gmbus dpd, gpio_reg = c5024, reg0 = 6
>
> BXT will have:
> gmbus[0]: name = i915 gmbus None, gpio_reg = 0, reg0 = 0
> gmbus[1]: name = i915 gmbus None, gpio_reg = 0, reg0 = 0
> gmbus[2]: name = i915 gmbus None, gpio_reg = 0, reg0 = 0
> gmbus[3]: name = i915 gmbus dpc, gpio_reg = c5018, reg0 = 2
> gmbus[4]: name = i915 gmbus dpb, gpio_reg = c5014, reg0 = 1
> gmbus[5]: name = i915 gmbus misc, gpio_reg = c501c, reg0 = 3
>
> Values of GMBUS_PORT_DPB, GMBUS_PORT_DPC, GMBUS_PORT_DPD is
> retained as it is like other platforms. Only logic in gmbus
> structure creation is changed to minimize changes in multiple
> files.
>
> v1: Initial release
> Structure gmbus_ports_bxt  created for 3 ports only.
> Here for BXT, gmbus[0], gmbus[1], gmbus[2] is untouched.
> Logic used to calculate pin from respective register address as:
> pin = reg & 0x000f >> 2
>
> v2: Incorporated review comments from Jani Nikula.
> Added a full bxt specific gmbus_ports_bxt and used it for bxt
> regardless of pin >= 4.
> Added const char *name and initialized it conditionally to
> IS_BROXTON() so and avoided duplication of snprintf.
> Added port_to_pin_bxt(port) function which returns right
> pin value for a port for bxt platform.
>
> Issue: VIZ-3574
> Signed-off-by: A.Sunil Kamath <sunil.kamath@intel.com>
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_i2c.c | 55 +++++++++++++++++++++++++++++++++++-----
>  1 file changed, 49 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
> index b31088a..3aa31e1 100644
> --- a/drivers/gpu/drm/i915/intel_i2c.c
> +++ b/drivers/gpu/drm/i915/intel_i2c.c
> @@ -48,6 +48,16 @@ static const struct gmbus_port gmbus_ports[] = {
>  	{ "dpd", GPIOF },
>  };
>  
> +/* gmbus pin pair configuration for bxt */
> +static const struct gmbus_port gmbus_ports_bxt[] = {
> +	{ "None", 0 },
> +	{ "None", 0 },
> +	{ "None", 0 },
> +	{ "dpc", PCH_GPIOC },
> +	{ "dpb", PCH_GPIOB },
> +	{ "misc", PCH_GPIOD },
> +};
> +
>  /* Intel GPIO access functions */
>  
>  #define I2C_RISEFALL_TIME 10
> @@ -185,12 +195,17 @@ static void
>  intel_gpio_setup(struct intel_gmbus *bus, u32 pin)
>  {
>  	struct drm_i915_private *dev_priv = bus->dev_priv;
> +	struct drm_device *dev = dev_priv->dev;

IS_BROXTON() eats dev_priv too so this is not needed.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


>  	struct i2c_algo_bit_data *algo;
>  
>  	algo = &bus->bit_algo;
>  
>  	/* -1 to map pin pair to gmbus index */
> -	bus->gpio_reg = dev_priv->gpio_mmio_base + gmbus_ports[pin - 1].reg;
> +	if (IS_BROXTON(dev))
> +		bus->gpio_reg = gmbus_ports_bxt[pin - 1].reg;
> +	else
> +		bus->gpio_reg = dev_priv->gpio_mmio_base
> +				+ gmbus_ports[pin - 1].reg;
>  
>  	bus->adapter.algo_data = algo;
>  	algo->setsda = set_data;
> @@ -510,6 +525,27 @@ static const struct i2c_algorithm gmbus_algorithm = {
>  	.functionality	= gmbus_func
>  };
>  
> +/* returns mapped pin for a port in BXT */
> +static u32 port_to_pin_bxt(u32 port)
> +{
> +	u32 pin;
> +
> +	switch (port) {
> +	case GMBUS_PORT_DPB:
> +		pin = 1;
> +		break;
> +	case GMBUS_PORT_DPC:
> +		pin = 2;
> +		break;
> +	case GMBUS_PORT_DPD:
> +		pin = 3;
> +		break;
> +	default:
> +		pin = 0;
> +	}
> +	return pin;
> +}
> +
>  /**
>   * intel_gmbus_setup - instantiate all Intel i2c GMBuses
>   * @dev: DRM device
> @@ -534,13 +570,17 @@ int intel_setup_gmbus(struct drm_device *dev)
>  	for (i = 0; i < GMBUS_NUM_PORTS; i++) {
>  		struct intel_gmbus *bus = &dev_priv->gmbus[i];
>  		u32 port = i + 1; /* +1 to map gmbus index to pin pair */
> +		const char *name;
>  
>  		bus->adapter.owner = THIS_MODULE;
>  		bus->adapter.class = I2C_CLASS_DDC;
> -		snprintf(bus->adapter.name,
> -			 sizeof(bus->adapter.name),
> -			 "i915 gmbus %s",
> -			 gmbus_ports[i].name);
> +		if (IS_BROXTON(dev))
> +			name = gmbus_ports_bxt[i].name;
> +		else
> +			name = gmbus_ports[i].name;
> +
> +		snprintf(bus->adapter.name, sizeof(bus->adapter.name),
> +			 "i915 gmbus %s", name);
>  
>  		bus->adapter.dev.parent = &dev->pdev->dev;
>  		bus->dev_priv = dev_priv;
> @@ -548,7 +588,10 @@ int intel_setup_gmbus(struct drm_device *dev)
>  		bus->adapter.algo = &gmbus_algorithm;
>  
>  		/* By default use a conservative clock rate */
> -		bus->reg0 = port | GMBUS_RATE_100KHZ;
> +		if (IS_BROXTON(dev))
> +			bus->reg0 = port_to_pin_bxt(port) | GMBUS_RATE_100KHZ;
> +		else
> +			bus->reg0 = port | GMBUS_RATE_100KHZ;
>  
>  		/* gmbus seems to be broken on i830 */
>  		if (IS_I830(dev))
> -- 
> 2.1.0
>
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Re: [PATCH 21/49] drm/i915/bxt: WARN in case BXT unused gmbus ports are accessed

[Jani Nikula]

On Tue, 17 Mar 2015, Imre Deak <imre.deak@intel.com> wrote:
> From: "A.Sunil Kamath" <sunil.kamath@intel.com>
>
> This patch will WARN if unused gmbus ports gets accessed for
> BXT using gmbus_get_adapter also ensure that only valid ports
> of BXT gets used. For BXT its more important to do this as it
> has only 3 valid ports and structure has empty content otherwise.
>
> Because of additonal IS_BROXTON check an additional "dev"
> argument is added to intel_gmbus_is_port_valid. Also added
> related changes in other places from where this function is accessed.
>
> v1: This WARN patch is added as per review comments from
> Daniel Vetter on gmbus BXT patch
>
> v2: Changed get_adapter to have only one is_port_valid call
> according to review comments from M Satheeshakrishna.
>
> v3: Early bail out on errors according to review comments from
> Daniel Vetter.
>
> Issue: VIZ-3574
> Signed-off-by: A.Sunil Kamath <sunil.kamath@intel.com>
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h   | 8 ++++++--
>  drivers/gpu/drm/i915/intel_bios.c | 3 ++-
>  drivers/gpu/drm/i915/intel_dvo.c  | 2 +-
>  drivers/gpu/drm/i915/intel_i2c.c  | 9 ++++++---
>  drivers/gpu/drm/i915/intel_lvds.c | 2 +-
>  drivers/gpu/drm/i915/intel_sdvo.c | 4 +++-
>  6 files changed, 19 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 8fb7cc0..52e5f18 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3037,9 +3037,13 @@ void i915_teardown_sysfs(struct drm_device *dev_priv);
>  /* intel_i2c.c */
>  extern int intel_setup_gmbus(struct drm_device *dev);
>  extern void intel_teardown_gmbus(struct drm_device *dev);
> -static inline bool intel_gmbus_is_port_valid(unsigned port)
> +static inline bool
> +intel_gmbus_is_port_valid(struct drm_device *dev, unsigned port)

It's probably better to pass dev_priv here, and fix all the call
sites. Removes a bunch of extra local vars down there.

With this fixed,

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


>  {
> -	return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
> +	if (IS_BROXTON(dev))
> +		return port >= GMBUS_PORT_DPC && port <= GMBUS_PORT_DPD;

It's seriously confusing that _DPB is within that range... but not a
problem in this patch per se.

> +	else
> +		return port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD;
>  }
>  
>  extern struct i2c_adapter *intel_gmbus_get_adapter(
> diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
> index c684085..e423cc8 100644
> --- a/drivers/gpu/drm/i915/intel_bios.c
> +++ b/drivers/gpu/drm/i915/intel_bios.c
> @@ -431,6 +431,7 @@ parse_general_definitions(struct drm_i915_private *dev_priv,
>  			  struct bdb_header *bdb)
>  {
>  	struct bdb_general_definitions *general;
> +	struct drm_device *dev = dev_priv->dev;
>  
>  	general = find_section(bdb, BDB_GENERAL_DEFINITIONS);
>  	if (general) {
> @@ -438,7 +439,7 @@ parse_general_definitions(struct drm_i915_private *dev_priv,
>  		if (block_size >= sizeof(*general)) {
>  			int bus_pin = general->crt_ddc_gmbus_pin;
>  			DRM_DEBUG_KMS("crt_ddc_bus_pin: %d\n", bus_pin);
> -			if (intel_gmbus_is_port_valid(bus_pin))
> +			if (intel_gmbus_is_port_valid(dev, bus_pin))
>  				dev_priv->vbt.crt_ddc_pin = bus_pin;
>  		} else {
>  			DRM_DEBUG_KMS("BDB_GD too small (%d). Invalid.\n",
> diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c
> index d857951..27d5b9a 100644
> --- a/drivers/gpu/drm/i915/intel_dvo.c
> +++ b/drivers/gpu/drm/i915/intel_dvo.c
> @@ -499,7 +499,7 @@ void intel_dvo_init(struct drm_device *dev)
>  		 * special cases, but otherwise default to what's defined
>  		 * in the spec.
>  		 */
> -		if (intel_gmbus_is_port_valid(dvo->gpio))
> +		if (intel_gmbus_is_port_valid(dev, dvo->gpio))
>  			gpio = dvo->gpio;
>  		else if (dvo->type == INTEL_DVO_CHIP_LVDS)
>  			gpio = GMBUS_PORT_SSC;
> diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
> index 3aa31e1..06892b5 100644
> --- a/drivers/gpu/drm/i915/intel_i2c.c
> +++ b/drivers/gpu/drm/i915/intel_i2c.c
> @@ -619,10 +619,13 @@ err:
>  struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv,
>  					    unsigned port)
>  {
> -	WARN_ON(!intel_gmbus_is_port_valid(port));
> +	struct drm_device *dev = dev_priv->dev;
> +
> +	if (WARN_ON(!intel_gmbus_is_port_valid(dev, port)))
> +		return NULL;
> +
>  	/* -1 to map pin pair to gmbus index */
> -	return (intel_gmbus_is_port_valid(port)) ?
> -		&dev_priv->gmbus[port - 1].adapter : NULL;
> +	return &dev_priv->gmbus[port - 1].adapter;
>  }
>  
>  void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
> diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
> index 24e8730..094b88e 100644
> --- a/drivers/gpu/drm/i915/intel_lvds.c
> +++ b/drivers/gpu/drm/i915/intel_lvds.c
> @@ -780,7 +780,7 @@ static bool lvds_is_present_in_vbt(struct drm_device *dev,
>  		    child->device_type != DEVICE_TYPE_LFP)
>  			continue;
>  
> -		if (intel_gmbus_is_port_valid(child->i2c_pin))
> +		if (intel_gmbus_is_port_valid(dev, child->i2c_pin))
>  			*i2c_pin = child->i2c_pin;
>  
>  		/* However, we cannot trust the BIOS writers to populate
> diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
> index 9e554c2..d68936e 100644
> --- a/drivers/gpu/drm/i915/intel_sdvo.c
> +++ b/drivers/gpu/drm/i915/intel_sdvo.c
> @@ -2283,6 +2283,7 @@ intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
>  			  struct intel_sdvo *sdvo, u32 reg)
>  {
>  	struct sdvo_device_mapping *mapping;
> +	struct drm_device *dev = dev_priv->dev;
>  	u8 pin;
>  
>  	if (sdvo->is_sdvob)
> @@ -2290,7 +2291,8 @@ intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
>  	else
>  		mapping = &dev_priv->sdvo_mappings[1];
>  
> -	if (mapping->initialized && intel_gmbus_is_port_valid(mapping->i2c_pin))
> +	if (mapping->initialized &&
> +		intel_gmbus_is_port_valid(dev, mapping->i2c_pin))
>  		pin = mapping->i2c_pin;
>  	else
>  		pin = GMBUS_PORT_DPB;
> -- 
> 2.1.0
>
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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Re: [PATCH 02/49] drm/i915/bxt: BXT FBC enablement

[Imre Deak]

On Tue, 2015-03-17 at 10:49 -0700, Rodrigo Vivi wrote:
> Does BXT really has fbc?

Yes.

> And same implementation and registers as HSW?

Yes, but actually the selection for BXT would be incorrect in
i915_setup_compression(), I can follow up with a fix for that in this
patchset. In addition we also need to add BXT specific workarounds, but
I would suggest doing that as a follow-up to this enabling patchset.

--Imre

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[PATCH 02.1/49] drm/i915: use proper FBC base register on all new platforms

[Imre Deak]

Starting from GEN5 the FBC base register is the same on all platforms.
GEN>=5 is the same condition as HAS_PCH_SPLIT except on BXT, so make
things work on BXT as well.

Motivated by Rodrigo's request to check FBC support on BXT.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_stolen.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c
index f8da716..348ed5a 100644
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -209,7 +209,7 @@ static int i915_setup_compression(struct drm_device *dev, int size, int fb_cpp)
 
 	dev_priv->fbc.threshold = ret;
 
-	if (HAS_PCH_SPLIT(dev))
+	if (INTEL_INFO(dev_priv)->gen >= 5)
 		I915_WRITE(ILK_DPFC_CB_BASE, dev_priv->fbc.compressed_fb.start);
 	else if (IS_GM45(dev)) {
 		I915_WRITE(DPFC_CB_BASE, dev_priv->fbc.compressed_fb.start);
-- 
2.1.0

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Re: [PATCH 22/49] drm/i915/bxt: Avoid registering unused gmbus ports as i2c adapter

[Jani Nikula]

On Tue, 17 Mar 2015, Imre Deak <imre.deak@intel.com> wrote:
> From: "A.Sunil Kamath" <sunil.kamath@intel.com>
>
> Though we populate all gmbus ports during setup_gmbus, only
> valid ones should be registered to i2c adapters. This is
> important as userspace can directly interact with the i2c bus.
>
> While populating gmbus register we ensure that unused ports
> will have gpio_reg value set as 0. This patch ensures that
> only those with non zero gpio reg will get registered as i2c
> adapter and this is applicable for all platforms.
>
> del_adapter will check if the adaptor was really added
> before, still its better to avoid unnecessary calls to the same.
> This patch also adds a check to deregister only added i2c adapters.
>
> Tested using i2c-tools to confirm that only valid gmbus ports
> are registered as i2c adapter.
>
> BXT will have only valid i2c adapters as below:
> i2c-x      i2c     i915 gmbus dpc      I2C adapter
> i2c-x+1    i2c     i915 gmbus dpb      I2C adapter
> i2c-x+2    i2c     i915 gmbus misc     I2C adapter
>
> v1: This patch is added as per review comments from
> Daniel Vetter on gmbus BXT patch
>
> Issue: VIZ-3574
> Signed-off-by: A.Sunil Kamath <sunil.kamath@intel.com>
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_i2c.c | 15 ++++++++++-----
>  1 file changed, 10 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
> index 06892b5..d5ca310 100644
> --- a/drivers/gpu/drm/i915/intel_i2c.c
> +++ b/drivers/gpu/drm/i915/intel_i2c.c
> @@ -599,9 +599,12 @@ int intel_setup_gmbus(struct drm_device *dev)
>  
>  		intel_gpio_setup(bus, port);
>  
> -		ret = i2c_add_adapter(&bus->adapter);
> -		if (ret)
> -			goto err;
> +		/* Do not register unused gmbus ports as i2c adapter */
> +		if (bus->gpio_reg) {

This works by accident, as bus->gpio_reg will contain
dev_priv->gpio_mmio_base even if the reg is 0. Luckily for BXT this is
the case.

I think the question is, why do we initialize anything for
dev_priv->gmbus[i] where i is an unused pin pair? I think we should have
the validity check at the top, and if (invalid) continue;.

I care because we appear to be registering unused adapters also on other
recent platforms, and we should fix that too. That doesn't have to be
part of bxt enabling, but I don't like adding broken stuff that makes
future work harder.

BR,
Jani.



> + ret = i2c_add_adapter(&bus->adapter); + if (ret) + goto err; + } }
>  
>  	intel_i2c_reset(dev_priv->dev);
> @@ -611,7 +614,8 @@ int intel_setup_gmbus(struct drm_device *dev)
>  err:
>  	while (--i) {
>  		struct intel_gmbus *bus = &dev_priv->gmbus[i];
> -		i2c_del_adapter(&bus->adapter);
> +		if (bus->gpio_reg)
> +			i2c_del_adapter(&bus->adapter);
>  	}
>  	return ret;
>  }
> @@ -652,6 +656,7 @@ void intel_teardown_gmbus(struct drm_device *dev)
>  
>  	for (i = 0; i < GMBUS_NUM_PORTS; i++) {
>  		struct intel_gmbus *bus = &dev_priv->gmbus[i];
> -		i2c_del_adapter(&bus->adapter);
> +		if (bus->gpio_reg)
> +			i2c_del_adapter(&bus->adapter);
>  	}
>  }
> -- 
> 2.1.0
>
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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Re: [PATCH 22/49] drm/i915/bxt: Avoid registering unused gmbus ports as i2c adapter

[Jani Nikula]

On Thu, 26 Mar 2015, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> On Tue, 17 Mar 2015, Imre Deak <imre.deak@intel.com> wrote:
>> From: "A.Sunil Kamath" <sunil.kamath@intel.com>
>>
>> Though we populate all gmbus ports during setup_gmbus, only
>> valid ones should be registered to i2c adapters. This is
>> important as userspace can directly interact with the i2c bus.
>>
>> While populating gmbus register we ensure that unused ports
>> will have gpio_reg value set as 0. This patch ensures that
>> only those with non zero gpio reg will get registered as i2c
>> adapter and this is applicable for all platforms.
>>
>> del_adapter will check if the adaptor was really added
>> before, still its better to avoid unnecessary calls to the same.
>> This patch also adds a check to deregister only added i2c adapters.
>>
>> Tested using i2c-tools to confirm that only valid gmbus ports
>> are registered as i2c adapter.
>>
>> BXT will have only valid i2c adapters as below:
>> i2c-x      i2c     i915 gmbus dpc      I2C adapter
>> i2c-x+1    i2c     i915 gmbus dpb      I2C adapter
>> i2c-x+2    i2c     i915 gmbus misc     I2C adapter
>>
>> v1: This patch is added as per review comments from
>> Daniel Vetter on gmbus BXT patch
>>
>> Issue: VIZ-3574
>> Signed-off-by: A.Sunil Kamath <sunil.kamath@intel.com>
>> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
>> ---
>>  drivers/gpu/drm/i915/intel_i2c.c | 15 ++++++++++-----
>>  1 file changed, 10 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
>> index 06892b5..d5ca310 100644
>> --- a/drivers/gpu/drm/i915/intel_i2c.c
>> +++ b/drivers/gpu/drm/i915/intel_i2c.c
>> @@ -599,9 +599,12 @@ int intel_setup_gmbus(struct drm_device *dev)
>>  
>>  		intel_gpio_setup(bus, port);
>>  
>> -		ret = i2c_add_adapter(&bus->adapter);
>> -		if (ret)
>> -			goto err;
>> +		/* Do not register unused gmbus ports as i2c adapter */
>> +		if (bus->gpio_reg) {
>
> This works by accident, as bus->gpio_reg will contain
> dev_priv->gpio_mmio_base even if the reg is 0. Luckily for BXT this is
> the case.
>
> I think the question is, why do we initialize anything for
> dev_priv->gmbus[i] where i is an unused pin pair? I think we should have
> the validity check at the top, and if (invalid) continue;.
>
> I care because we appear to be registering unused adapters also on other
> recent platforms, and we should fix that too. That doesn't have to be
> part of bxt enabling, but I don't like adding broken stuff that makes
> future work harder.

Okay, so I ended up fixing this myself [1], replacing patches 20, 21,
and 22 of this series.

BR,
Jani.

[1] http://mid.gmane.org/cover.1427407523.git.jani.nikula@intel.com



>
> BR,
> Jani.
>
>
>
>> + ret = i2c_add_adapter(&bus->adapter); + if (ret) + goto err; + } }
>>  
>>  	intel_i2c_reset(dev_priv->dev);
>> @@ -611,7 +614,8 @@ int intel_setup_gmbus(struct drm_device *dev)
>>  err:
>>  	while (--i) {
>>  		struct intel_gmbus *bus = &dev_priv->gmbus[i];
>> -		i2c_del_adapter(&bus->adapter);
>> +		if (bus->gpio_reg)
>> +			i2c_del_adapter(&bus->adapter);
>>  	}
>>  	return ret;
>>  }
>> @@ -652,6 +656,7 @@ void intel_teardown_gmbus(struct drm_device *dev)
>>  
>>  	for (i = 0; i < GMBUS_NUM_PORTS; i++) {
>>  		struct intel_gmbus *bus = &dev_priv->gmbus[i];
>> -		i2c_del_adapter(&bus->adapter);
>> +		if (bus->gpio_reg)
>> +			i2c_del_adapter(&bus->adapter);
>>  	}
>>  }
>> -- 
>> 2.1.0
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> -- 
> Jani Nikula, Intel Open Source Technology Center

-- 
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[PATCH v2] drm/i915/bxt: map GTT as uncached

[Imre Deak]

On Broxton per specification the GTT has to be mapped as uncached.
This was caught by the PTE write readback warning, which showed a
corrupted PTE value with using the current write-combine mapping.

v2:
- add comment explaining how the problem with WC mapping manifests
  (Daniel)

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index e33b121..4d15237 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2256,7 +2256,17 @@ static int ggtt_probe_common(struct drm_device *dev,
 	gtt_phys_addr = pci_resource_start(dev->pdev, 0) +
 		(pci_resource_len(dev->pdev, 0) / 2);
 
-	dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size);
+	/*
+	 * On BXT writes larger than 64 bit to the GTT pagetable range will be
+	 * dropped. For WC mappings in general we have 64 byte burst writes
+	 * when the WC buffer is flushed, so we can't use it, but have to
+	 * resort to an uncached mapping. The WC issue is easily caught by the
+	 * readback check when writing GTT PTE entries.
+	 */
+	if (IS_BROXTON(dev))
+		dev_priv->gtt.gsm = ioremap_nocache(gtt_phys_addr, gtt_size);
+	else
+		dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size);
 	if (!dev_priv->gtt.gsm) {
 		DRM_ERROR("Failed to map the gtt page table\n");
 		return -ENOMEM;
-- 
2.1.0

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[PATCH v2 13/49] drm/i915/bxt: add bxt_init_clock_gating

[Imre Deak]

v2:
- Make the condition to select between SKL and BXT consistent with the
  corresponding condition in init_workarounds_ring (Nick)

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index c52f8b7..8a8d52a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -94,6 +94,11 @@ static void skl_init_clock_gating(struct drm_device *dev)
 			   GEN8_LQSC_RO_PERF_DIS);
 }
 
+static void bxt_init_clock_gating(struct drm_device *dev)
+{
+	gen9_init_clock_gating(dev);
+}
+
 static void i915_pineview_get_mem_freq(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -6548,7 +6553,12 @@ void intel_init_pm(struct drm_device *dev)
 	if (INTEL_INFO(dev)->gen >= 9) {
 		skl_setup_wm_latency(dev);
 
-		dev_priv->display.init_clock_gating = skl_init_clock_gating;
+		if (IS_BROXTON(dev))
+			dev_priv->display.init_clock_gating =
+				bxt_init_clock_gating;
+		else if (IS_SKYLAKE(dev))
+			dev_priv->display.init_clock_gating =
+				skl_init_clock_gating;
 		dev_priv->display.update_wm = skl_update_wm;
 		dev_priv->display.update_sprite_wm = skl_update_sprite_wm;
 	} else if (HAS_PCH_SPLIT(dev)) {
-- 
2.1.0

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[PATCH v2 23/49] drm/i915/bxt: Increase DDI buf idle timeout

[Imre Deak]

From: Vandana Kannan <vandana.kannan@intel.com>

For BXT, DDI buf idle timeout delay needs to be increased to 16us.

Since this is a timeout value and we return as soon as the condition is
realized, no penalty incurred for other platforms.

v2:
- remove TIMEOUT macro used only at a single place (Daniel)

Suggested-by: Satheeshakrishna M <satheeshakrishna.m@intel.com>
Cc: Satheeshakrishna M <satheeshakrishna.m@intel.com>
Cc: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> (v1)
---
 drivers/gpu/drm/i915/intel_ddi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 8aee7d7..e24cd6f 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -322,7 +322,7 @@ static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
 	uint32_t reg = DDI_BUF_CTL(port);
 	int i;
 
-	for (i = 0; i < 8; i++) {
+	for (i = 0; i < 16; i++) {
 		udelay(1);
 		if (I915_READ(reg) & DDI_BUF_IS_IDLE)
 			return;
-- 
2.1.0

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[PATCH v6 24/49] drm/i915/bxt: DDI Hotplug interrupt setup

[Imre Deak]

From: Shashank Sharma <shashank.sharma@intel.com>

In BXT, DDI hotplug control has been moved to CPU from PCH.
This patch adds a new IRQ setup function for BXT which:
1. Checks which HPD ports are requested to be enabled by encoders.
2. Enables those ports in the hot plug control register.
3. Un-masks these port interrupts in the IMR register.
4. Enables these port interrupts in the IER register.

V3: Kept the default HPD filter count to default (500 us) as per
    satheesh's comment
v4: Remove unused HPD filter defines (Damien)
v5: warn if trying to setup HPD on port A (imre)
v6: fix order of definitions for register bitfields (Daniel)

Reviewed-by: Satheeshakrishna M <satheeshakrishna.m@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com> (v4)
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 49 ++++++++++++++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/i915_reg.h | 25 ++++++++++++++++++++-
 2 files changed, 72 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 14ecb4d..d09b389 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -88,6 +88,12 @@ static const u32 hpd_status_i915[HPD_NUM_PINS] = { /* i915 and valleyview are th
 	[HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
 };
 
+/* BXT hpd list */
+static const u32 hpd_bxt[] = {
+	[HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
+	[HPD_PORT_C] = BXT_DE_PORT_HP_DDIC
+};
+
 /* IIR can theoretically queue up two events. Be paranoid. */
 #define GEN8_IRQ_RESET_NDX(type, which) do { \
 	I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
@@ -3178,6 +3184,44 @@ static void ibx_hpd_irq_setup(struct drm_device *dev)
 	I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
 }
 
+static void bxt_hpd_irq_setup(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_mode_config *mode_config = &dev->mode_config;
+	struct intel_encoder *intel_encoder;
+	u32 hotplug_port = 0;
+	u32 hotplug_ctrl;
+
+	/* Now, enable HPD */
+	list_for_each_entry(intel_encoder, &mode_config->encoder_list,
+		base.head) {
+		if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark
+				== HPD_ENABLED)
+			hotplug_port |= hpd_bxt[intel_encoder->hpd_pin];
+	}
+
+	/* Mask all HPD control bits */
+	hotplug_ctrl = I915_READ(BXT_HOTPLUG_CTL) & ~BXT_HOTPLUG_CTL_MASK;
+
+	/* Enable requested port in hotplug control */
+	/* TODO: implement (short) HPD support on port A */
+	WARN_ON_ONCE(hotplug_port & BXT_DE_PORT_HP_DDIA);
+	if (hotplug_port & BXT_DE_PORT_HP_DDIB)
+		hotplug_ctrl |= BXT_DDIB_HPD_ENABLE;
+	if (hotplug_port & BXT_DE_PORT_HP_DDIC)
+		hotplug_ctrl |= BXT_DDIC_HPD_ENABLE;
+	I915_WRITE(BXT_HOTPLUG_CTL, hotplug_ctrl);
+
+	/* Unmask DDI hotplug in IMR */
+	hotplug_ctrl = I915_READ(GEN8_DE_PORT_IMR) & ~hotplug_port;
+	I915_WRITE(GEN8_DE_PORT_IMR, hotplug_ctrl);
+
+	/* Enable DDI hotplug in IER */
+	hotplug_ctrl = I915_READ(GEN8_DE_PORT_IER) | hotplug_port;
+	I915_WRITE(GEN8_DE_PORT_IER, hotplug_ctrl);
+	POSTING_READ(GEN8_DE_PORT_IER);
+}
+
 static void ibx_irq_postinstall(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -4298,7 +4342,10 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
 		dev->driver->irq_uninstall = gen8_irq_uninstall;
 		dev->driver->enable_vblank = gen8_enable_vblank;
 		dev->driver->disable_vblank = gen8_disable_vblank;
-		dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
+		if (HAS_PCH_SPLIT(dev))
+			dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
+		else
+			dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
 	} else if (HAS_PCH_SPLIT(dev)) {
 		dev->driver->irq_handler = ironlake_irq_handler;
 		dev->driver->irq_preinstall = ironlake_irq_reset;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6a5ade6..a082d7d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5240,10 +5240,16 @@ enum skl_disp_power_wells {
 #define GEN8_DE_PORT_IMR 0x44444
 #define GEN8_DE_PORT_IIR 0x44448
 #define GEN8_DE_PORT_IER 0x4444c
-#define  GEN8_PORT_DP_A_HOTPLUG		(1 << 3)
 #define  GEN9_AUX_CHANNEL_D		(1 << 27)
 #define  GEN9_AUX_CHANNEL_C		(1 << 26)
 #define  GEN9_AUX_CHANNEL_B		(1 << 25)
+#define  BXT_DE_PORT_HP_DDIC		(1 << 5)
+#define  BXT_DE_PORT_HP_DDIB		(1 << 4)
+#define  BXT_DE_PORT_HP_DDIA		(1 << 3)
+#define  BXT_DE_PORT_HOTPLUG_MASK	(BXT_DE_PORT_HP_DDIA | \
+					 BXT_DE_PORT_HP_DDIB | \
+					 BXT_DE_PORT_HP_DDIC)
+#define  GEN8_PORT_DP_A_HOTPLUG		(1 << 3)
 #define  GEN8_AUX_CHANNEL_A		(1 << 0)
 
 #define GEN8_DE_MISC_ISR 0x44460
@@ -5257,6 +5263,23 @@ enum skl_disp_power_wells {
 #define GEN8_PCU_IIR 0x444e8
 #define GEN8_PCU_IER 0x444ec
 
+/* BXT hotplug control */
+#define BXT_HOTPLUG_CTL			0xC4030
+#define BXT_DDIA_HPD_ENABLE		(1 << 28)
+#define BXT_DDIC_HPD_ENABLE		(1 << 12)
+#define BXT_DDIB_HPD_ENABLE		(1 << 4)
+#define BXT_HOTPLUG_CTL_MASK		(BXT_DDIA_HPD_ENABLE | \
+					 BXT_DDIB_HPD_ENABLE | \
+					 BXT_DDIC_HPD_ENABLE)
+
+/* Hot plug status */
+#define BXT_DDIA_HPD_STATUS		(3 << 24)
+#define BXT_DDIC_HPD_STATUS		(3 << 8)
+#define BXT_DDIB_HPD_STATUS		(3 << 0)
+#define BXT_HPD_STATUS_MASK		(BXT_DDIA_HPD_STATUS | \
+					 BXT_DDIB_HPD_STATUS | \
+					 BXT_DDIC_HPD_STATUS)
+
 #define ILK_DISPLAY_CHICKEN2	0x42004
 /* Required on all Ironlake and Sandybridge according to the B-Spec. */
 #define  ILK_ELPIN_409_SELECT	(1 << 25)
-- 
2.1.0

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[PATCH 25.1/49] drm/i915/bxt: support for HPD long/short status decoding

[Imre Deak]

All non-GMCH platforms have the same register layout for HPD long/short
status, so let's use this condition instead of HAS_PCH_SPLIT, as the
latter doesn't apply for BXT.

Noticed by Daniel.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 4833e2b..17eed72 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1446,7 +1446,7 @@ static inline void intel_hpd_irq_handler(struct drm_device *dev,
 		if (port && dev_priv->hpd_irq_port[port]) {
 			bool long_hpd;
 
-			if (HAS_PCH_SPLIT(dev)) {
+			if (!HAS_GMCH_DISPLAY(dev_priv)) {
 				dig_shift = pch_port_to_hotplug_shift(port);
 				long_hpd = (dig_hotplug_reg >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT;
 			} else {
-- 
2.1.0

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Re: [PATCH v2] drm/i915/bxt: map GTT as uncached

[Antti Koskipää]

Reviewed-by: Antti Koskipää <antti.koskipaa@linux.intel.com>

On 03/27/2015 01:07 PM, Imre Deak wrote:
> On Broxton per specification the GTT has to be mapped as uncached.
> This was caught by the PTE write readback warning, which showed a
> corrupted PTE value with using the current write-combine mapping.
> 
> v2:
> - add comment explaining how the problem with WC mapping manifests
>   (Daniel)
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_gem_gtt.c | 12 +++++++++++-
>  1 file changed, 11 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index e33b121..4d15237 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -2256,7 +2256,17 @@ static int ggtt_probe_common(struct drm_device *dev,
>  	gtt_phys_addr = pci_resource_start(dev->pdev, 0) +
>  		(pci_resource_len(dev->pdev, 0) / 2);
>  
> -	dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size);
> +	/*
> +	 * On BXT writes larger than 64 bit to the GTT pagetable range will be
> +	 * dropped. For WC mappings in general we have 64 byte burst writes
> +	 * when the WC buffer is flushed, so we can't use it, but have to
> +	 * resort to an uncached mapping. The WC issue is easily caught by the
> +	 * readback check when writing GTT PTE entries.
> +	 */
> +	if (IS_BROXTON(dev))
> +		dev_priv->gtt.gsm = ioremap_nocache(gtt_phys_addr, gtt_size);
> +	else
> +		dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size);
>  	if (!dev_priv->gtt.gsm) {
>  		DRM_ERROR("Failed to map the gtt page table\n");
>  		return -ENOMEM;
> 

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Re: [PATCH 02/49] drm/i915/bxt: BXT FBC enablement

[Antti Koskipää]

Reviewed-by: Antti Koskipää <antti.koskipaa@linux.intel.com>

On 03/17/2015 11:39 AM, Imre Deak wrote:
> From: Daisy Sun <daisy.sun@intel.com>
> 
> Enable FBC feature on Broxton
> 
> Issue: VIZ-3784
> Signed-off-by: Daisy Sun <daisy.sun@intel.com>
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 4d50785..48434cb6 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -388,6 +388,7 @@ static const struct intel_device_info intel_broxton_info = {
>  	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
>  	.num_pipes = 3,
>  	.has_ddi = 1,
> +	.has_fbc = 1,
>  	GEN_DEFAULT_PIPEOFFSETS,
>  	IVB_CURSOR_OFFSETS,
>  };
> 

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Re: [PATCH 02/49] drm/i915/bxt: BXT FBC enablement

[Antti Koskipää]

Reviewed-by: Antti Koskipää <antti.koskipaa@linux.intel.com>

On 03/17/2015 11:39 AM, Imre Deak wrote:
> From: Daisy Sun <daisy.sun@intel.com>
> 
> Enable FBC feature on Broxton
> 
> Issue: VIZ-3784
> Signed-off-by: Daisy Sun <daisy.sun@intel.com>
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 4d50785..48434cb6 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -388,6 +388,7 @@ static const struct intel_device_info intel_broxton_info = {
>  	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
>  	.num_pipes = 3,
>  	.has_ddi = 1,
> +	.has_fbc = 1,
>  	GEN_DEFAULT_PIPEOFFSETS,
>  	IVB_CURSOR_OFFSETS,
>  };
> 

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Re: [PATCH 02.1/49] drm/i915: use proper FBC base register on all new platforms

[Antti Koskipää]

Reviewed-by: Antti Koskipää <antti.koskipaa@linux.intel.com>

On 03/26/2015 05:35 PM, Imre Deak wrote:
> Starting from GEN5 the FBC base register is the same on all platforms.
> GEN>=5 is the same condition as HAS_PCH_SPLIT except on BXT, so make
> things work on BXT as well.
> 
> Motivated by Rodrigo's request to check FBC support on BXT.
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_gem_stolen.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c
> index f8da716..348ed5a 100644
> --- a/drivers/gpu/drm/i915/i915_gem_stolen.c
> +++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
> @@ -209,7 +209,7 @@ static int i915_setup_compression(struct drm_device *dev, int size, int fb_cpp)
>  
>  	dev_priv->fbc.threshold = ret;
>  
> -	if (HAS_PCH_SPLIT(dev))
> +	if (INTEL_INFO(dev_priv)->gen >= 5)
>  		I915_WRITE(ILK_DPFC_CB_BASE, dev_priv->fbc.compressed_fb.start);
>  	else if (IS_GM45(dev)) {
>  		I915_WRITE(DPFC_CB_BASE, dev_priv->fbc.compressed_fb.start);
> 

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[PATCH 33/49] drm/i915/bxt: Add DC9 Trigger sequence

[sagar.a.kamble]

+static int bxt_suspend_complete(struct drm_i915_private *dev_priv)
+{
+       struct drm_device *dev = dev_priv->dev;
+
+       /* TODO: when DC5 support is added disable DC5 here. */
+
+       bxt_uninit_cdclk(dev);
+       bxt_enable_dc9(dev_priv);
+
+       return 0;
+}
+
 static int hsw_suspend_complete(struct drm_i915_private *dev_priv)
 {
        hsw_enable_pc8(dev_priv);
@@ -1009,6 +1021,20 @@ static int hsw_suspend_complete(struct
drm_i915_private *dev_priv)
        return 0;
 }
 
+static int bxt_resume_prepare(struct drm_i915_private *dev_priv)
+{
+       struct drm_device *dev = dev_priv->dev;
+
+       /* TODO: When CSR FW support is added make sure the FW is loaded. */
+
+       bxt_disable_dc9(dev_priv);
Kindly add below comment as well:
/* TODO: when DC5 support is added enable DC5 here if conditions are
met. */
+       bxt_init_cdclk(dev);
+       bxt_ddi_phy_init(dev);
+       intel_prepare_ddi(dev);
+
+       return 0;
+}
+
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Re: [PATCH 06/49] drm/i915/bxt: Broxton has 3 sprite planes on pipe A/B, 2 on pipe C

[Daniel Vetter]

On Tue, Mar 17, 2015 at 11:39:32AM +0200, Imre Deak wrote:
> From: Damien Lespiau <damien.lespiau@intel.com>
> 
> v2: Rebase on top of the for_each_pipe() change adding dev_priv as first
>     argument.
> 
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_dma.c | 6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index d49ed68..a94a970 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -585,7 +585,11 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
>  
>  	info = (struct intel_device_info *)&dev_priv->info;
>  
> -	if (IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen == 9)
> +	if (IS_BROXTON(dev)) {
> +		info->num_sprites[PIPE_A] = 3;
> +		info->num_sprites[PIPE_B] = 3;
> +		info->num_sprites[PIPE_C] = 2;

Same todo as with skl: The last sprite plane is actually also the cursor,
and we really shouldn't expose both. Damien is signed up to fix that since
I don't want to drop the prelim_hw_support label for skl before we fix
this abi issue.
-Daniel

> +	} else if (IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen == 9)
>  		for_each_pipe(dev_priv, pipe)
>  			info->num_sprites[pipe] = 2;
>  	else
> -- 
> 2.1.0
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [PATCH 30/49] drm/i915/bxt: add display initialize/uninitialize sequence

[Ville Syrjälä]

On Tue, Mar 17, 2015 at 11:39:56AM +0200, Imre Deak wrote:
> From: Vandana Kannan <vandana.kannan@intel.com>
> 
> Add display clock/PHY initialization sequence as per BSpec.
> 
> Until GOP/VBIOS provides an upper limit value for CDCLK, comparing clock
> value with 624 MHz and returning 0 in case it exceeds.
> 
> Note that the CD clock and PHY initialization/uninitialization are done
> at their current place only for simplicity, in a future patch - when more
> of the runtime PM features will be enabled - these will be moved to
> power well#1 and modeset encoder enabling/disabling hooks respectively.
> This also means that atm dynamic power gating power well #2 is
> effectively disabled.

OK, I've gone through the PHY stuff a bit now, and skipped the cdclk
stuff this time.

> 
> v1: Added function definitions in header files
> v2: Imre's review comments addressed
> - Moved CDCLK related definitions to i915_reg.h
> - Removed defintions for CDCLK frequency
> - Split uninit_cdclk() by adding a phy_uninit function
> - Calculate freq and decimal based on input frequency
> - Program SSA precharge based on input frequency
> - Use wait_for 1ms instead 200us udelay for DE PLL locking
> - Removed initial value for divider, freq, decimal, ratio.
> - Replaced polling loops with wait_for
> - Parameterized latency optim setting
> - Fix the parts where DE PLL has to be disabled.
> - Call CDCLK selection from mode set
> 
> v3: (imre)
> - add note about the plan to move the cdclk/phy init to a better place
> - take rps.hw_lock around pcode access
> - fix DDI PHY timeout value
> - squash in Vandana's "PORT_CL2CM_DW6_A BUN fix",
>   "DDI PHY programming register defn", "Do ddi_phy_init always",
>   "Check CDCLK upper limit" patches
> - move PHY register macros next to the corresponding CHV/VLV macros
> - move DE PLL register macros here from another patch since they are
>   used here first
> - add BXT_ prefix to CDCLK flags
> - s/COMMON_RESET/COMMON_RESET_DIS/ and clarify related code comments
> - fix incorrect read value for the RMW of BXT_PHY_CTL_FAMILY_DDI
> - fix using GT_DISPLAY_EDP_POWER_ON vs. GT_DISPLAY_DDI_POWER_ON
>   when powering on DDI ports
> - fix incorrect port when setting BXT_PORT_TX_DW14_LN for DDI ports
> - add missing masking when programming CDCLK_FREQ_DECIMAL
> - add missing powering on for DDI-C port, rename OCL2_LDOFUSE_PWR_EN
>   to OCL2_LDOFUSE_PWR_DIS to reduce confusion
> - add note about mismatch with bspec in the PORT_REF_DW6 fields
> - factor out PHY init code to a new function, so we can call it for
>   PHY_A and PHY_BC, instead of open-coding the same
> 
> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> (v2)
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h      | 126 +++++++++++++++
>  drivers/gpu/drm/i915/intel_ddi.c     | 291 +++++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_display.c |  75 +++++++++
>  drivers/gpu/drm/i915/intel_drv.h     |   4 +
>  4 files changed, 496 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b4474d3..a3579c0 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1120,6 +1120,110 @@ enum skl_disp_power_wells {
>  #define   DPIO_FRC_LATENCY_SHFIT	8
>  #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
>  #define   DPIO_UPAR_SHIFT		30
> +
> +/* BXT PHY registers */
> +enum bxt_phy {
> +	BXT_PHY_A,
> +	BXT_PHY_BC
> +};

We have enum dpio_phy already. Although here we have defined 0 to be the
single channel PHY and 1 is the two channel PHY,  whereas on CHV it's
the other way around. I'm going to suggest we flip BXT over to use the
CHV scheme to avoid any surpises later if we actualy try to unify the
code.

> +
> +#define BXT_PHY(phy, a, b)		((a) + (phy) * ((b) - (a)))

This seems to be just another _PIPE(), should at least have an
underscore so that people don't confuse it with something they are
supposed to use.

> +
> +#define BXT_P_CR_GT_DISP_PWRON_0_2_0_GTTMMADR	0x138090

We can drop the _0_2_0_GTTMMADR suffix, we've never included it for any
other platforms either.

> +#define   _EDP_POWER_ON				(1 << 1)
> +#define   _DDI_POWER_ON				(1 << 0)
> +#define   GT_DISPLAY_POWER_ON(phy)		BXT_PHY(phy, _EDP_POWER_ON, \
> +							_DDI_POWER_ON)

Using a _PIPE() type of macro for register bits seems a bit unusual.
I'd just open code it as (1 << (phy)) or something. That also work
better if we the PHYs around so that PHY0 is the dual channel PHY.

> +
> +#define _PHY_CTL_FAMILY_EDP		0x64C80
> +#define _PHY_CTL_FAMILY_DDI		0x64C90
> +#define   COMMON_RESET_DIS		(1 << 31)
> +#define BXT_PHY_CTL_FAMILY(phy)		BXT_PHY(phy, _PHY_CTL_FAMILY_EDP, \
> +						     _PHY_CTL_FAMILY_DDI)
> +
> +/* BXT PHY common lane registers */
> +#define _PORT_CL1CM_DW0_A		0x162000
> +#define _PORT_CL1CM_DW0_BC		0x6C000
> +#define   PHY_POWER_GOOD		(1 << 16)
> +#define BXT_PORT_CL1CM_DW0(phy)		BXT_PHY(phy, _PORT_CL1CM_DW0_A,	\
> +						     _PORT_CL1CM_DW0_BC)

I'm a bit sad these are not sharing the CHV reg defines, or even
resemble them in any way.

> +
> +#define _PORT_CL1CM_DW9_A		0x162024
> +#define _PORT_CL1CM_DW9_BC		0x6C024
> +#define   IREF0RC_OFFSET_SHIFT		8
> +#define   IREF0RC_OFFSET_MASK		(0xFF << IREF0RC_OFFSET_SHIFT)
> +#define BXT_PORT_CL1CM_DW9(phy)		BXT_PHY(phy, _PORT_CL1CM_DW9_A,	\
> +						     _PORT_CL1CM_DW9_BC)
> +
> +#define _PORT_CL1CM_DW10_A		0x162028
> +#define _PORT_CL1CM_DW10_BC		0x6C028
> +#define   IREF1RC_OFFSET_SHIFT		8
> +#define   IREF1RC_OFFSET_MASK		(0xFF << IREF1RC_OFFSET_SHIFT)
> +#define BXT_PORT_CL1CM_DW10(phy)	BXT_PHY(phy, _PORT_CL1CM_DW10_A, \
> +						     _PORT_CL1CM_DW10_BC)
> +
> +#define _PORT_CL1CM_DW28_A		0x162070
> +#define _PORT_CL1CM_DW28_BC		0x6C070
> +#define   OCL1_POWER_DOWN_EN		(1 << 23)
> +#define   DW28_OLDO_DYN_PWR_DOWN_EN	(1 << 22)
> +#define   SUS_CLK_CONFIG		0x3
> +#define BXT_PORT_CL1CM_DW28(phy)	BXT_PHY(phy, _PORT_CL1CM_DW28_A, \
> +						     _PORT_CL1CM_DW28_BC)
> +
> +#define _PORT_CL1CM_DW30_A		0x162078
> +#define _PORT_CL1CM_DW30_BC		0x6C078
> +#define   OCL2_LDOFUSE_PWR_DIS		(1 << 6)
> +#define BXT_PORT_CL1CM_DW30(phy)	BXT_PHY(phy, _PORT_CL1CM_DW30_A, \
> +						     _PORT_CL1CM_DW30_BC)
> +
> +/* Defined for PHY_BC only */
> +#define BXT_PORT_CL2CM_DW6_BC		0x6C358
> +#define   DW6_OLDO_DYN_PWR_DOWN_EN	(1 << 28)
> +
> +/* BXT PHY Ref registers */
> +#define _PORT_REF_DW3_A			0x16218C
> +#define _PORT_REF_DW3_BC		0x6C18C
> +#define   GRC_DONE			(1 << 22)
> +#define BXT_PORT_REF_DW3(phy)		BXT_PHY(phy, _PORT_REF_DW3_A,	\
> +						     _PORT_REF_DW3_BC)
> +
> +#define _PORT_REF_DW6_A			0x162198
> +#define _PORT_REF_DW6_BC		0x6C198
> +/*
> + * FIXME: BSpec disagrees on the following two fields, check them with
> + * HW/documentation people.
> + */

CHV configdb also disagrees.

> +#define   GRC_CODE_SHIFT		23
> +#define   GRC_CODE_MASK			(0x1FF << GRC_CODE_SHIFT)
> +#define   GRC_CODE_FAST_SHIFT		16
> +#define   GRC_CODE_FAST_MASK		(0x7F << GRC_CODE_FAST_SHIFT)
> +#define   GRC_CODE_SLOW_SHIFT		8
> +#define   GRC_CODE_SLOW_MASK		(0xFF << GRC_CODE_SLOW_SHIFT)
> +#define   GRC_CODE_NOM_MASK		0xFF
> +#define BXT_PORT_REF_DW6(phy)		BXT_PHY(phy, _PORT_REF_DW6_A,	\
> +						     _PORT_REF_DW6_BC)
> +
> +#define _PORT_REF_DW8_A			0x1621A0
> +#define _PORT_REF_DW8_BC		0x6C1A0
> +#define   GRC_DIS			(1 << 15)
> +#define   GRC_RDY_OVRD			(1 << 1)
> +#define BXT_PORT_REF_DW8(phy)		BXT_PHY(phy, _PORT_REF_DW8_A,	\
> +						     _PORT_REF_DW8_BC)
> +
> +/* BXT PHY TX registers */
> +#define BXT_LANE_OFFSET(lane)           (((lane) >> 1) * 0x200 +	\
> +					 ((lane) & 1) * 0x80)
> +
> +#define _PORT_TX_DW14_LN0_A		0x162538
> +#define _PORT_TX_DW14_LN0_B		0x6C538
> +#define _PORT_TX_DW14_LN0_C		0x6C938
> +#define   LATENCY_OPTIM_SHIFT		30
> +#define   LATENCY_OPTIM			(1 << LATENCY_OPTIM_SHIFT)
> +#define BXT_PORT_TX_DW14_LN(port, lane)	(_PORT3(port, _PORT_TX_DW14_LN0_A,   \
> +						      _PORT_TX_DW14_LN0_B,   \
> +						      _PORT_TX_DW14_LN0_C) + \
> +					 BXT_LANE_OFFSET(lane))
> +
>  /*
>   * Fence registers
>   */
> @@ -5326,6 +5430,9 @@ enum skl_disp_power_wells {
>  #define  DISP_FBC_WM_DIS		(1<<15)
>  #define DISP_ARB_CTL2	0x45004
>  #define  DISP_DATA_PARTITION_5_6	(1<<6)
> +#define DBUF_CTL	0x45008
> +#define  DBUF_POWER_REQUEST		(1<<31)
> +#define  DBUF_POWER_STATE		(1<<30)
>  #define GEN7_MSG_CTL	0x45010
>  #define  WAIT_FOR_PCH_RESET_ACK		(1<<1)
>  #define  WAIT_FOR_PCH_FLR_ACK		(1<<0)
<snip>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index a203d9d..789682d 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1957,6 +1957,294 @@ static void skl_shared_dplls_init(struct drm_i915_private *dev_priv)
>  	}
>  }
>  
> +static void bxt_init_phy(struct drm_i915_private *dev_priv, enum bxt_phy phy)
> +{
> +	enum port port;
> +	uint32_t val;
> +
> +	val = I915_READ(BXT_P_CR_GT_DISP_PWRON_0_2_0_GTTMMADR);
> +	val |= GT_DISPLAY_POWER_ON(phy);
> +	I915_WRITE(BXT_P_CR_GT_DISP_PWRON_0_2_0_GTTMMADR, val);
> +
> +	/* Considering 10ms timeout until BSpec is updated */
> +	if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10))
> +		DRM_ERROR("timeout during PHY#%d power on\n", phy);
> +
> +	/* Program latency optim setting */
> +	for (port =  (phy == BXT_PHY_A ? PORT_A : PORT_B);
> +	     port <= (phy == BXT_PHY_A ? PORT_A : PORT_C); port++) {
> +		int lane;
> +
> +		for (lane = 0; lane < 4; lane++) {
> +			val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
> +			val &= ~LATENCY_OPTIM;
> +			if (lane == 1)

Should be != 1

> +				val |= LATENCY_OPTIM;
> +
> +			I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val);
> +		}
> +	}
> +
> +	/* Program PLL Rcomp code offset */
> +	val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
> +	val &= ~IREF0RC_OFFSET_MASK;
> +	val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
> +	I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
> +
> +	val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
> +	val &= ~IREF1RC_OFFSET_MASK;
> +	val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
> +	I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
> +
> +	/* Program power gating */
> +	val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
> +	val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
> +		SUS_CLK_CONFIG;
> +	I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
> +
> +	if (phy == BXT_PHY_BC) {
> +		val = I915_READ(BXT_PORT_CL2CM_DW6_BC);
> +		val |= DW6_OLDO_DYN_PWR_DOWN_EN;
> +		I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val);
> +	}
> +
> +	val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
> +	val &= ~OCL2_LDOFUSE_PWR_DIS;
> +	/*
> +	 * On PHY_A disable power on the second channel, since no port is
> +	 * connected there. On PHY_BC both channels have a port, so leave it
> +	 * enabled.
> +	 * Note that port C is only connected on BXT-P, so on BXT0/1 we should
> +	 * power down the second channel on PHY_BC as well.
> +	 */
> +	if (phy == BXT_PHY_A)
> +		val |= OCL2_LDOFUSE_PWR_DIS;
> +	I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
> +
> +	if (phy == BXT_PHY_BC) {
> +		uint32_t grc_code;
> +		/*
> +		 * PHY_BC isn't connected to an RCOMP resistor so copy over
> +		 * the corresponding calibrated value from PHY_A, and disable
> +		 * the automatic calibration on PHY_BC.
> +		 */
> +		if (wait_for(I915_READ(BXT_PORT_REF_DW3(BXT_PHY_A)) & GRC_DONE,
> +			     10))
> +			DRM_ERROR("timeout waiting for PHY#0 GRC\n");
> +
> +		val = I915_READ(BXT_PORT_REF_DW6(BXT_PHY_A));
> +		val = (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
> +		grc_code = val << GRC_CODE_FAST_SHIFT |
> +			   val << GRC_CODE_SLOW_SHIFT |
> +			   val;
> +		I915_WRITE(BXT_PORT_REF_DW6(BXT_PHY_BC), grc_code);
> +
> +		val = I915_READ(BXT_PORT_REF_DW8(BXT_PHY_BC));
> +		val |= GRC_DIS | GRC_RDY_OVRD;
> +		I915_WRITE(BXT_PORT_REF_DW8(BXT_PHY_BC), val);
> +	}
> +
> +	/* Release common_reset */
> +	val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
> +	val |= COMMON_RESET_DIS;
> +	I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
> +}

I suppose we'll want to model this thing as a power well like on CHV
eventually, but I guess we can start off with initializing it once.

> +
> +void bxt_ddi_phy_init(struct drm_device *dev)
> +{
> +	/* Enable PHY_A first since it provides Rcomp for PHY_BC */
> +	bxt_init_phy(dev->dev_private, BXT_PHY_A);
> +	bxt_init_phy(dev->dev_private, BXT_PHY_BC);
> +}
> +
> +static void bxt_ddi_phy_uninit(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	uint32_t temp;
> +
> +	temp = I915_READ(BXT_PHY_CTL_FAMILY(BXT_PHY_A));
> +	I915_WRITE(BXT_PHY_CTL_FAMILY(BXT_PHY_A), temp & ~COMMON_RESET_DIS);
> +
> +	temp = I915_READ(BXT_PHY_CTL_FAMILY(BXT_PHY_BC));
> +	I915_WRITE(BXT_PHY_CTL_FAMILY(BXT_PHY_BC), temp & ~COMMON_RESET_DIS);
> +
> +	I915_WRITE(BXT_P_CR_GT_DISP_PWRON_0_2_0_GTTMMADR, 0);
> +}

This should really be per-phy to avoid confusion when comparing with the
init function.

> +
<snip>
> +
> +void bxt_init_cdclk(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +
> +	/* NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
> +	 * or else the reset will hang because there is no PCH to respond.
> +	 * Move the handshake programming to initialization sequence.
> +	 * Previously was left up to BIOS.
> +	 */
> +	u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
> +
> +	temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
> +	I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
> +
> +	/* Enable PG1 for cdclk */
> +	intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
> +
> +	/* check if cd clock is enabled */
> +	if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
> +		DRM_DEBUG_KMS("Display already initialized\n");
> +		return;
> +	}
> +
> +	/* FIXME:- The initial CDCLK needs to be read from VBT.
> +	 * Need to make this change after VBT has changes for BXT.
> +	 */
> +	bxt_select_cdclk_freq(dev, 624000);
> +
> +	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
> +	udelay(10);
> +
> +	if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
> +		DRM_ERROR("DBuf power enable timeout!\n");
> +}

This code seems like power well territory again. Just stuffing it into
PG1 would seem like a good enough solution judging by the fact that we
hold the PG1 reference as long as we have the DBUF power request enabled.

Or are there actual uses for having PG1 enabled w/o this thing?

> +
> +void bxt_uninit_cdclk(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +
> +	bxt_ddi_phy_uninit(dev);
> +
> +	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
> +	udelay(10);
> +
> +	if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
> +		DRM_ERROR("DBuf power disable timeout!\n");
> +
> +	bxt_select_cdclk_freq(dev, 0);
> +
> +	intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
> +}
> +
>  void intel_ddi_pll_init(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -1973,6 +2261,9 @@ void intel_ddi_pll_init(struct drm_device *dev)
>  	if (IS_SKYLAKE(dev)) {
>  		if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
>  			DRM_ERROR("LCPLL1 is disabled\n");
> +	} else if (IS_BROXTON(dev)) {
> +		bxt_init_cdclk(dev);
> +		bxt_ddi_phy_init(dev);
>  	} else {
>  		/*
>  		 * The LCPLL register should be turned on by the BIOS. For now
-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 30/49] drm/i915/bxt: add display initialize/uninitialize sequence

[Imre Deak]

On to, 2015-04-02 at 19:32 +0300, Ville Syrjälä wrote:
> On Tue, Mar 17, 2015 at 11:39:56AM +0200, Imre Deak wrote:
> > From: Vandana Kannan <vandana.kannan@intel.com>
> > 
> > Add display clock/PHY initialization sequence as per BSpec.
> > 
> > Until GOP/VBIOS provides an upper limit value for CDCLK, comparing clock
> > value with 624 MHz and returning 0 in case it exceeds.
> > 
> > Note that the CD clock and PHY initialization/uninitialization are done
> > at their current place only for simplicity, in a future patch - when more
> > of the runtime PM features will be enabled - these will be moved to
> > power well#1 and modeset encoder enabling/disabling hooks respectively.
> > This also means that atm dynamic power gating power well #2 is
> > effectively disabled.
> 
> OK, I've gone through the PHY stuff a bit now, and skipped the cdclk
> stuff this time.
> 
> > 
> > v1: Added function definitions in header files
> > v2: Imre's review comments addressed
> > - Moved CDCLK related definitions to i915_reg.h
> > - Removed defintions for CDCLK frequency
> > - Split uninit_cdclk() by adding a phy_uninit function
> > - Calculate freq and decimal based on input frequency
> > - Program SSA precharge based on input frequency
> > - Use wait_for 1ms instead 200us udelay for DE PLL locking
> > - Removed initial value for divider, freq, decimal, ratio.
> > - Replaced polling loops with wait_for
> > - Parameterized latency optim setting
> > - Fix the parts where DE PLL has to be disabled.
> > - Call CDCLK selection from mode set
> > 
> > v3: (imre)
> > - add note about the plan to move the cdclk/phy init to a better place
> > - take rps.hw_lock around pcode access
> > - fix DDI PHY timeout value
> > - squash in Vandana's "PORT_CL2CM_DW6_A BUN fix",
> >   "DDI PHY programming register defn", "Do ddi_phy_init always",
> >   "Check CDCLK upper limit" patches
> > - move PHY register macros next to the corresponding CHV/VLV macros
> > - move DE PLL register macros here from another patch since they are
> >   used here first
> > - add BXT_ prefix to CDCLK flags
> > - s/COMMON_RESET/COMMON_RESET_DIS/ and clarify related code comments
> > - fix incorrect read value for the RMW of BXT_PHY_CTL_FAMILY_DDI
> > - fix using GT_DISPLAY_EDP_POWER_ON vs. GT_DISPLAY_DDI_POWER_ON
> >   when powering on DDI ports
> > - fix incorrect port when setting BXT_PORT_TX_DW14_LN for DDI ports
> > - add missing masking when programming CDCLK_FREQ_DECIMAL
> > - add missing powering on for DDI-C port, rename OCL2_LDOFUSE_PWR_EN
> >   to OCL2_LDOFUSE_PWR_DIS to reduce confusion
> > - add note about mismatch with bspec in the PORT_REF_DW6 fields
> > - factor out PHY init code to a new function, so we can call it for
> >   PHY_A and PHY_BC, instead of open-coding the same
> > 
> > Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> (v2)
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h      | 126 +++++++++++++++
> >  drivers/gpu/drm/i915/intel_ddi.c     | 291 +++++++++++++++++++++++++++++++++++
> >  drivers/gpu/drm/i915/intel_display.c |  75 +++++++++
> >  drivers/gpu/drm/i915/intel_drv.h     |   4 +
> >  4 files changed, 496 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index b4474d3..a3579c0 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -1120,6 +1120,110 @@ enum skl_disp_power_wells {
> >  #define   DPIO_FRC_LATENCY_SHFIT	8
> >  #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
> >  #define   DPIO_UPAR_SHIFT		30
> > +
> > +/* BXT PHY registers */
> > +enum bxt_phy {
> > +	BXT_PHY_A,
> > +	BXT_PHY_BC
> > +};
> 
> We have enum dpio_phy already. Although here we have defined 0 to be the
> single channel PHY and 1 is the two channel PHY,  whereas on CHV it's
> the other way around. I'm going to suggest we flip BXT over to use the
> CHV scheme to avoid any surpises later if we actualy try to unify the
> code.

Yea, I haven't noticed it, will use that instead.

> > +
> > +#define BXT_PHY(phy, a, b)		((a) + (phy) * ((b) - (a)))
> 
> This seems to be just another _PIPE(), should at least have an
> underscore so that people don't confuse it with something they are
> supposed to use.

Ok, I can rewrite this to
#define _BXT_PHY(phy, a, b)	_PIPE(phy, a, b)

> 
> > +
> > +#define BXT_P_CR_GT_DISP_PWRON_0_2_0_GTTMMADR	0x138090
> 
> We can drop the _0_2_0_GTTMMADR suffix, we've never included it for any
> other platforms either.

Ok.

> > +#define   _EDP_POWER_ON				(1 << 1)
> > +#define   _DDI_POWER_ON				(1 << 0)
> > +#define   GT_DISPLAY_POWER_ON(phy)		BXT_PHY(phy, _EDP_POWER_ON, \
> > +							_DDI_POWER_ON)
> 
> Using a _PIPE() type of macro for register bits seems a bit unusual.
> I'd just open code it as (1 << (phy)) or something. That also work
> better if we the PHYs around so that PHY0 is the dual channel PHY.

Ok, will rewrite it.

> > +
> > +#define _PHY_CTL_FAMILY_EDP		0x64C80
> > +#define _PHY_CTL_FAMILY_DDI		0x64C90
> > +#define   COMMON_RESET_DIS		(1 << 31)
> > +#define BXT_PHY_CTL_FAMILY(phy)		BXT_PHY(phy, _PHY_CTL_FAMILY_EDP, \
> > +						     _PHY_CTL_FAMILY_DDI)
> > +
> > +/* BXT PHY common lane registers */
> > +#define _PORT_CL1CM_DW0_A		0x162000
> > +#define _PORT_CL1CM_DW0_BC		0x6C000
> > +#define   PHY_POWER_GOOD		(1 << 16)
> > +#define BXT_PORT_CL1CM_DW0(phy)		BXT_PHY(phy, _PORT_CL1CM_DW0_A,	\
> > +						     _PORT_CL1CM_DW0_BC)
> 
> I'm a bit sad these are not sharing the CHV reg defines, or even
> resemble them in any way.

I agree this isn't ideal. I've already refactored some parts in the
original version of this patch (see the commit version log) to bring it
closer to CHV, but there is definitely more to do. I'd say it's better
to do this after moving the cdckl/phy init code to the modeset/power
well enable time.

> > +#define _PORT_CL1CM_DW9_A		0x162024
> > +#define _PORT_CL1CM_DW9_BC		0x6C024
> > +#define   IREF0RC_OFFSET_SHIFT		8
> > +#define   IREF0RC_OFFSET_MASK		(0xFF << IREF0RC_OFFSET_SHIFT)
> > +#define BXT_PORT_CL1CM_DW9(phy)		BXT_PHY(phy, _PORT_CL1CM_DW9_A,	\
> > +						     _PORT_CL1CM_DW9_BC)
> > +
> > +#define _PORT_CL1CM_DW10_A		0x162028
> > +#define _PORT_CL1CM_DW10_BC		0x6C028
> > +#define   IREF1RC_OFFSET_SHIFT		8
> > +#define   IREF1RC_OFFSET_MASK		(0xFF << IREF1RC_OFFSET_SHIFT)
> > +#define BXT_PORT_CL1CM_DW10(phy)	BXT_PHY(phy, _PORT_CL1CM_DW10_A, \
> > +						     _PORT_CL1CM_DW10_BC)
> > +
> > +#define _PORT_CL1CM_DW28_A		0x162070
> > +#define _PORT_CL1CM_DW28_BC		0x6C070
> > +#define   OCL1_POWER_DOWN_EN		(1 << 23)
> > +#define   DW28_OLDO_DYN_PWR_DOWN_EN	(1 << 22)
> > +#define   SUS_CLK_CONFIG		0x3
> > +#define BXT_PORT_CL1CM_DW28(phy)	BXT_PHY(phy, _PORT_CL1CM_DW28_A, \
> > +						     _PORT_CL1CM_DW28_BC)
> > +
> > +#define _PORT_CL1CM_DW30_A		0x162078
> > +#define _PORT_CL1CM_DW30_BC		0x6C078
> > +#define   OCL2_LDOFUSE_PWR_DIS		(1 << 6)
> > +#define BXT_PORT_CL1CM_DW30(phy)	BXT_PHY(phy, _PORT_CL1CM_DW30_A, \
> > +						     _PORT_CL1CM_DW30_BC)
> > +
> > +/* Defined for PHY_BC only */
> > +#define BXT_PORT_CL2CM_DW6_BC		0x6C358
> > +#define   DW6_OLDO_DYN_PWR_DOWN_EN	(1 << 28)
> > +
> > +/* BXT PHY Ref registers */
> > +#define _PORT_REF_DW3_A			0x16218C
> > +#define _PORT_REF_DW3_BC		0x6C18C
> > +#define   GRC_DONE			(1 << 22)
> > +#define BXT_PORT_REF_DW3(phy)		BXT_PHY(phy, _PORT_REF_DW3_A,	\
> > +						     _PORT_REF_DW3_BC)
> > +
> > +#define _PORT_REF_DW6_A			0x162198
> > +#define _PORT_REF_DW6_BC		0x6C198
> > +/*
> > + * FIXME: BSpec disagrees on the following two fields, check them with
> > + * HW/documentation people.
> > + */
> 
> CHV configdb also disagrees.

Ok, thanks. Before fixing this, I want to wait for the HW to test
things.

> > +#define   GRC_CODE_SHIFT		23
> > +#define   GRC_CODE_MASK			(0x1FF << GRC_CODE_SHIFT)
> > +#define   GRC_CODE_FAST_SHIFT		16
> > +#define   GRC_CODE_FAST_MASK		(0x7F << GRC_CODE_FAST_SHIFT)
> > +#define   GRC_CODE_SLOW_SHIFT		8
> > +#define   GRC_CODE_SLOW_MASK		(0xFF << GRC_CODE_SLOW_SHIFT)
> > +#define   GRC_CODE_NOM_MASK		0xFF
> > +#define BXT_PORT_REF_DW6(phy)		BXT_PHY(phy, _PORT_REF_DW6_A,	\
> > +						     _PORT_REF_DW6_BC)
> > +
> > +#define _PORT_REF_DW8_A			0x1621A0
> > +#define _PORT_REF_DW8_BC		0x6C1A0
> > +#define   GRC_DIS			(1 << 15)
> > +#define   GRC_RDY_OVRD			(1 << 1)
> > +#define BXT_PORT_REF_DW8(phy)		BXT_PHY(phy, _PORT_REF_DW8_A,	\
> > +						     _PORT_REF_DW8_BC)
> > +
> > +/* BXT PHY TX registers */
> > +#define BXT_LANE_OFFSET(lane)           (((lane) >> 1) * 0x200 +	\
> > +					 ((lane) & 1) * 0x80)
> > +
> > +#define _PORT_TX_DW14_LN0_A		0x162538
> > +#define _PORT_TX_DW14_LN0_B		0x6C538
> > +#define _PORT_TX_DW14_LN0_C		0x6C938
> > +#define   LATENCY_OPTIM_SHIFT		30
> > +#define   LATENCY_OPTIM			(1 << LATENCY_OPTIM_SHIFT)
> > +#define BXT_PORT_TX_DW14_LN(port, lane)	(_PORT3(port, _PORT_TX_DW14_LN0_A,   \
> > +						      _PORT_TX_DW14_LN0_B,   \
> > +						      _PORT_TX_DW14_LN0_C) + \
> > +					 BXT_LANE_OFFSET(lane))
> > +
> >  /*
> >   * Fence registers
> >   */
> > @@ -5326,6 +5430,9 @@ enum skl_disp_power_wells {
> >  #define  DISP_FBC_WM_DIS		(1<<15)
> >  #define DISP_ARB_CTL2	0x45004
> >  #define  DISP_DATA_PARTITION_5_6	(1<<6)
> > +#define DBUF_CTL	0x45008
> > +#define  DBUF_POWER_REQUEST		(1<<31)
> > +#define  DBUF_POWER_STATE		(1<<30)
> >  #define GEN7_MSG_CTL	0x45010
> >  #define  WAIT_FOR_PCH_RESET_ACK		(1<<1)
> >  #define  WAIT_FOR_PCH_FLR_ACK		(1<<0)
> <snip>
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> > index a203d9d..789682d 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -1957,6 +1957,294 @@ static void skl_shared_dplls_init(struct drm_i915_private *dev_priv)
> >  	}
> >  }
> >  
> > +static void bxt_init_phy(struct drm_i915_private *dev_priv, enum bxt_phy phy)
> > +{
> > +	enum port port;
> > +	uint32_t val;
> > +
> > +	val = I915_READ(BXT_P_CR_GT_DISP_PWRON_0_2_0_GTTMMADR);
> > +	val |= GT_DISPLAY_POWER_ON(phy);
> > +	I915_WRITE(BXT_P_CR_GT_DISP_PWRON_0_2_0_GTTMMADR, val);
> > +
> > +	/* Considering 10ms timeout until BSpec is updated */
> > +	if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10))
> > +		DRM_ERROR("timeout during PHY#%d power on\n", phy);
> > +
> > +	/* Program latency optim setting */
> > +	for (port =  (phy == BXT_PHY_A ? PORT_A : PORT_B);
> > +	     port <= (phy == BXT_PHY_A ? PORT_A : PORT_C); port++) {
> > +		int lane;
> > +
> > +		for (lane = 0; lane < 4; lane++) {
> > +			val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
> > +			val &= ~LATENCY_OPTIM;
> > +			if (lane == 1)
> 
> Should be != 1

Thanks for catching it, this is a fall-out from my refactoring. Will fix
it.

> > +				val |= LATENCY_OPTIM;
> > +
> > +			I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val);
> > +		}
> > +	}
> > +
> > +	/* Program PLL Rcomp code offset */
> > +	val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
> > +	val &= ~IREF0RC_OFFSET_MASK;
> > +	val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
> > +	I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
> > +
> > +	val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
> > +	val &= ~IREF1RC_OFFSET_MASK;
> > +	val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
> > +	I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
> > +
> > +	/* Program power gating */
> > +	val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
> > +	val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
> > +		SUS_CLK_CONFIG;
> > +	I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
> > +
> > +	if (phy == BXT_PHY_BC) {
> > +		val = I915_READ(BXT_PORT_CL2CM_DW6_BC);
> > +		val |= DW6_OLDO_DYN_PWR_DOWN_EN;
> > +		I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val);
> > +	}
> > +
> > +	val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
> > +	val &= ~OCL2_LDOFUSE_PWR_DIS;
> > +	/*
> > +	 * On PHY_A disable power on the second channel, since no port is
> > +	 * connected there. On PHY_BC both channels have a port, so leave it
> > +	 * enabled.
> > +	 * Note that port C is only connected on BXT-P, so on BXT0/1 we should
> > +	 * power down the second channel on PHY_BC as well.
> > +	 */
> > +	if (phy == BXT_PHY_A)
> > +		val |= OCL2_LDOFUSE_PWR_DIS;
> > +	I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
> > +
> > +	if (phy == BXT_PHY_BC) {
> > +		uint32_t grc_code;
> > +		/*
> > +		 * PHY_BC isn't connected to an RCOMP resistor so copy over
> > +		 * the corresponding calibrated value from PHY_A, and disable
> > +		 * the automatic calibration on PHY_BC.
> > +		 */
> > +		if (wait_for(I915_READ(BXT_PORT_REF_DW3(BXT_PHY_A)) & GRC_DONE,
> > +			     10))
> > +			DRM_ERROR("timeout waiting for PHY#0 GRC\n");
> > +
> > +		val = I915_READ(BXT_PORT_REF_DW6(BXT_PHY_A));
> > +		val = (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
> > +		grc_code = val << GRC_CODE_FAST_SHIFT |
> > +			   val << GRC_CODE_SLOW_SHIFT |
> > +			   val;
> > +		I915_WRITE(BXT_PORT_REF_DW6(BXT_PHY_BC), grc_code);
> > +
> > +		val = I915_READ(BXT_PORT_REF_DW8(BXT_PHY_BC));
> > +		val |= GRC_DIS | GRC_RDY_OVRD;
> > +		I915_WRITE(BXT_PORT_REF_DW8(BXT_PHY_BC), val);
> > +	}
> > +
> > +	/* Release common_reset */
> > +	val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
> > +	val |= COMMON_RESET_DIS;
> > +	I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
> > +}
> 
> I suppose we'll want to model this thing as a power well like on CHV
> eventually, but I guess we can start off with initializing it once.

Yep, sounds good, but I'd also prefer to do this as a follow-up.

> > +
> > +void bxt_ddi_phy_init(struct drm_device *dev)
> > +{
> > +	/* Enable PHY_A first since it provides Rcomp for PHY_BC */
> > +	bxt_init_phy(dev->dev_private, BXT_PHY_A);
> > +	bxt_init_phy(dev->dev_private, BXT_PHY_BC);
> > +}
> > +
> > +static void bxt_ddi_phy_uninit(struct drm_device *dev)
> > +{
> > +	struct drm_i915_private *dev_priv = dev->dev_private;
> > +	uint32_t temp;
> > +
> > +	temp = I915_READ(BXT_PHY_CTL_FAMILY(BXT_PHY_A));
> > +	I915_WRITE(BXT_PHY_CTL_FAMILY(BXT_PHY_A), temp & ~COMMON_RESET_DIS);
> > +
> > +	temp = I915_READ(BXT_PHY_CTL_FAMILY(BXT_PHY_BC));
> > +	I915_WRITE(BXT_PHY_CTL_FAMILY(BXT_PHY_BC), temp & ~COMMON_RESET_DIS);
> > +
> > +	I915_WRITE(BXT_P_CR_GT_DISP_PWRON_0_2_0_GTTMMADR, 0);
> > +}
> 
> This should really be per-phy to avoid confusion when comparing with the
> init function.

Ok, will rewrite it.

> > +
> <snip>
> > +
> > +void bxt_init_cdclk(struct drm_device *dev)
> > +{
> > +	struct drm_i915_private *dev_priv = dev->dev_private;
> > +
> > +	/* NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
> > +	 * or else the reset will hang because there is no PCH to respond.
> > +	 * Move the handshake programming to initialization sequence.
> > +	 * Previously was left up to BIOS.
> > +	 */
> > +	u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
> > +
> > +	temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
> > +	I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
> > +
> > +	/* Enable PG1 for cdclk */
> > +	intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
> > +
> > +	/* check if cd clock is enabled */
> > +	if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
> > +		DRM_DEBUG_KMS("Display already initialized\n");
> > +		return;
> > +	}
> > +
> > +	/* FIXME:- The initial CDCLK needs to be read from VBT.
> > +	 * Need to make this change after VBT has changes for BXT.
> > +	 */
> > +	bxt_select_cdclk_freq(dev, 624000);
> > +
> > +	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
> > +	udelay(10);
> > +
> > +	if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
> > +		DRM_ERROR("DBuf power enable timeout!\n");
> > +}
> 
> This code seems like power well territory again. Just stuffing it into
> PG1 would seem like a good enough solution judging by the fact that we
> hold the PG1 reference as long as we have the DBUF power request enabled.
> 
> Or are there actual uses for having PG1 enabled w/o this thing?

I don't think so, bspec requires this power request line to be asserted
for all display internal functionality. So I agree moving it to the
power well code is a good plan (as a follow-up).

> > +
> > +void bxt_uninit_cdclk(struct drm_device *dev)
> > +{
> > +	struct drm_i915_private *dev_priv = dev->dev_private;
> > +
> > +	bxt_ddi_phy_uninit(dev);
> > +
> > +	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
> > +	udelay(10);
> > +
> > +	if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
> > +		DRM_ERROR("DBuf power disable timeout!\n");
> > +
> > +	bxt_select_cdclk_freq(dev, 0);
> > +
> > +	intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
> > +}
> > +
> >  void intel_ddi_pll_init(struct drm_device *dev)
> >  {
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> > @@ -1973,6 +2261,9 @@ void intel_ddi_pll_init(struct drm_device *dev)
> >  	if (IS_SKYLAKE(dev)) {
> >  		if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
> >  			DRM_ERROR("LCPLL1 is disabled\n");
> > +	} else if (IS_BROXTON(dev)) {
> > +		bxt_init_cdclk(dev);
> > +		bxt_ddi_phy_init(dev);
> >  	} else {
> >  		/*
> >  		 * The LCPLL register should be turned on by the BIOS. For now


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Re: [PATCH v2 23/49] drm/i915/bxt: Increase DDI buf idle timeout

[Jani Nikula]

On Fri, 27 Mar 2015, Imre Deak <imre.deak@intel.com> wrote:
> From: Vandana Kannan <vandana.kannan@intel.com>
>
> For BXT, DDI buf idle timeout delay needs to be increased to 16us.
>
> Since this is a timeout value and we return as soon as the condition is
> realized, no penalty incurred for other platforms.
>
> v2:
> - remove TIMEOUT macro used only at a single place (Daniel)
>
> Suggested-by: Satheeshakrishna M <satheeshakrishna.m@intel.com>
> Cc: Satheeshakrishna M <satheeshakrishna.m@intel.com>
> Cc: Damien Lespiau <damien.lespiau@intel.com>
> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> (v1)

Might have a comment about bxt vs. others in there, but either way,

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 8aee7d7..e24cd6f 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -322,7 +322,7 @@ static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
>  	uint32_t reg = DDI_BUF_CTL(port);
>  	int i;
>  
> -	for (i = 0; i < 8; i++) {
> +	for (i = 0; i < 16; i++) {
>  		udelay(1);
>  		if (I915_READ(reg) & DDI_BUF_IS_IDLE)
>  			return;
> -- 
> 2.1.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
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Re: [PATCH v2 13/49] drm/i915/bxt: add bxt_init_clock_gating

[Nick Hoath]

On 27/03/2015 12:00, Deak, Imre wrote:
> v2:
> - Make the condition to select between SKL and BXT consistent with the
>    corresponding condition in init_workarounds_ring (Nick)
>

Reviewed-by: Nick Hoath <nicholas.hoath@intel.com>

> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_pm.c | 12 +++++++++++-
>   1 file changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index c52f8b7..8a8d52a 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -94,6 +94,11 @@ static void skl_init_clock_gating(struct drm_device *dev)
>   			   GEN8_LQSC_RO_PERF_DIS);
>   }
>
> +static void bxt_init_clock_gating(struct drm_device *dev)
> +{
> +	gen9_init_clock_gating(dev);
> +}
> +
>   static void i915_pineview_get_mem_freq(struct drm_device *dev)
>   {
>   	struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -6548,7 +6553,12 @@ void intel_init_pm(struct drm_device *dev)
>   	if (INTEL_INFO(dev)->gen >= 9) {
>   		skl_setup_wm_latency(dev);
>
> -		dev_priv->display.init_clock_gating = skl_init_clock_gating;
> +		if (IS_BROXTON(dev))
> +			dev_priv->display.init_clock_gating =
> +				bxt_init_clock_gating;
> +		else if (IS_SKYLAKE(dev))
> +			dev_priv->display.init_clock_gating =
> +				skl_init_clock_gating;
>   		dev_priv->display.update_wm = skl_update_wm;
>   		dev_priv->display.update_sprite_wm = skl_update_sprite_wm;
>   	} else if (HAS_PCH_SPLIT(dev)) {
>

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Re: [PATCH v6 24/49] drm/i915/bxt: DDI Hotplug interrupt setup

[Jani Nikula]

On Fri, 27 Mar 2015, Imre Deak <imre.deak@intel.com> wrote:
> From: Shashank Sharma <shashank.sharma@intel.com>
>
> In BXT, DDI hotplug control has been moved to CPU from PCH.
> This patch adds a new IRQ setup function for BXT which:
> 1. Checks which HPD ports are requested to be enabled by encoders.
> 2. Enables those ports in the hot plug control register.
> 3. Un-masks these port interrupts in the IMR register.
> 4. Enables these port interrupts in the IER register.
>
> V3: Kept the default HPD filter count to default (500 us) as per
>     satheesh's comment
> v4: Remove unused HPD filter defines (Damien)
> v5: warn if trying to setup HPD on port A (imre)
> v6: fix order of definitions for register bitfields (Daniel)
>
> Reviewed-by: Satheeshakrishna M <satheeshakrishna.m@intel.com>
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> Signed-off-by: Shashank Sharma <shashank.sharma@intel.com> (v4)
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_irq.c | 49 ++++++++++++++++++++++++++++++++++++++++-
>  drivers/gpu/drm/i915/i915_reg.h | 25 ++++++++++++++++++++-
>  2 files changed, 72 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 14ecb4d..d09b389 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -88,6 +88,12 @@ static const u32 hpd_status_i915[HPD_NUM_PINS] = { /* i915 and valleyview are th
>  	[HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
>  };
>  
> +/* BXT hpd list */
> +static const u32 hpd_bxt[] = {

You need to specify the size hpd_bxt[HPD_NUM_PINS] here to be defensive
about not going out of bounds.

> +	[HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
> +	[HPD_PORT_C] = BXT_DE_PORT_HP_DDIC
> +};
> +
>  /* IIR can theoretically queue up two events. Be paranoid. */
>  #define GEN8_IRQ_RESET_NDX(type, which) do { \
>  	I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
> @@ -3178,6 +3184,44 @@ static void ibx_hpd_irq_setup(struct drm_device *dev)
>  	I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
>  }
>  
> +static void bxt_hpd_irq_setup(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct drm_mode_config *mode_config = &dev->mode_config;
> +	struct intel_encoder *intel_encoder;
> +	u32 hotplug_port = 0;
> +	u32 hotplug_ctrl;
> +
> +	/* Now, enable HPD */
> +	list_for_each_entry(intel_encoder, &mode_config->encoder_list,
> +		base.head) {

for_each_intel_encoder

> +		if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark
> +				== HPD_ENABLED)
> +			hotplug_port |= hpd_bxt[intel_encoder->hpd_pin];
> +	}
> +
> +	/* Mask all HPD control bits */
> +	hotplug_ctrl = I915_READ(BXT_HOTPLUG_CTL) & ~BXT_HOTPLUG_CTL_MASK;
> +
> +	/* Enable requested port in hotplug control */
> +	/* TODO: implement (short) HPD support on port A */
> +	WARN_ON_ONCE(hotplug_port & BXT_DE_PORT_HP_DDIA);
> +	if (hotplug_port & BXT_DE_PORT_HP_DDIB)
> +		hotplug_ctrl |= BXT_DDIB_HPD_ENABLE;
> +	if (hotplug_port & BXT_DE_PORT_HP_DDIC)
> +		hotplug_ctrl |= BXT_DDIC_HPD_ENABLE;
> +	I915_WRITE(BXT_HOTPLUG_CTL, hotplug_ctrl);
> +
> +	/* Unmask DDI hotplug in IMR */
> +	hotplug_ctrl = I915_READ(GEN8_DE_PORT_IMR) & ~hotplug_port;
> +	I915_WRITE(GEN8_DE_PORT_IMR, hotplug_ctrl);
> +
> +	/* Enable DDI hotplug in IER */
> +	hotplug_ctrl = I915_READ(GEN8_DE_PORT_IER) | hotplug_port;
> +	I915_WRITE(GEN8_DE_PORT_IER, hotplug_ctrl);
> +	POSTING_READ(GEN8_DE_PORT_IER);
> +}
> +
>  static void ibx_irq_postinstall(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -4298,7 +4342,10 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
>  		dev->driver->irq_uninstall = gen8_irq_uninstall;
>  		dev->driver->enable_vblank = gen8_enable_vblank;
>  		dev->driver->disable_vblank = gen8_disable_vblank;
> -		dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
> +		if (HAS_PCH_SPLIT(dev))
> +			dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
> +		else
> +			dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
>  	} else if (HAS_PCH_SPLIT(dev)) {
>  		dev->driver->irq_handler = ironlake_irq_handler;
>  		dev->driver->irq_preinstall = ironlake_irq_reset;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 6a5ade6..a082d7d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5240,10 +5240,16 @@ enum skl_disp_power_wells {
>  #define GEN8_DE_PORT_IMR 0x44444
>  #define GEN8_DE_PORT_IIR 0x44448
>  #define GEN8_DE_PORT_IER 0x4444c
> -#define  GEN8_PORT_DP_A_HOTPLUG		(1 << 3)
>  #define  GEN9_AUX_CHANNEL_D		(1 << 27)
>  #define  GEN9_AUX_CHANNEL_C		(1 << 26)
>  #define  GEN9_AUX_CHANNEL_B		(1 << 25)
> +#define  BXT_DE_PORT_HP_DDIC		(1 << 5)
> +#define  BXT_DE_PORT_HP_DDIB		(1 << 4)
> +#define  BXT_DE_PORT_HP_DDIA		(1 << 3)
> +#define  BXT_DE_PORT_HOTPLUG_MASK	(BXT_DE_PORT_HP_DDIA | \
> +					 BXT_DE_PORT_HP_DDIB | \
> +					 BXT_DE_PORT_HP_DDIC)
> +#define  GEN8_PORT_DP_A_HOTPLUG		(1 << 3)
>  #define  GEN8_AUX_CHANNEL_A		(1 << 0)
>  
>  #define GEN8_DE_MISC_ISR 0x44460
> @@ -5257,6 +5263,23 @@ enum skl_disp_power_wells {
>  #define GEN8_PCU_IIR 0x444e8
>  #define GEN8_PCU_IER 0x444ec
>  
> +/* BXT hotplug control */
> +#define BXT_HOTPLUG_CTL			0xC4030
> +#define BXT_DDIA_HPD_ENABLE		(1 << 28)
> +#define BXT_DDIC_HPD_ENABLE		(1 << 12)
> +#define BXT_DDIB_HPD_ENABLE		(1 << 4)
> +#define BXT_HOTPLUG_CTL_MASK		(BXT_DDIA_HPD_ENABLE | \
> +					 BXT_DDIB_HPD_ENABLE | \
> +					 BXT_DDIC_HPD_ENABLE)
> +
> +/* Hot plug status */
> +#define BXT_DDIA_HPD_STATUS		(3 << 24)
> +#define BXT_DDIC_HPD_STATUS		(3 << 8)
> +#define BXT_DDIB_HPD_STATUS		(3 << 0)
> +#define BXT_HPD_STATUS_MASK		(BXT_DDIA_HPD_STATUS | \
> +					 BXT_DDIB_HPD_STATUS | \
> +					 BXT_DDIC_HPD_STATUS)

I'd appreciate keeping the convention of having two spaces between
#define and the name for register contents (bits, masks, etc.).

> +
>  #define ILK_DISPLAY_CHICKEN2	0x42004
>  /* Required on all Ironlake and Sandybridge according to the B-Spec. */
>  #define  ILK_ELPIN_409_SELECT	(1 << 25)
> -- 
> 2.1.0
>
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

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Re: [PATCH 25/49] drm/i915/bxt: Add DDI hpd handler

[Jani Nikula]

On Tue, 17 Mar 2015, Imre Deak <imre.deak@intel.com> wrote:
> From: Shashank Sharma <shashank.sharma@intel.com>
>
> This patch adds a hot plug interrupt handler function for BXT.
> What this function typically does is:
> 1. Check if hot plug is enabled from hot plug control register.
> 2. Call hpd_irq_handler with appropriate trigger to detect a
>    plug storm and schedule a bottom half.
> 3. Clear sticky status bits in hot plug control register..
>
> Reviewed-by: Satheeshakrishna M <satheeshakrishna.m@intel.com>
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_irq.c | 45 +++++++++++++++++++++++++++++++++++++++--
>  1 file changed, 43 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index a51c00e..4a2f85b 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2227,6 +2227,38 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg)
>  	return ret;
>  }
>  
> +static void bxt_hpd_handler(struct drm_device *dev, uint32_t iir_status)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	uint32_t hp_control;
> +	uint32_t hp_trigger;
> +
> +	/* Get the status */
> +	hp_trigger = iir_status & BXT_DE_PORT_HOTPLUG_MASK;
> +	hp_control = I915_READ(BXT_HOTPLUG_CTL);
> +
> +	/* Hotplug not enabled ? */
> +	if (unlikely(!(hp_control & BXT_HOTPLUG_CTL_MASK))) {

Drop the unlikely. Or turn this into WARN_ON_ONCE, or something.

> +		DRM_ERROR("Interrupt when HPD disabled\n");
> +		return;
> +	}
> +
> +	DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
> +		hp_control & BXT_HOTPLUG_CTL_MASK);
> +
> +	/* Check for HPD storm and schedule bottom half */
> +	intel_hpd_irq_handler(dev, hp_trigger, hp_control, hpd_bxt);

That one needs to be updated for bxt hp_control.

> +
> +	/*
> +	 * Todo: Save the hot plug status for bottom half before

Make it TODO, XXX, or FIXME, but not Todo.

> +	 * clearing the sticky status bits, else the status will be
> +	 * lost.
> +	 */
> +
> +	/* Clear sticky bits in hpd status */
> +	I915_WRITE(BXT_HOTPLUG_CTL, hp_control);
> +}
> +
>  static irqreturn_t gen8_irq_handler(int irq, void *arg)
>  {
>  	struct drm_device *dev = arg;
> @@ -2236,6 +2268,7 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
>  	uint32_t tmp = 0;
>  	enum pipe pipe;
>  	u32 aux_mask = GEN8_AUX_CHANNEL_A;
> +	bool found = false;

Move this down within the block where it's needed.

>  
>  	if (!intel_irqs_enabled(dev_priv))
>  		return IRQ_NONE;
> @@ -2276,9 +2309,17 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
>  			I915_WRITE(GEN8_DE_PORT_IIR, tmp);
>  			ret = IRQ_HANDLED;
>  
> -			if (tmp & aux_mask)
> +			if (tmp & aux_mask) {
>  				dp_aux_irq_handler(dev);
> -			else
> +				found = true;
> +			}
> +
> +			if (tmp & BXT_DE_PORT_HOTPLUG_MASK) {

This needs IS_BROXTON check.

> +				bxt_hpd_handler(dev, tmp);
> +				found = true;
> +			}
> +
> +			if (!found)
>  				DRM_ERROR("Unexpected DE Port interrupt\n");
>  		}
>  		else
> -- 
> 2.1.0
>
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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Re: [PATCH 25.1/49] drm/i915/bxt: support for HPD long/short status decoding

[Jani Nikula]

On Fri, 27 Mar 2015, Imre Deak <imre.deak@intel.com> wrote:
> All non-GMCH platforms have the same register layout for HPD long/short
> status, so let's use this condition instead of HAS_PCH_SPLIT, as the
> latter doesn't apply for BXT.
>
> Noticed by Daniel.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_irq.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 4833e2b..17eed72 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -1446,7 +1446,7 @@ static inline void intel_hpd_irq_handler(struct drm_device *dev,
>  		if (port && dev_priv->hpd_irq_port[port]) {
>  			bool long_hpd;
>  
> -			if (HAS_PCH_SPLIT(dev)) {
> +			if (!HAS_GMCH_DISPLAY(dev_priv)) {
>  				dig_shift = pch_port_to_hotplug_shift(port);

This is (will be) broken for port A.

>  				long_hpd = (dig_hotplug_reg >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT;
>  			} else {
> -- 
> 2.1.0
>

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Re: [PATCH 26/49] drm/i915/bxt: Add BXT support in gen8_irq functions

[Jani Nikula]

On Tue, 17 Mar 2015, Imre Deak <imre.deak@intel.com> wrote:
> From: Shashank Sharma <shashank.sharma@intel.com>
>
> This patch adds conditional checks in gen8_irq functions
> to support BXT. Most of the checks just look for PCH split
> availability, and block the call to PCH interrupt functions if
> not available.
>
> Reviewed-by: Satheeshakrishna M <satheeshakrishna.m@intel.com>
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> Signed-off-by: Shashank Sharma <ppashank.sharma@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_irq.c | 14 ++++++++++----
>  1 file changed, 10 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 4a2f85b..3b82eb2 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2372,7 +2372,13 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
>  			DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
>  	}
>  
> -	if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) {
> +	/*
> +	 * Todo: BXT doesnt have a PCH, so GEN8_DE_PCH_IRQ shouldn't
> +	 * be set. But until this part is confirmed, going paranoid, and adding
> +	 * a IS_BROXTON check here.
> +	 */
> +	if (!IS_BROXTON(dev) && !HAS_PCH_NOP(dev) &&
> +			master_ctl & GEN8_DE_PCH_IRQ) {

Drop the todo comment, and add HAS_PCH_SPLIT() instead of !IS_BROXTON()
here, and it's fine. We never want to call pch functions on non-pch
platforms, so this is IMO the obvious thing to do.

>  		/*
>  		 * FIXME(BDW): Assume for now that the new interrupt handling
>  		 * scheme also closed the SDE interrupt handling race we've seen
> @@ -3096,7 +3102,7 @@ static void ibx_irq_reset(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  
> -	if (HAS_PCH_NOP(dev))
> +	if (HAS_PCH_NOP(dev) || !HAS_PCH_SPLIT(dev))
>  		return;

No, I think it's much better to simply not call pch functions on non-pch
platforms. Instead, please add

	if (HAS_PCH_SPLIT(dev))
        	ibx_irq_reset(dev);

in gen8_irq_reset().

>  
>  	GEN5_IRQ_RESET(SDE);
> @@ -3117,7 +3123,7 @@ static void ibx_irq_pre_postinstall(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  
> -	if (HAS_PCH_NOP(dev))
> +	if (HAS_PCH_NOP(dev) || !HAS_PCH_SPLIT(dev))
>  		return;

Same here, but for gen8_irq_postinstall().

>  
>  	WARN_ON(I915_READ(SDEIER) != 0);
> @@ -3325,7 +3331,7 @@ static void ibx_irq_postinstall(struct drm_device *dev)
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	u32 mask;
>  
> -	if (HAS_PCH_NOP(dev))
> +	if (HAS_PCH_NOP(dev) || !HAS_PCH_SPLIT(dev))
>  		return;

Ditto.

>  
>  	if (HAS_PCH_IBX(dev))
> -- 
> 2.1.0
>
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
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Re: [PATCH 27/49] drm/i915/bxt: Enable GMBUS IRQ

[Jani Nikula]

On Tue, 17 Mar 2015, Imre Deak <imre.deak@intel.com> wrote:
> From: Shashank Sharma <shashank.sharma@intel.com>
>
> GMBUS interrupt has been moved to CPU side in BXT.
> What this patch does is:
> 1. Enable GMBUS IRQ in de_post_install function
> 2. Handle this interrupt as a port interrupt in display irq
>    handler
>
> v2: Rebase on top of the for_each_pipe() change adding dev_priv as
>     first argument (Damien).
> v3: read BXT_DE_PORT_GMBUS IIR flag only on BXT on other platforms
>     it's reserved (imre)
>
> Reviewed-by: Satheeshakrishna M <satheeshakrishna.m@intel.com>
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> Signed-off-by: Shashank Sharma <shashank.sharma@intel.com> (v1)
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_irq.c | 14 +++++++++++---
>  drivers/gpu/drm/i915/i915_reg.h |  3 +++
>  2 files changed, 14 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 3b82eb2..2be167c 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2319,6 +2319,11 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
>  				found = true;
>  			}
>  
> +			if (IS_BROXTON(dev) && (tmp & BXT_DE_PORT_GMBUS)) {
> +				gmbus_irq_handler(dev);
> +				found = true;
> +			}
> +
>  			if (!found)
>  				DRM_ERROR("Unexpected DE Port interrupt\n");
>  		}
> @@ -3596,13 +3601,16 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
>  	uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
>  	uint32_t de_pipe_enables;
>  	int pipe;
> -	u32 aux_en = GEN8_AUX_CHANNEL_A;
> +	u32 de_port_en = GEN8_AUX_CHANNEL_A;
>  
>  	if (IS_GEN9(dev_priv)) {
>  		de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
>  				  GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
> -		aux_en |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
> +		de_port_en |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
>  			GEN9_AUX_CHANNEL_D;
> +
> +		if (IS_BROXTON(dev_priv))
> +			de_port_en |= BXT_DE_PORT_GMBUS;
>  	} else
>  		de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
>  				  GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
> @@ -3621,7 +3629,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
>  					  dev_priv->de_irq_mask[pipe],
>  					  de_pipe_enables);
>  
> -	GEN5_IRQ_INIT(GEN8_DE_PORT_, ~aux_en, aux_en);
> +	GEN5_IRQ_INIT(GEN8_DE_PORT_, ~de_port_en, de_port_en);
>  }
>  
>  static int gen8_irq_postinstall(struct drm_device *dev)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 1efee7d..b4474d3 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5255,6 +5255,9 @@ enum skl_disp_power_wells {
>  					BXT_DE_PORT_HP_DDIB | \
>  					BXT_DE_PORT_HP_DDIC)
>  
> +/* BXT GMBUS */

That's obvious from the define, no need for the comment, just move this
right next to the other bit definitions above and put two spaces after
#define.

With that done,

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> +#define BXT_DE_PORT_GMBUS	(1 << 1)
> +
>  #define GEN8_DE_MISC_ISR 0x44460
>  #define GEN8_DE_MISC_IMR 0x44464
>  #define GEN8_DE_MISC_IIR 0x44468
> -- 
> 2.1.0
>
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Re: [PATCH 25.1/49] drm/i915/bxt: support for HPD long/short status decoding

[Imre Deak]

On ke, 2015-04-08 at 13:58 +0300, Jani Nikula wrote:
> On Fri, 27 Mar 2015, Imre Deak <imre.deak@intel.com> wrote:
> > All non-GMCH platforms have the same register layout for HPD long/short
> > status, so let's use this condition instead of HAS_PCH_SPLIT, as the
> > latter doesn't apply for BXT.
> >
> > Noticed by Daniel.
> >
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_irq.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> > index 4833e2b..17eed72 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -1446,7 +1446,7 @@ static inline void intel_hpd_irq_handler(struct drm_device *dev,
> >  		if (port && dev_priv->hpd_irq_port[port]) {
> >  			bool long_hpd;
> >  
> > -			if (HAS_PCH_SPLIT(dev)) {
> > +			if (!HAS_GMCH_DISPLAY(dev_priv)) {
> >  				dig_shift = pch_port_to_hotplug_shift(port);
> 
> This is (will be) broken for port A.

HPD on port A is not supported atm on any platforms. On BXT we also WARN
if someone tried to enable it in bxt_hpd_irq_setup(). I think adding
support for this is a separate (follow-up) issue.

> 
> >  				long_hpd = (dig_hotplug_reg >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT;
> >  			} else {
> > -- 
> > 2.1.0
> >
> 


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Re: [PATCH 25.1/49] drm/i915/bxt: support for HPD long/short status decoding

[Jani Nikula]

On Wed, 08 Apr 2015, Imre Deak <imre.deak@intel.com> wrote:
> On ke, 2015-04-08 at 13:58 +0300, Jani Nikula wrote:
>> On Fri, 27 Mar 2015, Imre Deak <imre.deak@intel.com> wrote:
>> > All non-GMCH platforms have the same register layout for HPD long/short
>> > status, so let's use this condition instead of HAS_PCH_SPLIT, as the
>> > latter doesn't apply for BXT.
>> >
>> > Noticed by Daniel.
>> >
>> > Signed-off-by: Imre Deak <imre.deak@intel.com>
>> > ---
>> >  drivers/gpu/drm/i915/i915_irq.c | 2 +-
>> >  1 file changed, 1 insertion(+), 1 deletion(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>> > index 4833e2b..17eed72 100644
>> > --- a/drivers/gpu/drm/i915/i915_irq.c
>> > +++ b/drivers/gpu/drm/i915/i915_irq.c
>> > @@ -1446,7 +1446,7 @@ static inline void intel_hpd_irq_handler(struct drm_device *dev,
>> >  		if (port && dev_priv->hpd_irq_port[port]) {
>> >  			bool long_hpd;
>> >  
>> > -			if (HAS_PCH_SPLIT(dev)) {
>> > +			if (!HAS_GMCH_DISPLAY(dev_priv)) {
>> >  				dig_shift = pch_port_to_hotplug_shift(port);
>> 
>> This is (will be) broken for port A.
>
> HPD on port A is not supported atm on any platforms. On BXT we also WARN
> if someone tried to enable it in bxt_hpd_irq_setup(). I think adding
> support for this is a separate (follow-up) issue.

Fair enough.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


>
>> 
>> >  				long_hpd = (dig_hotplug_reg >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT;
>> >  			} else {
>> > -- 
>> > 2.1.0
>> >
>> 
>
>

-- 
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Re: [PATCH v2 23/49] drm/i915/bxt: Increase DDI buf idle timeout

[Daniel Vetter]

On Wed, Apr 08, 2015 at 12:20:12PM +0300, Jani Nikula wrote:
> On Fri, 27 Mar 2015, Imre Deak <imre.deak@intel.com> wrote:
> > From: Vandana Kannan <vandana.kannan@intel.com>
> >
> > For BXT, DDI buf idle timeout delay needs to be increased to 16us.
> >
> > Since this is a timeout value and we return as soon as the condition is
> > realized, no penalty incurred for other platforms.
> >
> > v2:
> > - remove TIMEOUT macro used only at a single place (Daniel)
> >
> > Suggested-by: Satheeshakrishna M <satheeshakrishna.m@intel.com>
> > Cc: Satheeshakrishna M <satheeshakrishna.m@intel.com>
> > Cc: Damien Lespiau <damien.lespiau@intel.com>
> > Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
> > Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> (v1)

Just because this one is lacking sobe lines ... when you send out patches,
you should add your own sob. Anyway, applied without that.
-Daniel

> 
> Might have a comment about bxt vs. others in there, but either way,
> 
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> 
> 
> > ---
> >  drivers/gpu/drm/i915/intel_ddi.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> > index 8aee7d7..e24cd6f 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -322,7 +322,7 @@ static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
> >  	uint32_t reg = DDI_BUF_CTL(port);
> >  	int i;
> >  
> > -	for (i = 0; i < 8; i++) {
> > +	for (i = 0; i < 16; i++) {
> >  		udelay(1);
> >  		if (I915_READ(reg) & DDI_BUF_IS_IDLE)
> >  			return;
> > -- 
> > 2.1.0
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Jani Nikula, Intel Open Source Technology Center

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [PATCH 11/49] drm/i915/gen9: fix PIPE_CONTROL flush for VS_INVALIDATE

[Nick Hoath]

On 17/03/2015 09:39, Imre Deak wrote:
> On GEN9+ per specification a NULL PIPE_CONTROL needs to be emitted
> before any PIPE_CONTROL command with the VS_INVALIDATE flag set.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Reviewed-by: Nick Hoath <nicholas.hoath@intel.com>

> ---
>   drivers/gpu/drm/i915/intel_lrc.c | 19 ++++++++++++++++++-
>   1 file changed, 18 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index fcb074b..71aeeb3 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1262,6 +1262,7 @@ static int gen8_emit_flush_render(struct intel_ringbuffer *ringbuf,
>   {
>   	struct intel_engine_cs *ring = ringbuf->ring;
>   	u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
> +	bool vf_flush_wa;
>   	u32 flags = 0;
>   	int ret;
>
> @@ -1283,10 +1284,26 @@ static int gen8_emit_flush_render(struct intel_ringbuffer *ringbuf,
>   		flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
>   	}
>
> -	ret = intel_logical_ring_begin(ringbuf, ctx, 6);
> +	/*
> +	 * On GEN9+ Before VF_CACHE_INVALIDATE we need to emit a NULL pipe
> +	 * control.
> +	 */
> +	vf_flush_wa = INTEL_INFO(ring->dev)->gen >= 9 &&
> +		      flags & PIPE_CONTROL_VF_CACHE_INVALIDATE;
> +
> +	ret = intel_logical_ring_begin(ringbuf, ctx, vf_flush_wa ? 12 : 6);
>   	if (ret)
>   		return ret;
>
> +	if (vf_flush_wa) {
> +		intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
> +		intel_logical_ring_emit(ringbuf, 0);
> +		intel_logical_ring_emit(ringbuf, 0);
> +		intel_logical_ring_emit(ringbuf, 0);
> +		intel_logical_ring_emit(ringbuf, 0);
> +		intel_logical_ring_emit(ringbuf, 0);
> +	}
> +
>   	intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
>   	intel_logical_ring_emit(ringbuf, flags);
>   	intel_logical_ring_emit(ringbuf, scratch_addr);
>

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Re: [PATCH 15/49] drm/i915/bxt: add GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ workaround

[Nick Hoath]

On 17/03/2015 09:39, Imre Deak wrote:
> From: Ben Widawsky <benjamin.widawsky@intel.com>
>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_reg.h | 1 +
>   drivers/gpu/drm/i915/intel_pm.c | 4 +++-
>   2 files changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 3369a11..b7ba061 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6104,6 +6104,7 @@ enum skl_disp_power_wells {
>   #define GEN8_UCGCTL6				0x9430
>   #define   GEN8_GAPSUNIT_CLOCK_GATE_DISABLE	(1<<24)
>   #define   GEN8_SDEUNIT_CLOCK_GATE_DISABLE	(1<<14)
> +#define   GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ (1<<28)
>
>   #define GEN6_GFXPAUSE				0xA000
>   #define GEN6_RPNSWREQ				0xA008
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index d5dd0b3..52d3c02 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -103,10 +103,12 @@ static void bxt_init_clock_gating(struct drm_device *dev)
>   	/*
>   	 * FIXME:
>   	 * GEN8_SDEUNIT_CLOCK_GATE_DISABLE applies on A0 only.
> +	 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
>   	 */
>   	 /* WaDisableSDEUnitClockGating:bxt */

I can't find where WaDisableSDEUnitClockGating is listed as required for 
BXT?

>   	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
> -		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
> +		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE |
> +		   GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
>
>   }
>
>

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Re: [PATCH 15/49] drm/i915/bxt: add GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ workaround

[Imre Deak]

On ke, 2015-04-08 at 14:04 +0100, Nick Hoath wrote:
> On 17/03/2015 09:39, Imre Deak wrote:
> > From: Ben Widawsky <benjamin.widawsky@intel.com>
> >
> > Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> >   drivers/gpu/drm/i915/i915_reg.h | 1 +
> >   drivers/gpu/drm/i915/intel_pm.c | 4 +++-
> >   2 files changed, 4 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 3369a11..b7ba061 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -6104,6 +6104,7 @@ enum skl_disp_power_wells {
> >   #define GEN8_UCGCTL6				0x9430
> >   #define   GEN8_GAPSUNIT_CLOCK_GATE_DISABLE	(1<<24)
> >   #define   GEN8_SDEUNIT_CLOCK_GATE_DISABLE	(1<<14)
> > +#define   GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ (1<<28)
> >
> >   #define GEN6_GFXPAUSE				0xA000
> >   #define GEN6_RPNSWREQ				0xA008
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index d5dd0b3..52d3c02 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -103,10 +103,12 @@ static void bxt_init_clock_gating(struct drm_device *dev)
> >   	/*
> >   	 * FIXME:
> >   	 * GEN8_SDEUNIT_CLOCK_GATE_DISABLE applies on A0 only.
> > +	 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
> >   	 */
> >   	 /* WaDisableSDEUnitClockGating:bxt */
> 
> I can't find where WaDisableSDEUnitClockGating is listed as required for 
> BXT?

It's specified in BSpec GEN8_UCGCTL6 (0x9430) as required for BXT A0.

--Imre

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Re: [PATCH 18/49] drm/i915/bxt: add workaround to avoid PTE corruption

[Nick Hoath]

On 17/03/2015 09:39, Imre Deak wrote:
> From: Robert Beckett <robert.beckett@intel.com>
>
> Set TLBPF in TILECTL. This fixes an issue with BXT HW seeing
> corrupted pte entries.
>
> v2:
> - move the workaround to bxt_init_clock_gating (imre)
>
> Signed-off-by: Robert Beckett <robert.beckett@intel.com> (v1)
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Reviewed-by: Nick Hoath <nicholas.hoath@intel.com>

> ---
>   drivers/gpu/drm/i915/i915_reg.h | 1 +
>   drivers/gpu/drm/i915/intel_pm.c | 2 ++
>   2 files changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 1d074e8..d69d7b9 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1151,6 +1151,7 @@ enum skl_disp_power_wells {
>   /* control register for cpu gtt access */
>   #define TILECTL				0x101000
>   #define   TILECTL_SWZCTL			(1 << 0)
> +#define   TILECTL_TLBPF			(1 << 1)
>   #define   TILECTL_TLB_PREFETCH_DIS	(1 << 2)
>   #define   TILECTL_BACKSNOOP_DIS		(1 << 3)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 52d3c02..d3f2557 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -110,6 +110,8 @@ static void bxt_init_clock_gating(struct drm_device *dev)
>   		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE |
>   		   GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
>
> +	/* FIXME: apply on A0 only */
> +	I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
>   }
>
>   static void i915_pineview_get_mem_freq(struct drm_device *dev)
>

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Re: [PATCH 15/49] drm/i915/bxt: add GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ workaround

[Nick Hoath]

On 08/04/2015 14:10, Deak, Imre wrote:
> On ke, 2015-04-08 at 14:04 +0100, Nick Hoath wrote:
>> On 17/03/2015 09:39, Imre Deak wrote:
>>> From: Ben Widawsky <benjamin.widawsky@intel.com>
>>>
>>> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
>>> Signed-off-by: Imre Deak <imre.deak@intel.com>
>>> ---
>>>    drivers/gpu/drm/i915/i915_reg.h | 1 +
>>>    drivers/gpu/drm/i915/intel_pm.c | 4 +++-
>>>    2 files changed, 4 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>>> index 3369a11..b7ba061 100644
>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>> @@ -6104,6 +6104,7 @@ enum skl_disp_power_wells {
>>>    #define GEN8_UCGCTL6				0x9430
>>>    #define   GEN8_GAPSUNIT_CLOCK_GATE_DISABLE	(1<<24)
>>>    #define   GEN8_SDEUNIT_CLOCK_GATE_DISABLE	(1<<14)
>>> +#define   GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ (1<<28)
>>>
>>>    #define GEN6_GFXPAUSE				0xA000
>>>    #define GEN6_RPNSWREQ				0xA008
>>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>>> index d5dd0b3..52d3c02 100644
>>> --- a/drivers/gpu/drm/i915/intel_pm.c
>>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>>> @@ -103,10 +103,12 @@ static void bxt_init_clock_gating(struct drm_device *dev)
>>>    	/*
>>>    	 * FIXME:
>>>    	 * GEN8_SDEUNIT_CLOCK_GATE_DISABLE applies on A0 only.
>>> +	 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.

Shouldn't this WA therefore have a check for 3x6 around it?

>>>    	 */
>>>    	 /* WaDisableSDEUnitClockGating:bxt */
>>
>> I can't find where WaDisableSDEUnitClockGating is listed as required for
>> BXT?
>
> It's specified in BSpec GEN8_UCGCTL6 (0x9430) as required for BXT A0.
>
> --Imre
>

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Re: [PATCH 17/49] drm/i915/skl: add WaDisableMaskBasedCammingInRCC workaround

[Nick Hoath]

On 20/03/2015 10:33, Deak, Imre wrote:
> On Fri, 2015-03-20 at 09:07 +0000, Nick Hoath wrote:
>> On 17/03/2015 09:39, Imre Deak wrote:
>>> From: Ben Widawsky <benjamin.widawsky@intel.com>
>>>
>>> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
>>> Signed-off-by: Imre Deak <imre.deak@intel.com>

Bearing in mind having to revisit all these with the stepping checks:
Reviewed-by: Nick Hoath <nicholas.hoath@intel.com>

>>> ---
>>>    drivers/gpu/drm/i915/intel_ringbuffer.c | 4 ++--
>>>    1 file changed, 2 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
>>> index e23cbdc..000f608 100644
>>> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
>>> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
>>> @@ -970,8 +970,8 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
>>>    	 * FIXME: don't apply the following on BXT for stepping C. On BXT A0
>>>    	 * the flag reads back as 0.
>>>    	 */
>>> -	/* WaDisableMaskBasedCammingInRCC:bxtA */
>>> -	if (IS_BROXTON(dev))
>>> +	/* WaDisableMaskBasedCammingInRCC:sklC,bxtA */
>>> +	if (INTEL_REVID(dev) == SKL_REVID_C0 || IS_BROXTON(dev))
>> This looks wrong. (IS_BROXTON && BXT_REVID_C0) || (IS_SKYLAKE &&
>> SKL_REVID_C0) please.
>
> It's correct though. gen9_init_workarounds() is called for Skylake or
> Broxton, so the condition is true either on Broxton regardless of the
> stepping, or on Skylake if the revid matches.
>
> Also on Broxton we have to _exclude_ the workaround on C0, so if we add
> the revid check for Broxton too, then we have to rewrite the condition
> to:
>
> (IS_BROXTON && INTEL_REVID != BXT_REVID_C0) || (IS_SKYLAKE &&
> INTEL_REVID == SKL_REVID_C0)
>
>>>    		WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
>>>    				  PIXEL_MASK_CAMMING_DISABLE);
>>>
>>>
>>
>
>

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Re: [PATCH 15/49] drm/i915/bxt: add GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ workaround

[Imre Deak]

On ke, 2015-04-08 at 14:38 +0100, Nick Hoath wrote:
> On 08/04/2015 14:10, Deak, Imre wrote:
> > On ke, 2015-04-08 at 14:04 +0100, Nick Hoath wrote:
> >> On 17/03/2015 09:39, Imre Deak wrote:
> >>> From: Ben Widawsky <benjamin.widawsky@intel.com>
> >>>
> >>> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> >>> Signed-off-by: Imre Deak <imre.deak@intel.com>
> >>> ---
> >>>    drivers/gpu/drm/i915/i915_reg.h | 1 +
> >>>    drivers/gpu/drm/i915/intel_pm.c | 4 +++-
> >>>    2 files changed, 4 insertions(+), 1 deletion(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> >>> index 3369a11..b7ba061 100644
> >>> --- a/drivers/gpu/drm/i915/i915_reg.h
> >>> +++ b/drivers/gpu/drm/i915/i915_reg.h
> >>> @@ -6104,6 +6104,7 @@ enum skl_disp_power_wells {
> >>>    #define GEN8_UCGCTL6				0x9430
> >>>    #define   GEN8_GAPSUNIT_CLOCK_GATE_DISABLE	(1<<24)
> >>>    #define   GEN8_SDEUNIT_CLOCK_GATE_DISABLE	(1<<14)
> >>> +#define   GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ (1<<28)
> >>>
> >>>    #define GEN6_GFXPAUSE				0xA000
> >>>    #define GEN6_RPNSWREQ				0xA008
> >>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> >>> index d5dd0b3..52d3c02 100644
> >>> --- a/drivers/gpu/drm/i915/intel_pm.c
> >>> +++ b/drivers/gpu/drm/i915/intel_pm.c
> >>> @@ -103,10 +103,12 @@ static void bxt_init_clock_gating(struct drm_device *dev)
> >>>    	/*
> >>>    	 * FIXME:
> >>>    	 * GEN8_SDEUNIT_CLOCK_GATE_DISABLE applies on A0 only.
> >>> +	 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
> 
> Shouldn't this WA therefore have a check for 3x6 around it?

Yes, and that's the reason for the above FIXME:. Once we know which
steppings are not-3x6, or have a way to retrieve this information we can
revisit this (see Jeff's EU slice info patchset). Atm Bspec lists all
BXT devices having a 3x6 config.

--Imre

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Re: [PATCH 15/49] drm/i915/bxt: add GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ workaround

[Nick Hoath]

On 08/04/2015 14:38, Nick Hoath wrote:
> On 08/04/2015 14:10, Deak, Imre wrote:
>> On ke, 2015-04-08 at 14:04 +0100, Nick Hoath wrote:
>>> On 17/03/2015 09:39, Imre Deak wrote:
>>>> From: Ben Widawsky <benjamin.widawsky@intel.com>
>>>>
>>>> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
>>>> Signed-off-by: Imre Deak <imre.deak@intel.com>

Reviewed-by: Nick Hoath <nicholas.hoath@intel.com>

>>>> ---
>>>>    drivers/gpu/drm/i915/i915_reg.h | 1 +
>>>>    drivers/gpu/drm/i915/intel_pm.c | 4 +++-
>>>>    2 files changed, 4 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>>>> b/drivers/gpu/drm/i915/i915_reg.h
>>>> index 3369a11..b7ba061 100644
>>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>>> @@ -6104,6 +6104,7 @@ enum skl_disp_power_wells {
>>>>    #define GEN8_UCGCTL6                0x9430
>>>>    #define   GEN8_GAPSUNIT_CLOCK_GATE_DISABLE    (1<<24)
>>>>    #define   GEN8_SDEUNIT_CLOCK_GATE_DISABLE    (1<<14)
>>>> +#define   GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ (1<<28)
>>>>
>>>>    #define GEN6_GFXPAUSE                0xA000
>>>>    #define GEN6_RPNSWREQ                0xA008
>>>> diff --git a/drivers/gpu/drm/i915/intel_pm.c
>>>> b/drivers/gpu/drm/i915/intel_pm.c
>>>> index d5dd0b3..52d3c02 100644
>>>> --- a/drivers/gpu/drm/i915/intel_pm.c
>>>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>>>> @@ -103,10 +103,12 @@ static void bxt_init_clock_gating(struct
>>>> drm_device *dev)
>>>>        /*
>>>>         * FIXME:
>>>>         * GEN8_SDEUNIT_CLOCK_GATE_DISABLE applies on A0 only.
>>>> +     * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT
>>>> SKUs only.
>
> Shouldn't this WA therefore have a check for 3x6 around it?
>
>>>>         */
>>>>         /* WaDisableSDEUnitClockGating:bxt */
>>>
>>> I can't find where WaDisableSDEUnitClockGating is listed as required for
>>> BXT?
>>
>> It's specified in BSpec GEN8_UCGCTL6 (0x9430) as required for BXT A0.
>>
>> --Imre
>>
>

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Re: [PATCH 48/49] drm/i915/bxt: VSwing programming sequence

[Imre Deak]

Hi Sivakumar,

On Tue, 2015-03-24 at 14:49 +0530, Sivakumar Thulasimani wrote:

> On 3/17/2015 3:10 PM, Imre Deak wrote:
> 
> > From: Vandana Kannan <vandana.kannan@intel.com>
> > 
> > VSwing programming sequence as specified in the updated BXT BSpec
> > ...
> > ...
> >  
> > +void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
> > +			     enum port port, int type)
> > +{
> > +	struct drm_i915_private *dev_priv = dev->dev_private;
> > +	const struct bxt_ddi_buf_trans *ddi_translations;
> > +	u32 n_entries, i;
> > +	uint32_t val;
> > +
> > +	if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
> INTEL_OUPPUT_DP_MST might be needed here, please check once. otherwise
> fine with the changes.

Tbh, I had to check this after you brought this up: we can't get here
with INTEL_OUTPUT_DP_MST. That type is only assigned to "fake" encoders,
which only handle the MST aspects of the modeset. An MST encoder like
this will have an associated "primary" encoder (available via its
"primary" digital port field) which will handle the ordinary DP aspects
of the modeset. So link training as such is handled by the primary
encoder which for DP will be always either INTEL_OUTPUT_DISPLAYPORT or
INTEL_OUTPUT_EDP.

Thanks for pointing this out,
Imre

> Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>


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[PATCH v7 24/49] drm/i915/bxt: DDI Hotplug interrupt setup

[Imre Deak]

From: Shashank Sharma <shashank.sharma@intel.com>

In BXT, DDI hotplug control has been moved to CPU from PCH.
This patch adds a new IRQ setup function for BXT which:
1. Checks which HPD ports are requested to be enabled by encoders.
2. Enables those ports in the hot plug control register.
3. Un-masks these port interrupts in the IMR register.
4. Enables these port interrupts in the IER register.

V3: Kept the default HPD filter count to default (500 us) as per
    satheesh's comment
v4: Remove unused HPD filter defines (Damien)
v5: warn if trying to setup HPD on port A (imre)
v6: fix order of definitions for register bitfields (Daniel)
v7: (jani)
- define the size of the hpd_bxt array explicitly for bound checking
- use for_each_intel_encoder instead of open coding it
- fix format/order of definitions for BXT_HOTPLUG_CTL reg bitfields

Reviewed-by: Satheeshakrishna M <satheeshakrishna.m@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com> (v4)
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 47 ++++++++++++++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/i915_reg.h | 23 +++++++++++++++++++-
 2 files changed, 68 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 46bcbff..631484d 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -88,6 +88,12 @@ static const u32 hpd_status_i915[HPD_NUM_PINS] = { /* i915 and valleyview are th
 	[HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
 };
 
+/* BXT hpd list */
+static const u32 hpd_bxt[HPD_NUM_PINS] = {
+	[HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
+	[HPD_PORT_C] = BXT_DE_PORT_HP_DDIC
+};
+
 /* IIR can theoretically queue up two events. Be paranoid. */
 #define GEN8_IRQ_RESET_NDX(type, which) do { \
 	I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
@@ -3159,6 +3165,42 @@ static void ibx_hpd_irq_setup(struct drm_device *dev)
 	I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
 }
 
+static void bxt_hpd_irq_setup(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_encoder *intel_encoder;
+	u32 hotplug_port = 0;
+	u32 hotplug_ctrl;
+
+	/* Now, enable HPD */
+	for_each_intel_encoder(dev, intel_encoder) {
+		if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark
+				== HPD_ENABLED)
+			hotplug_port |= hpd_bxt[intel_encoder->hpd_pin];
+	}
+
+	/* Mask all HPD control bits */
+	hotplug_ctrl = I915_READ(BXT_HOTPLUG_CTL) & ~BXT_HOTPLUG_CTL_MASK;
+
+	/* Enable requested port in hotplug control */
+	/* TODO: implement (short) HPD support on port A */
+	WARN_ON_ONCE(hotplug_port & BXT_DE_PORT_HP_DDIA);
+	if (hotplug_port & BXT_DE_PORT_HP_DDIB)
+		hotplug_ctrl |= BXT_DDIB_HPD_ENABLE;
+	if (hotplug_port & BXT_DE_PORT_HP_DDIC)
+		hotplug_ctrl |= BXT_DDIC_HPD_ENABLE;
+	I915_WRITE(BXT_HOTPLUG_CTL, hotplug_ctrl);
+
+	/* Unmask DDI hotplug in IMR */
+	hotplug_ctrl = I915_READ(GEN8_DE_PORT_IMR) & ~hotplug_port;
+	I915_WRITE(GEN8_DE_PORT_IMR, hotplug_ctrl);
+
+	/* Enable DDI hotplug in IER */
+	hotplug_ctrl = I915_READ(GEN8_DE_PORT_IER) | hotplug_port;
+	I915_WRITE(GEN8_DE_PORT_IER, hotplug_ctrl);
+	POSTING_READ(GEN8_DE_PORT_IER);
+}
+
 static void ibx_irq_postinstall(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -4279,7 +4321,10 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
 		dev->driver->irq_uninstall = gen8_irq_uninstall;
 		dev->driver->enable_vblank = gen8_enable_vblank;
 		dev->driver->disable_vblank = gen8_disable_vblank;
-		dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
+		if (HAS_PCH_SPLIT(dev))
+			dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
+		else
+			dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
 	} else if (HAS_PCH_SPLIT(dev)) {
 		dev->driver->irq_handler = ironlake_irq_handler;
 		dev->driver->irq_preinstall = ironlake_irq_reset;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7d51aec..670a9d4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5256,10 +5256,16 @@ enum skl_disp_power_wells {
 #define GEN8_DE_PORT_IMR 0x44444
 #define GEN8_DE_PORT_IIR 0x44448
 #define GEN8_DE_PORT_IER 0x4444c
-#define  GEN8_PORT_DP_A_HOTPLUG		(1 << 3)
 #define  GEN9_AUX_CHANNEL_D		(1 << 27)
 #define  GEN9_AUX_CHANNEL_C		(1 << 26)
 #define  GEN9_AUX_CHANNEL_B		(1 << 25)
+#define  BXT_DE_PORT_HP_DDIC		(1 << 5)
+#define  BXT_DE_PORT_HP_DDIB		(1 << 4)
+#define  BXT_DE_PORT_HP_DDIA		(1 << 3)
+#define  BXT_DE_PORT_HOTPLUG_MASK	(BXT_DE_PORT_HP_DDIA | \
+					 BXT_DE_PORT_HP_DDIB | \
+					 BXT_DE_PORT_HP_DDIC)
+#define  GEN8_PORT_DP_A_HOTPLUG		(1 << 3)
 #define  GEN8_AUX_CHANNEL_A		(1 << 0)
 
 #define GEN8_DE_MISC_ISR 0x44460
@@ -5273,6 +5279,21 @@ enum skl_disp_power_wells {
 #define GEN8_PCU_IIR 0x444e8
 #define GEN8_PCU_IER 0x444ec
 
+/* BXT hotplug control */
+#define BXT_HOTPLUG_CTL			0xC4030
+#define   BXT_DDIA_HPD_ENABLE		(1 << 28)
+#define   BXT_DDIA_HPD_STATUS		(3 << 24)
+#define   BXT_DDIC_HPD_ENABLE		(1 << 12)
+#define   BXT_DDIC_HPD_STATUS		(3 << 8)
+#define   BXT_DDIB_HPD_ENABLE		(1 << 4)
+#define   BXT_DDIB_HPD_STATUS		(3 << 0)
+#define   BXT_HOTPLUG_CTL_MASK		(BXT_DDIA_HPD_ENABLE | \
+					 BXT_DDIB_HPD_ENABLE | \
+					 BXT_DDIC_HPD_ENABLE)
+#define   BXT_HPD_STATUS_MASK		(BXT_DDIA_HPD_STATUS | \
+					 BXT_DDIB_HPD_STATUS | \
+					 BXT_DDIC_HPD_STATUS)
+
 #define ILK_DISPLAY_CHICKEN2	0x42004
 /* Required on all Ironlake and Sandybridge according to the B-Spec. */
 #define  ILK_ELPIN_409_SELECT	(1 << 25)
-- 
1.9.1

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[PATCH v2 25/49] drm/i915/bxt: Add DDI hpd handler

[Imre Deak]

From: Shashank Sharma <shashank.sharma@intel.com>

This patch adds a hot plug interrupt handler function for BXT.
What this function typically does is:
1. Check if hot plug is enabled from hot plug control register.
2. Call hpd_irq_handler with appropriate trigger to detect a
   plug storm and schedule a bottom half.
3. Clear sticky status bits in hot plug control register..

v2: (jani)
- drop redundant unlikely()
- s/Todo/FIXME:/ in code comment
- declare 'found' var in the scope where it's used
- check for IS_BROXTON before handling BXT_DE_PORT_HOTPLUG_MASK

Reviewed-by: Satheeshakrishna M<satheeshakrishna.m@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Sigend-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 46 +++++++++++++++++++++++++++++++++++++++--
 1 file changed, 44 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 631484d..b06364f 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2152,6 +2152,38 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg)
 	return ret;
 }
 
+static void bxt_hpd_handler(struct drm_device *dev, uint32_t iir_status)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	uint32_t hp_control;
+	uint32_t hp_trigger;
+
+	/* Get the status */
+	hp_trigger = iir_status & BXT_DE_PORT_HOTPLUG_MASK;
+	hp_control = I915_READ(BXT_HOTPLUG_CTL);
+
+	/* Hotplug not enabled ? */
+	if (!(hp_control & BXT_HOTPLUG_CTL_MASK)) {
+		DRM_ERROR("Interrupt when HPD disabled\n");
+		return;
+	}
+
+	DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
+		hp_control & BXT_HOTPLUG_CTL_MASK);
+
+	/* Check for HPD storm and schedule bottom half */
+	intel_hpd_irq_handler(dev, hp_trigger, hp_control, hpd_bxt);
+
+	/*
+	 * FIXME: Save the hot plug status for bottom half before
+	 * clearing the sticky status bits, else the status will be
+	 * lost.
+	 */
+
+	/* Clear sticky bits in hpd status */
+	I915_WRITE(BXT_HOTPLUG_CTL, hp_control);
+}
+
 static irqreturn_t gen8_irq_handler(int irq, void *arg)
 {
 	struct drm_device *dev = arg;
@@ -2197,12 +2229,22 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
 	if (master_ctl & GEN8_DE_PORT_IRQ) {
 		tmp = I915_READ(GEN8_DE_PORT_IIR);
 		if (tmp) {
+			bool found = false;
+
 			I915_WRITE(GEN8_DE_PORT_IIR, tmp);
 			ret = IRQ_HANDLED;
 
-			if (tmp & aux_mask)
+			if (tmp & aux_mask) {
 				dp_aux_irq_handler(dev);
-			else
+				found = true;
+			}
+
+			if (IS_BROXTON(dev) && tmp & BXT_DE_PORT_HOTPLUG_MASK) {
+				bxt_hpd_handler(dev, tmp);
+				found = true;
+			}
+
+			if (!found)
 				DRM_ERROR("Unexpected DE Port interrupt\n");
 		}
 		else
-- 
1.9.1

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[PATCH v2 26/49] drm/i915/bxt: Add BXT support in gen8_irq functions

[Imre Deak]

From: Shashank Sharma <shashank.sharma@intel.com>

This patch adds conditional checks in gen8_irq functions
to support BXT. Most of the checks just look for PCH split
availability, and block the call to PCH interrupt functions if
not available.

v2: (jani)
- drop redundant TODO comment about PCH IRQ flags on BXT
- check HAS_PCH_SPLIT instead of IS_BROXTON when handling PCH specific
  IRQ events in gen8_irq_handler()
- check HAS_PCH_SPLIT before calling the function instead of a
  corresponding early return within the called function for
  ibx_irq_reset(), ibx_irq_pre_postinstall(), ibx_irq_postinstall()

Reviewed-by: Satheeshakrishna M<satheeshakrishna.m@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Shashank Sharma <ppashank.sharma@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 21 ++++++++++++++-------
 1 file changed, 14 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index b06364f..a185f44 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2297,7 +2297,8 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
 			DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
 	}
 
-	if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) {
+	if (HAS_PCH_SPLIT(dev) && !HAS_PCH_NOP(dev) &&
+	    master_ctl & GEN8_DE_PCH_IRQ) {
 		/*
 		 * FIXME(BDW): Assume for now that the new interrupt handling
 		 * scheme also closed the SDE interrupt handling race we've seen
@@ -3073,7 +3074,8 @@ static void ironlake_irq_reset(struct drm_device *dev)
 
 	gen5_gt_irq_reset(dev);
 
-	ibx_irq_reset(dev);
+	if (HAS_PCH_SPLIT(dev))
+		ibx_irq_reset(dev);
 }
 
 static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
@@ -3133,7 +3135,8 @@ static void gen8_irq_reset(struct drm_device *dev)
 	GEN5_IRQ_RESET(GEN8_DE_MISC_);
 	GEN5_IRQ_RESET(GEN8_PCU_);
 
-	ibx_irq_reset(dev);
+	if (HAS_PCH_SPLIT(dev))
+		ibx_irq_reset(dev);
 }
 
 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
@@ -3323,13 +3326,15 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
 
 	I915_WRITE(HWSTAM, 0xeffe);
 
-	ibx_irq_pre_postinstall(dev);
+	if (HAS_PCH_SPLIT(dev))
+		ibx_irq_pre_postinstall(dev);
 
 	GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
 
 	gen5_gt_irq_postinstall(dev);
 
-	ibx_irq_postinstall(dev);
+	if (HAS_PCH_SPLIT(dev))
+		ibx_irq_postinstall(dev);
 
 	if (IS_IRONLAKE_M(dev)) {
 		/* Enable PCU event interrupts
@@ -3545,12 +3550,14 @@ static int gen8_irq_postinstall(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
-	ibx_irq_pre_postinstall(dev);
+	if (HAS_PCH_SPLIT(dev))
+		ibx_irq_pre_postinstall(dev);
 
 	gen8_gt_irq_postinstall(dev_priv);
 	gen8_de_irq_postinstall(dev_priv);
 
-	ibx_irq_postinstall(dev);
+	if (HAS_PCH_SPLIT(dev))
+		ibx_irq_postinstall(dev);
 
 	I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
 	POSTING_READ(GEN8_MASTER_IRQ);
-- 
1.9.1

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[PATCH v4 27/49] drm/i915/bxt: Enable GMBUS IRQ

[Imre Deak]

From: Shashank Sharma <shashank.sharma@intel.com>

GMBUS interrupt has been moved to CPU side in BXT.
What this patch does is:
1. Enable GMBUS IRQ in de_post_install function
2. Handle this interrupt as a port interrupt in display irq
   handler

v2: Rebase on top of the for_each_pipe() change adding dev_priv as
    first argument (Damien).
v3: read BXT_DE_PORT_GMBUS IIR flag only on BXT on other platforms
    it's reserved (imre)
v4: (jani)
- remove redundant 'BXT GMBUS' comment
- fix formatting of BXT_DE_PORT_GMBUS definition

Reviewed-by: Satheeshakrishna M <satheeshakrishna.m@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com> (v1)
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 14 +++++++++++---
 drivers/gpu/drm/i915/i915_reg.h |  1 +
 2 files changed, 12 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index a185f44..5417d5a 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2244,6 +2244,11 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
 				found = true;
 			}
 
+			if (IS_BROXTON(dev) && (tmp & BXT_DE_PORT_GMBUS)) {
+				gmbus_irq_handler(dev);
+				found = true;
+			}
+
 			if (!found)
 				DRM_ERROR("Unexpected DE Port interrupt\n");
 		}
@@ -3518,13 +3523,16 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
 	uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
 	uint32_t de_pipe_enables;
 	int pipe;
-	u32 aux_en = GEN8_AUX_CHANNEL_A;
+	u32 de_port_en = GEN8_AUX_CHANNEL_A;
 
 	if (IS_GEN9(dev_priv)) {
 		de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
 				  GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
-		aux_en |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
+		de_port_en |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
 			GEN9_AUX_CHANNEL_D;
+
+		if (IS_BROXTON(dev_priv))
+			de_port_en |= BXT_DE_PORT_GMBUS;
 	} else
 		de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
 				  GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
@@ -3543,7 +3551,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
 					  dev_priv->de_irq_mask[pipe],
 					  de_pipe_enables);
 
-	GEN5_IRQ_INIT(GEN8_DE_PORT_, ~aux_en, aux_en);
+	GEN5_IRQ_INIT(GEN8_DE_PORT_, ~de_port_en, de_port_en);
 }
 
 static int gen8_irq_postinstall(struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 670a9d4..4950aa4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5266,6 +5266,7 @@ enum skl_disp_power_wells {
 					 BXT_DE_PORT_HP_DDIB | \
 					 BXT_DE_PORT_HP_DDIC)
 #define  GEN8_PORT_DP_A_HOTPLUG		(1 << 3)
+#define  BXT_DE_PORT_GMBUS		(1 << 1)
 #define  GEN8_AUX_CHANNEL_A		(1 << 0)
 
 #define GEN8_DE_MISC_ISR 0x44460
-- 
1.9.1

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[PATCH 35/49] drm/i915/bxt: fix panel fitter setup in crtc disable/enable

[sagar.a.kamble]

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[PATCH 35/49] drm/i915/bxt: fix panel fitter setup in crtc disable/enable

[sagar.a.kamble]

For updated patch that is coming up per http://lists.freedesktop.org/archives/intel-gfx/2015-March/062315.html
Reviewed-by: Sagar Kamble <sagar.a.kamble at intel.com>
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[PATCH 34/49] drm/i915/bxt: Restrict PORT_CLK_SEL programming below gen9

[sagar.a.kamble]

For patch at http://lists.freedesktop.org/archives/intel-gfx/2015-March/062169.html
Reviewed-by: Sagar Kamble <sagar.a.kamble at intel.com>
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[PATCH 32/49] drm/i915/bxt: Implement enable/disable for Display C9 state

[sagar.a.kamble]

These are review comments for 
	1) http://lists.freedesktop.org/archives/intel-gfx/2015-March/062167.html
	2) http://lists.freedesktop.org/archives/intel-gfx/2015-March/062168.html

Couple of comments:
1) Defines for DC_STATE_EN* are coming up as part of http://lists.freedesktop.org/archives/intel-gfx/2015-April/063640.html.
Need to rebase this patch on top of it then or vice-versa.
2) DC5 has to enabled back after disabling DC9 if PW2 is power gated.

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Re: [PATCH 35/49] drm/i915/bxt: fix panel fitter setup in crtc disable/enable

[Daniel Vetter]

On Sun, Apr 12, 2015 at 03:49:34PM +0530, sagar.a.kamble@intel.com wrote:
> For updated patch that is coming up per http://lists.freedesktop.org/archives/intel-gfx/2015-March/062315.html
> Reviewed-by: Sagar Kamble <sagar.a.kamble at intel.com>

Please don't reply to mails by linking to their archive link because that
completely rips apart the discussion. Also the mailman archive isn't fully
stable, much better to link to gman using the Message-Id if there is a
need for that. But review/discussions really should be direct replies.

Thanks, Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [PATCH 32/49] drm/i915/bxt: Implement enable/disable for Display C9 state

[Imre Deak]

On su, 2015-04-12 at 16:02 +0530, sagar.a.kamble@intel.com wrote:
> These are review comments for 
> 	1) http://lists.freedesktop.org/archives/intel-gfx/2015-March/062167.html
> 	2) http://lists.freedesktop.org/archives/intel-gfx/2015-March/062168.html

It'd be better to have inlined review comments responding to the
original email.

> Couple of comments:
> 1) Defines for DC_STATE_EN* are coming up as part of
> http://lists.freedesktop.org/archives/intel-gfx/2015-April/063640.html.
> Need to rebase this patch on top of it then or vice-versa.

Yes, I can rebase this once Animesh's patchset gets merged. It's also a
trivial conflict that can be easily resolved while merging, so it's not
an issue imo.

> 2) DC5 has to enabled back after disabling DC9 if PW2 is power gated.

BXT DC5/runtime PM support will be added only later. At that point the
enabling of DC5 should be done from bxt_resume_prepare() if the the DMC
firmware is loaded. For now I'd just add the missing TODO comment about
this to bxt_resume_prepare() as you suggested elsewhere.

--Imre

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Re: [PATCH 32/49] drm/i915/bxt: Implement enable/disable for Display C9 state

[Sagar Arun Kamble]

On Mon, 2015-04-13 at 13:09 +0300, Imre Deak wrote:
> On su, 2015-04-12 at 16:02 +0530, sagar.a.kamble@intel.com wrote:
> > These are review comments for 
> > 	1) http://lists.freedesktop.org/archives/intel-gfx/2015-March/062167.html
> > 	2) http://lists.freedesktop.org/archives/intel-gfx/2015-March/062168.html
> 
> It'd be better to have inlined review comments responding to the
> original email.
Yes. Sorry for the inconvenience. My ML subscription was in digest mode.
So replied using only message-id knowing from Deepak. Now I have
switched to individual mails.
> 
> > Couple of comments:
> > 1) Defines for DC_STATE_EN* are coming up as part of
> > http://lists.freedesktop.org/archives/intel-gfx/2015-April/063640.html.
> > Need to rebase this patch on top of it then or vice-versa.
> 
> Yes, I can rebase this once Animesh's patchset gets merged. It's also a
> trivial conflict that can be easily resolved while merging, so it's not
> an issue imo.
> 
> > 2) DC5 has to enabled back after disabling DC9 if PW2 is power gated.
> 
> BXT DC5/runtime PM support will be added only later. At that point the
> enabling of DC5 should be done from bxt_resume_prepare() if the the DMC
> firmware is loaded. For now I'd just add the missing TODO comment about
> this to bxt_resume_prepare() as you suggested elsewhere.
Thanks.
Reviewed-by: Sagar Kamble <sagar.a.kamble at intel.com>
> 
> --Imre
> 


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Re: [PATCH 34/49] drm/i915/bxt: Restrict PORT_CLK_SEL programming below gen9

[Damien Lespiau]

On Sun, Apr 12, 2015 at 03:52:12PM +0530, sagar.a.kamble@intel.com wrote:
> For patch at http://lists.freedesktop.org/archives/intel-gfx/2015-March/062169.html
> Reviewed-by: Sagar Kamble <sagar.a.kamble at intel.com>

Usually reviews are done as a reply to the patch, but maybe you didn't
receive the earlier mail?

-		I915_WRITE(PORT_CLK_SEL(port),
-			   intel_crtc->config->ddi_pll_sel);
+		/* FIXME: add support for SKL */
+		if (!INTEL_INFO(dev)->gen < 9)
+			I915_WRITE(PORT_CLK_SEL(port),
+				   intel_crtc->config->ddi_pll_sel);
 
This '!' looks fishy to me.

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Re: [PATCH 34/49] drm/i915/bxt: Restrict PORT_CLK_SEL programming below gen9

[Imre Deak]

On ma, 2015-04-13 at 14:21 +0100, Damien Lespiau wrote:
> On Sun, Apr 12, 2015 at 03:52:12PM +0530, sagar.a.kamble@intel.com wrote:
> > For patch at http://lists.freedesktop.org/archives/intel-gfx/2015-March/062169.html
> > Reviewed-by: Sagar Kamble <sagar.a.kamble at intel.com>
> 
> Usually reviews are done as a reply to the patch, but maybe you didn't
> receive the earlier mail?
> 
> -		I915_WRITE(PORT_CLK_SEL(port),
> -			   intel_crtc->config->ddi_pll_sel);
> +		/* FIXME: add support for SKL */
> +		if (!INTEL_INFO(dev)->gen < 9)
> +			I915_WRITE(PORT_CLK_SEL(port),
> +				   intel_crtc->config->ddi_pll_sel);
>  
> This '!' looks fishy to me.

Yes, that's a typo from me. Will fix it, thanks for catching it.

--Imre

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Re: [PATCH v7 24/49] drm/i915/bxt: DDI Hotplug interrupt setup

[Jani Nikula]

On Fri, 10 Apr 2015, Imre Deak <imre.deak@intel.com> wrote:
> From: Shashank Sharma <shashank.sharma@intel.com>
>
> In BXT, DDI hotplug control has been moved to CPU from PCH.
> This patch adds a new IRQ setup function for BXT which:
> 1. Checks which HPD ports are requested to be enabled by encoders.
> 2. Enables those ports in the hot plug control register.
> 3. Un-masks these port interrupts in the IMR register.
> 4. Enables these port interrupts in the IER register.
>
> V3: Kept the default HPD filter count to default (500 us) as per
>     satheesh's comment
> v4: Remove unused HPD filter defines (Damien)
> v5: warn if trying to setup HPD on port A (imre)
> v6: fix order of definitions for register bitfields (Daniel)
> v7: (jani)
> - define the size of the hpd_bxt array explicitly for bound checking
> - use for_each_intel_encoder instead of open coding it
> - fix format/order of definitions for BXT_HOTPLUG_CTL reg bitfields
>
> Reviewed-by: Satheeshakrishna M <satheeshakrishna.m@intel.com>
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> Signed-off-by: Shashank Sharma <shashank.sharma@intel.com> (v4)
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/i915_irq.c | 47 ++++++++++++++++++++++++++++++++++++++++-
>  drivers/gpu/drm/i915/i915_reg.h | 23 +++++++++++++++++++-
>  2 files changed, 68 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 46bcbff..631484d 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -88,6 +88,12 @@ static const u32 hpd_status_i915[HPD_NUM_PINS] = { /* i915 and valleyview are th
>  	[HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
>  };
>  
> +/* BXT hpd list */
> +static const u32 hpd_bxt[HPD_NUM_PINS] = {
> +	[HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
> +	[HPD_PORT_C] = BXT_DE_PORT_HP_DDIC
> +};
> +
>  /* IIR can theoretically queue up two events. Be paranoid. */
>  #define GEN8_IRQ_RESET_NDX(type, which) do { \
>  	I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
> @@ -3159,6 +3165,42 @@ static void ibx_hpd_irq_setup(struct drm_device *dev)
>  	I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
>  }
>  
> +static void bxt_hpd_irq_setup(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct intel_encoder *intel_encoder;
> +	u32 hotplug_port = 0;
> +	u32 hotplug_ctrl;
> +
> +	/* Now, enable HPD */
> +	for_each_intel_encoder(dev, intel_encoder) {
> +		if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark
> +				== HPD_ENABLED)
> +			hotplug_port |= hpd_bxt[intel_encoder->hpd_pin];
> +	}
> +
> +	/* Mask all HPD control bits */
> +	hotplug_ctrl = I915_READ(BXT_HOTPLUG_CTL) & ~BXT_HOTPLUG_CTL_MASK;
> +
> +	/* Enable requested port in hotplug control */
> +	/* TODO: implement (short) HPD support on port A */
> +	WARN_ON_ONCE(hotplug_port & BXT_DE_PORT_HP_DDIA);
> +	if (hotplug_port & BXT_DE_PORT_HP_DDIB)
> +		hotplug_ctrl |= BXT_DDIB_HPD_ENABLE;
> +	if (hotplug_port & BXT_DE_PORT_HP_DDIC)
> +		hotplug_ctrl |= BXT_DDIC_HPD_ENABLE;
> +	I915_WRITE(BXT_HOTPLUG_CTL, hotplug_ctrl);
> +
> +	/* Unmask DDI hotplug in IMR */
> +	hotplug_ctrl = I915_READ(GEN8_DE_PORT_IMR) & ~hotplug_port;
> +	I915_WRITE(GEN8_DE_PORT_IMR, hotplug_ctrl);
> +
> +	/* Enable DDI hotplug in IER */
> +	hotplug_ctrl = I915_READ(GEN8_DE_PORT_IER) | hotplug_port;
> +	I915_WRITE(GEN8_DE_PORT_IER, hotplug_ctrl);
> +	POSTING_READ(GEN8_DE_PORT_IER);
> +}
> +
>  static void ibx_irq_postinstall(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -4279,7 +4321,10 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
>  		dev->driver->irq_uninstall = gen8_irq_uninstall;
>  		dev->driver->enable_vblank = gen8_enable_vblank;
>  		dev->driver->disable_vblank = gen8_disable_vblank;
> -		dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
> +		if (HAS_PCH_SPLIT(dev))
> +			dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
> +		else
> +			dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
>  	} else if (HAS_PCH_SPLIT(dev)) {
>  		dev->driver->irq_handler = ironlake_irq_handler;
>  		dev->driver->irq_preinstall = ironlake_irq_reset;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7d51aec..670a9d4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5256,10 +5256,16 @@ enum skl_disp_power_wells {
>  #define GEN8_DE_PORT_IMR 0x44444
>  #define GEN8_DE_PORT_IIR 0x44448
>  #define GEN8_DE_PORT_IER 0x4444c
> -#define  GEN8_PORT_DP_A_HOTPLUG		(1 << 3)
>  #define  GEN9_AUX_CHANNEL_D		(1 << 27)
>  #define  GEN9_AUX_CHANNEL_C		(1 << 26)
>  #define  GEN9_AUX_CHANNEL_B		(1 << 25)
> +#define  BXT_DE_PORT_HP_DDIC		(1 << 5)
> +#define  BXT_DE_PORT_HP_DDIB		(1 << 4)
> +#define  BXT_DE_PORT_HP_DDIA		(1 << 3)
> +#define  BXT_DE_PORT_HOTPLUG_MASK	(BXT_DE_PORT_HP_DDIA | \
> +					 BXT_DE_PORT_HP_DDIB | \
> +					 BXT_DE_PORT_HP_DDIC)
> +#define  GEN8_PORT_DP_A_HOTPLUG		(1 << 3)
>  #define  GEN8_AUX_CHANNEL_A		(1 << 0)
>  
>  #define GEN8_DE_MISC_ISR 0x44460
> @@ -5273,6 +5279,21 @@ enum skl_disp_power_wells {
>  #define GEN8_PCU_IIR 0x444e8
>  #define GEN8_PCU_IER 0x444ec
>  
> +/* BXT hotplug control */
> +#define BXT_HOTPLUG_CTL			0xC4030
> +#define   BXT_DDIA_HPD_ENABLE		(1 << 28)
> +#define   BXT_DDIA_HPD_STATUS		(3 << 24)
> +#define   BXT_DDIC_HPD_ENABLE		(1 << 12)
> +#define   BXT_DDIC_HPD_STATUS		(3 << 8)
> +#define   BXT_DDIB_HPD_ENABLE		(1 << 4)
> +#define   BXT_DDIB_HPD_STATUS		(3 << 0)
> +#define   BXT_HOTPLUG_CTL_MASK		(BXT_DDIA_HPD_ENABLE | \
> +					 BXT_DDIB_HPD_ENABLE | \
> +					 BXT_DDIC_HPD_ENABLE)
> +#define   BXT_HPD_STATUS_MASK		(BXT_DDIA_HPD_STATUS | \
> +					 BXT_DDIB_HPD_STATUS | \
> +					 BXT_DDIC_HPD_STATUS)
> +
>  #define ILK_DISPLAY_CHICKEN2	0x42004
>  /* Required on all Ironlake and Sandybridge according to the B-Spec. */
>  #define  ILK_ELPIN_409_SELECT	(1 << 25)
> -- 
> 1.9.1
>

-- 
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Re: [PATCH v2 25/49] drm/i915/bxt: Add DDI hpd handler

[Jani Nikula]

On Fri, 10 Apr 2015, Imre Deak <imre.deak@intel.com> wrote:
> From: Shashank Sharma <shashank.sharma@intel.com>
>
> This patch adds a hot plug interrupt handler function for BXT.
> What this function typically does is:
> 1. Check if hot plug is enabled from hot plug control register.
> 2. Call hpd_irq_handler with appropriate trigger to detect a
>    plug storm and schedule a bottom half.
> 3. Clear sticky status bits in hot plug control register..
>
> v2: (jani)
> - drop redundant unlikely()
> - s/Todo/FIXME:/ in code comment
> - declare 'found' var in the scope where it's used
> - check for IS_BROXTON before handling BXT_DE_PORT_HOTPLUG_MASK
>
> Reviewed-by: Satheeshakrishna M<satheeshakrishna.m@intel.com>
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
> Sigend-off-by: Imre Deak <imre.deak@intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_irq.c | 46 +++++++++++++++++++++++++++++++++++++++--
>  1 file changed, 44 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 631484d..b06364f 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2152,6 +2152,38 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg)
>  	return ret;
>  }
>  
> +static void bxt_hpd_handler(struct drm_device *dev, uint32_t iir_status)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	uint32_t hp_control;
> +	uint32_t hp_trigger;
> +
> +	/* Get the status */
> +	hp_trigger = iir_status & BXT_DE_PORT_HOTPLUG_MASK;
> +	hp_control = I915_READ(BXT_HOTPLUG_CTL);
> +
> +	/* Hotplug not enabled ? */
> +	if (!(hp_control & BXT_HOTPLUG_CTL_MASK)) {
> +		DRM_ERROR("Interrupt when HPD disabled\n");
> +		return;
> +	}
> +
> +	DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
> +		hp_control & BXT_HOTPLUG_CTL_MASK);
> +
> +	/* Check for HPD storm and schedule bottom half */
> +	intel_hpd_irq_handler(dev, hp_trigger, hp_control, hpd_bxt);
> +
> +	/*
> +	 * FIXME: Save the hot plug status for bottom half before
> +	 * clearing the sticky status bits, else the status will be
> +	 * lost.
> +	 */
> +
> +	/* Clear sticky bits in hpd status */
> +	I915_WRITE(BXT_HOTPLUG_CTL, hp_control);
> +}
> +
>  static irqreturn_t gen8_irq_handler(int irq, void *arg)
>  {
>  	struct drm_device *dev = arg;
> @@ -2197,12 +2229,22 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
>  	if (master_ctl & GEN8_DE_PORT_IRQ) {
>  		tmp = I915_READ(GEN8_DE_PORT_IIR);
>  		if (tmp) {
> +			bool found = false;
> +
>  			I915_WRITE(GEN8_DE_PORT_IIR, tmp);
>  			ret = IRQ_HANDLED;
>  
> -			if (tmp & aux_mask)
> +			if (tmp & aux_mask) {
>  				dp_aux_irq_handler(dev);
> -			else
> +				found = true;
> +			}
> +
> +			if (IS_BROXTON(dev) && tmp & BXT_DE_PORT_HOTPLUG_MASK) {
> +				bxt_hpd_handler(dev, tmp);
> +				found = true;
> +			}
> +
> +			if (!found)
>  				DRM_ERROR("Unexpected DE Port interrupt\n");
>  		}
>  		else
> -- 
> 1.9.1
>

-- 
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Re: [PATCH v2 26/49] drm/i915/bxt: Add BXT support in gen8_irq functions

[Jani Nikula]

On Fri, 10 Apr 2015, Imre Deak <imre.deak@intel.com> wrote:
> From: Shashank Sharma <shashank.sharma@intel.com>
>
> This patch adds conditional checks in gen8_irq functions
> to support BXT. Most of the checks just look for PCH split
> availability, and block the call to PCH interrupt functions if
> not available.
>
> v2: (jani)
> - drop redundant TODO comment about PCH IRQ flags on BXT
> - check HAS_PCH_SPLIT instead of IS_BROXTON when handling PCH specific
>   IRQ events in gen8_irq_handler()
> - check HAS_PCH_SPLIT before calling the function instead of a
>   corresponding early return within the called function for
>   ibx_irq_reset(), ibx_irq_pre_postinstall(), ibx_irq_postinstall()
>
> Reviewed-by: Satheeshakrishna M<satheeshakrishna.m@intel.com>
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> Signed-off-by: Shashank Sharma <ppashank.sharma@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_irq.c | 21 ++++++++++++++-------
>  1 file changed, 14 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index b06364f..a185f44 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2297,7 +2297,8 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
>  			DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
>  	}
>  
> -	if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) {
> +	if (HAS_PCH_SPLIT(dev) && !HAS_PCH_NOP(dev) &&
> +	    master_ctl & GEN8_DE_PCH_IRQ) {
>  		/*
>  		 * FIXME(BDW): Assume for now that the new interrupt handling
>  		 * scheme also closed the SDE interrupt handling race we've seen
> @@ -3073,7 +3074,8 @@ static void ironlake_irq_reset(struct drm_device *dev)
>  
>  	gen5_gt_irq_reset(dev);
>  
> -	ibx_irq_reset(dev);
> +	if (HAS_PCH_SPLIT(dev))
> +		ibx_irq_reset(dev);
>  }
>  
>  static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
> @@ -3133,7 +3135,8 @@ static void gen8_irq_reset(struct drm_device *dev)
>  	GEN5_IRQ_RESET(GEN8_DE_MISC_);
>  	GEN5_IRQ_RESET(GEN8_PCU_);
>  
> -	ibx_irq_reset(dev);
> +	if (HAS_PCH_SPLIT(dev))
> +		ibx_irq_reset(dev);
>  }
>  
>  void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
> @@ -3323,13 +3326,15 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
>  
>  	I915_WRITE(HWSTAM, 0xeffe);
>  
> -	ibx_irq_pre_postinstall(dev);
> +	if (HAS_PCH_SPLIT(dev))
> +		ibx_irq_pre_postinstall(dev);
>  
>  	GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
>  
>  	gen5_gt_irq_postinstall(dev);
>  
> -	ibx_irq_postinstall(dev);
> +	if (HAS_PCH_SPLIT(dev))
> +		ibx_irq_postinstall(dev);

/me scratches head, we shouldn't ever call ironlake_irq_postinstall on
bxt, should we? Did I miss something?

With this hunk dropped, I think the patch looks good.

BR,
Jani.


>  
>  	if (IS_IRONLAKE_M(dev)) {
>  		/* Enable PCU event interrupts
> @@ -3545,12 +3550,14 @@ static int gen8_irq_postinstall(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  
> -	ibx_irq_pre_postinstall(dev);
> +	if (HAS_PCH_SPLIT(dev))
> +		ibx_irq_pre_postinstall(dev);
>  
>  	gen8_gt_irq_postinstall(dev_priv);
>  	gen8_de_irq_postinstall(dev_priv);
>  
> -	ibx_irq_postinstall(dev);
> +	if (HAS_PCH_SPLIT(dev))
> +		ibx_irq_postinstall(dev);
>  
>  	I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
>  	POSTING_READ(GEN8_MASTER_IRQ);
> -- 
> 1.9.1
>

-- 
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Re: [PATCH v4 27/49] drm/i915/bxt: Enable GMBUS IRQ

[Jani Nikula]

On Fri, 10 Apr 2015, Imre Deak <imre.deak@intel.com> wrote:
> From: Shashank Sharma <shashank.sharma@intel.com>
>
> GMBUS interrupt has been moved to CPU side in BXT.
> What this patch does is:
> 1. Enable GMBUS IRQ in de_post_install function
> 2. Handle this interrupt as a port interrupt in display irq
>    handler
>
> v2: Rebase on top of the for_each_pipe() change adding dev_priv as
>     first argument (Damien).
> v3: read BXT_DE_PORT_GMBUS IIR flag only on BXT on other platforms
>     it's reserved (imre)
> v4: (jani)
> - remove redundant 'BXT GMBUS' comment
> - fix formatting of BXT_DE_PORT_GMBUS definition
>
> Reviewed-by: Satheeshakrishna M <satheeshakrishna.m@intel.com>
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> Signed-off-by: Shashank Sharma <shashank.sharma@intel.com> (v1)
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>

Yup. ^

> ---
>  drivers/gpu/drm/i915/i915_irq.c | 14 +++++++++++---
>  drivers/gpu/drm/i915/i915_reg.h |  1 +
>  2 files changed, 12 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index a185f44..5417d5a 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2244,6 +2244,11 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
>  				found = true;
>  			}
>  
> +			if (IS_BROXTON(dev) && (tmp & BXT_DE_PORT_GMBUS)) {
> +				gmbus_irq_handler(dev);
> +				found = true;
> +			}
> +
>  			if (!found)
>  				DRM_ERROR("Unexpected DE Port interrupt\n");
>  		}
> @@ -3518,13 +3523,16 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
>  	uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
>  	uint32_t de_pipe_enables;
>  	int pipe;
> -	u32 aux_en = GEN8_AUX_CHANNEL_A;
> +	u32 de_port_en = GEN8_AUX_CHANNEL_A;
>  
>  	if (IS_GEN9(dev_priv)) {
>  		de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
>  				  GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
> -		aux_en |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
> +		de_port_en |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
>  			GEN9_AUX_CHANNEL_D;
> +
> +		if (IS_BROXTON(dev_priv))
> +			de_port_en |= BXT_DE_PORT_GMBUS;
>  	} else
>  		de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
>  				  GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
> @@ -3543,7 +3551,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
>  					  dev_priv->de_irq_mask[pipe],
>  					  de_pipe_enables);
>  
> -	GEN5_IRQ_INIT(GEN8_DE_PORT_, ~aux_en, aux_en);
> +	GEN5_IRQ_INIT(GEN8_DE_PORT_, ~de_port_en, de_port_en);
>  }
>  
>  static int gen8_irq_postinstall(struct drm_device *dev)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 670a9d4..4950aa4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5266,6 +5266,7 @@ enum skl_disp_power_wells {
>  					 BXT_DE_PORT_HP_DDIB | \
>  					 BXT_DE_PORT_HP_DDIC)
>  #define  GEN8_PORT_DP_A_HOTPLUG		(1 << 3)
> +#define  BXT_DE_PORT_GMBUS		(1 << 1)
>  #define  GEN8_AUX_CHANNEL_A		(1 << 0)
>  
>  #define GEN8_DE_MISC_ISR 0x44460
> -- 
> 1.9.1
>

-- 
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Re: [PATCH v2 26/49] drm/i915/bxt: Add BXT support in gen8_irq functions

[Imre Deak]

On ma, 2015-04-13 at 16:51 +0300, Jani Nikula wrote:
> On Fri, 10 Apr 2015, Imre Deak <imre.deak@intel.com> wrote:
> > From: Shashank Sharma <shashank.sharma@intel.com>
> >
> > This patch adds conditional checks in gen8_irq functions
> > to support BXT. Most of the checks just look for PCH split
> > availability, and block the call to PCH interrupt functions if
> > not available.
> >
> > v2: (jani)
> > - drop redundant TODO comment about PCH IRQ flags on BXT
> > - check HAS_PCH_SPLIT instead of IS_BROXTON when handling PCH specific
> >   IRQ events in gen8_irq_handler()
> > - check HAS_PCH_SPLIT before calling the function instead of a
> >   corresponding early return within the called function for
> >   ibx_irq_reset(), ibx_irq_pre_postinstall(), ibx_irq_postinstall()
> >
> > Reviewed-by: Satheeshakrishna M<satheeshakrishna.m@intel.com>
> > Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> > Signed-off-by: Shashank Sharma <ppashank.sharma@intel.com>
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_irq.c | 21 ++++++++++++++-------
> >  1 file changed, 14 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> > index b06364f..a185f44 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -2297,7 +2297,8 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
> >  			DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
> >  	}
> >  
> > -	if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) {
> > +	if (HAS_PCH_SPLIT(dev) && !HAS_PCH_NOP(dev) &&
> > +	    master_ctl & GEN8_DE_PCH_IRQ) {
> >  		/*
> >  		 * FIXME(BDW): Assume for now that the new interrupt handling
> >  		 * scheme also closed the SDE interrupt handling race we've seen
> > @@ -3073,7 +3074,8 @@ static void ironlake_irq_reset(struct drm_device *dev)
> >  
> >  	gen5_gt_irq_reset(dev);
> >  
> > -	ibx_irq_reset(dev);
> > +	if (HAS_PCH_SPLIT(dev))
> > +		ibx_irq_reset(dev);
> >  }
> >  
> >  static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
> > @@ -3133,7 +3135,8 @@ static void gen8_irq_reset(struct drm_device *dev)
> >  	GEN5_IRQ_RESET(GEN8_DE_MISC_);
> >  	GEN5_IRQ_RESET(GEN8_PCU_);
> >  
> > -	ibx_irq_reset(dev);
> > +	if (HAS_PCH_SPLIT(dev))
> > +		ibx_irq_reset(dev);
> >  }
> >  
> >  void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
> > @@ -3323,13 +3326,15 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
> >  
> >  	I915_WRITE(HWSTAM, 0xeffe);
> >  
> > -	ibx_irq_pre_postinstall(dev);
> > +	if (HAS_PCH_SPLIT(dev))
> > +		ibx_irq_pre_postinstall(dev);
> >  
> >  	GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
> >  
> >  	gen5_gt_irq_postinstall(dev);
> >  
> > -	ibx_irq_postinstall(dev);
> > +	if (HAS_PCH_SPLIT(dev))
> > +		ibx_irq_postinstall(dev);
> 
> /me scratches head, we shouldn't ever call ironlake_irq_postinstall on
> bxt, should we? Did I miss something?

Nope, I just added the check blindly to all call sites. But here
HAS_PCH_SPLIT happens to be true of course, so yea it's not needed.

> With this hunk dropped, I think the patch looks good.
> 
> BR,
> Jani.
> 
> 
> >  
> >  	if (IS_IRONLAKE_M(dev)) {
> >  		/* Enable PCU event interrupts
> > @@ -3545,12 +3550,14 @@ static int gen8_irq_postinstall(struct drm_device *dev)
> >  {
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> >  
> > -	ibx_irq_pre_postinstall(dev);
> > +	if (HAS_PCH_SPLIT(dev))
> > +		ibx_irq_pre_postinstall(dev);
> >  
> >  	gen8_gt_irq_postinstall(dev_priv);
> >  	gen8_de_irq_postinstall(dev_priv);
> >  
> > -	ibx_irq_postinstall(dev);
> > +	if (HAS_PCH_SPLIT(dev))
> > +		ibx_irq_postinstall(dev);
> >  
> >  	I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
> >  	POSTING_READ(GEN8_MASTER_IRQ);
> > -- 
> > 1.9.1
> >
> 


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[PATCH v3 26/49] drm/i915/bxt: Add BXT support in gen8_irq functions

[Imre Deak]

From: Shashank Sharma <shashank.sharma@intel.com>

This patch adds conditional checks in gen8_irq functions
to support BXT. Most of the checks just look for PCH split
availability, and block the call to PCH interrupt functions if
not available.

v2: (jani)
- drop redundant TODO comment about PCH IRQ flags on BXT
- check HAS_PCH_SPLIT instead of IS_BROXTON when handling PCH specific
  IRQ events in gen8_irq_handler()
- check HAS_PCH_SPLIT before calling the function instead of a
  corresponding early return within the called function for
  ibx_irq_reset(), ibx_irq_pre_postinstall(), ibx_irq_postinstall()
v3: (jani)
- in ironlake_irq_postinstall() and ironlake_irq_reset() HAS_PCH_SPLIT
  is always true, so drop the check for it

Reviewed-by: Satheeshakrishna M<satheeshakrishna.m@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Shashank Sharma <ppashank.sharma@intel.com> (v1)
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index b06364f..b0cd7a9 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2297,7 +2297,8 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
 			DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
 	}
 
-	if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) {
+	if (HAS_PCH_SPLIT(dev) && !HAS_PCH_NOP(dev) &&
+	    master_ctl & GEN8_DE_PCH_IRQ) {
 		/*
 		 * FIXME(BDW): Assume for now that the new interrupt handling
 		 * scheme also closed the SDE interrupt handling race we've seen
@@ -3133,7 +3134,8 @@ static void gen8_irq_reset(struct drm_device *dev)
 	GEN5_IRQ_RESET(GEN8_DE_MISC_);
 	GEN5_IRQ_RESET(GEN8_PCU_);
 
-	ibx_irq_reset(dev);
+	if (HAS_PCH_SPLIT(dev))
+		ibx_irq_reset(dev);
 }
 
 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
@@ -3545,12 +3547,14 @@ static int gen8_irq_postinstall(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
-	ibx_irq_pre_postinstall(dev);
+	if (HAS_PCH_SPLIT(dev))
+		ibx_irq_pre_postinstall(dev);
 
 	gen8_gt_irq_postinstall(dev_priv);
 	gen8_de_irq_postinstall(dev_priv);
 
-	ibx_irq_postinstall(dev);
+	if (HAS_PCH_SPLIT(dev))
+		ibx_irq_postinstall(dev);
 
 	I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
 	POSTING_READ(GEN8_MASTER_IRQ);
-- 
1.9.1

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Re: [PATCH v3 26/49] drm/i915/bxt: Add BXT support in gen8_irq functions

[Jani Nikula]

On Mon, 13 Apr 2015, Imre Deak <imre.deak@intel.com> wrote:
> From: Shashank Sharma <shashank.sharma@intel.com>
>
> This patch adds conditional checks in gen8_irq functions
> to support BXT. Most of the checks just look for PCH split
> availability, and block the call to PCH interrupt functions if
> not available.
>
> v2: (jani)
> - drop redundant TODO comment about PCH IRQ flags on BXT
> - check HAS_PCH_SPLIT instead of IS_BROXTON when handling PCH specific
>   IRQ events in gen8_irq_handler()
> - check HAS_PCH_SPLIT before calling the function instead of a
>   corresponding early return within the called function for
>   ibx_irq_reset(), ibx_irq_pre_postinstall(), ibx_irq_postinstall()
> v3: (jani)
> - in ironlake_irq_postinstall() and ironlake_irq_reset() HAS_PCH_SPLIT
>   is always true, so drop the check for it
>
> Reviewed-by: Satheeshakrishna M<satheeshakrishna.m@intel.com>
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> Signed-off-by: Shashank Sharma <ppashank.sharma@intel.com> (v1)
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/i915_irq.c | 12 ++++++++----
>  1 file changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index b06364f..b0cd7a9 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2297,7 +2297,8 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
>  			DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
>  	}
>  
> -	if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) {
> +	if (HAS_PCH_SPLIT(dev) && !HAS_PCH_NOP(dev) &&
> +	    master_ctl & GEN8_DE_PCH_IRQ) {
>  		/*
>  		 * FIXME(BDW): Assume for now that the new interrupt handling
>  		 * scheme also closed the SDE interrupt handling race we've seen
> @@ -3133,7 +3134,8 @@ static void gen8_irq_reset(struct drm_device *dev)
>  	GEN5_IRQ_RESET(GEN8_DE_MISC_);
>  	GEN5_IRQ_RESET(GEN8_PCU_);
>  
> -	ibx_irq_reset(dev);
> +	if (HAS_PCH_SPLIT(dev))
> +		ibx_irq_reset(dev);
>  }
>  
>  void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
> @@ -3545,12 +3547,14 @@ static int gen8_irq_postinstall(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  
> -	ibx_irq_pre_postinstall(dev);
> +	if (HAS_PCH_SPLIT(dev))
> +		ibx_irq_pre_postinstall(dev);
>  
>  	gen8_gt_irq_postinstall(dev_priv);
>  	gen8_de_irq_postinstall(dev_priv);
>  
> -	ibx_irq_postinstall(dev);
> +	if (HAS_PCH_SPLIT(dev))
> +		ibx_irq_postinstall(dev);
>  
>  	I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
>  	POSTING_READ(GEN8_MASTER_IRQ);
> -- 
> 1.9.1
>

-- 
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[PATCH v4 30/49] drm/i915/bxt: add display initialize/uninitialize sequence (CDCLK)

[Imre Deak]

From: Vandana Kannan <vandana.kannan@intel.com>

Add CDCLK specific display clock initialization sequence as per BSpec.

Note that the CDCLK initialization/uninitialization are done at their
current place only for simplicity, in a future patch - when more of the
runtime PM features will be enabled - these will be moved to power
well#1 and modeset encoder enabling/disabling hooks respectively. This
also means that atm dynamic power gating power well #1 is effectively
disabled.

The call to uninitialize CDCLK during system/runtime suspend will be
added later in this patchset.

v1: Added function definitions in header files
v2: Imre's review comments addressed
- Moved CDCLK related definitions to i915_reg.h
- Removed defintions for CDCLK frequency
- Split uninit_cdclk() by adding a phy_uninit function
- Calculate freq and decimal based on input frequency
- Program SSA precharge based on input frequency
- Use wait_for 1ms instead 200us udelay for DE PLL locking
- Removed initial value for divider, freq, decimal, ratio.
- Replaced polling loops with wait_for
- Parameterized latency optim setting
- Fix the parts where DE PLL has to be disabled.
- Call CDCLK selection from mode set

v3: (imre)
- add note about the plan to move the cdclk/phy init to a better place
- take rps.hw_lock around pcode access
- move DE PLL register macros here from another patch since they are
  used here first
- add BXT_ prefix to CDCLK flags
- add missing masking when programming CDCLK_FREQ_DECIMAL

v4: (ville)
- split the CDCLK/PHY parts into two patches, update commit message
  accordingly
- s/DISPLAY_PCU_CONTROL/HSW_PCODE_DE_WRITE_FREQ_REQ/
- simplify BXT_DE_PLL_RATIO macros
- fix BXT_DE_PLL_RATIO_MASK
- s/bxt_select_cdclk_freq/broxton_set_cdclk_freq/
- move cdclk init/uninit/set code from intel_ddi.c to intel_display.c
- remove redundant code comments for broxton_set_cdclk_freq()
- sanitize fixed point<->integer frequency value conversion
- use DRM_ERROR instead of WARN
- do RMW when programming BXT_DE_PLL_CTL for safety
- add note about PLL lock timeout being exactly 200us
- make PCU error messages more descriptive
- instead of using 0 freq to mean PLL off/bypass freq use 19200
  for clarity, as the latter one is the actual rate
- simplify pcode programming, removing duplicated
  sandybridge_pcode_write() call
- sanitize code flow, remove unnecessary scratch vars in
  broxton_set_cdclk() (imre)
- Remove bound check for maxmimum freq to match current code.
  This check will be added later at a more proper platform
  independent place once atomic support lands.
- add note to remove freq guard band which isn't needed on BXT
- add note to reduce freq to minimum if no pipe is enabled
- combine broxton_modeset_global_pipes() with
  valleyview_modeset_global_pipes()

Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> (v2)
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      |  20 ++++
 drivers/gpu/drm/i915/intel_ddi.c     |   2 +
 drivers/gpu/drm/i915/intel_display.c | 226 ++++++++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_drv.h     |   3 +
 4 files changed, 248 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4b53b20..c79bf8d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5452,6 +5452,9 @@ enum skl_disp_power_wells {
 #define  DISP_FBC_WM_DIS		(1<<15)
 #define DISP_ARB_CTL2	0x45004
 #define  DISP_DATA_PARTITION_5_6	(1<<6)
+#define DBUF_CTL	0x45008
+#define  DBUF_POWER_REQUEST		(1<<31)
+#define  DBUF_POWER_STATE		(1<<30)
 #define GEN7_MSG_CTL	0x45010
 #define  WAIT_FOR_PCH_RESET_ACK		(1<<1)
 #define  WAIT_FOR_PCH_FLR_ACK		(1<<0)
@@ -6403,6 +6406,7 @@ enum skl_disp_power_wells {
 #define   GEN6_PCODE_WRITE_D_COMP		0x11
 #define   GEN6_ENCODE_RC6_VID(mv)		(((mv) - 245) / 5)
 #define   GEN6_DECODE_RC6_VID(vids)		(((vids) * 5) + 245)
+#define   HSW_PCODE_DE_WRITE_FREQ_REQ		0x17
 #define   DISPLAY_IPS_CONTROL			0x19
 #define	  HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL	0x1A
 #define GEN6_PCODE_DATA				0x138128
@@ -6874,6 +6878,13 @@ enum skl_disp_power_wells {
 #define  CDCLK_FREQ_675_617		(3<<26)
 #define  CDCLK_FREQ_DECIMAL_MASK	(0x7ff)
 
+#define  BXT_CDCLK_CD2X_DIV_SEL_MASK	(3<<22)
+#define  BXT_CDCLK_CD2X_DIV_SEL_1	(0<<22)
+#define  BXT_CDCLK_CD2X_DIV_SEL_1_5	(1<<22)
+#define  BXT_CDCLK_CD2X_DIV_SEL_2	(2<<22)
+#define  BXT_CDCLK_CD2X_DIV_SEL_4	(3<<22)
+#define  BXT_CDCLK_SSA_PRECHARGE_ENABLE	(1<<16)
+
 /* LCPLL_CTL */
 #define LCPLL1_CTL		0x46010
 #define LCPLL2_CTL		0x46014
@@ -6938,6 +6949,15 @@ enum skl_disp_power_wells {
 #define GET_CFG_CR1_REG(id) (DPLL1_CFGCR1 + (id - SKL_DPLL1) * 8)
 #define GET_CFG_CR2_REG(id) (DPLL1_CFGCR2 + (id - SKL_DPLL1) * 8)
 
+/* BXT display engine PLL */
+#define BXT_DE_PLL_CTL			0x6d000
+#define   BXT_DE_PLL_RATIO(x)		(x)	/* {60,65,100} * 19.2MHz */
+#define   BXT_DE_PLL_RATIO_MASK		0xff
+
+#define BXT_DE_PLL_ENABLE		0x46070
+#define   BXT_DE_PLL_PLL_ENABLE		(1 << 31)
+#define   BXT_DE_PLL_LOCK		(1 << 30)
+
 /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
  * since on HSW we can't write to it using I915_WRITE. */
 #define D_COMP_HSW			(MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 5b50484..25d697b 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1880,6 +1880,8 @@ void intel_ddi_pll_init(struct drm_device *dev)
 	if (IS_SKYLAKE(dev)) {
 		if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
 			DRM_ERROR("LCPLL1 is disabled\n");
+	} else if (IS_BROXTON(dev)) {
+		broxton_init_cdclk(dev);
 	} else {
 		/*
 		 * The LCPLL register should be turned on by the BIOS. For now
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index bb5f2a5..5ee5d8c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5196,6 +5196,181 @@ static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
 	intel_display_set_init_power(dev_priv, false);
 }
 
+void broxton_set_cdclk(struct drm_device *dev, int frequency)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	uint32_t divider;
+	uint32_t ratio;
+	uint32_t current_freq;
+	int ret;
+
+	/* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
+	switch (frequency) {
+	case 144000:
+		divider = BXT_CDCLK_CD2X_DIV_SEL_4;
+		ratio = BXT_DE_PLL_RATIO(60);
+		break;
+	case 288000:
+		divider = BXT_CDCLK_CD2X_DIV_SEL_2;
+		ratio = BXT_DE_PLL_RATIO(60);
+		break;
+	case 384000:
+		divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
+		ratio = BXT_DE_PLL_RATIO(60);
+		break;
+	case 576000:
+		divider = BXT_CDCLK_CD2X_DIV_SEL_1;
+		ratio = BXT_DE_PLL_RATIO(60);
+		break;
+	case 624000:
+		divider = BXT_CDCLK_CD2X_DIV_SEL_1;
+		ratio = BXT_DE_PLL_RATIO(65);
+		break;
+	case 19200:
+		/*
+		 * Bypass frequency with DE PLL disabled. Init ratio, divider
+		 * to suppress GCC warning.
+		 */
+		ratio = 0;
+		divider = 0;
+		break;
+	default:
+		DRM_ERROR("unsupported CDCLK freq %d", frequency);
+
+		return;
+	}
+
+	mutex_lock(&dev_priv->rps.hw_lock);
+	/* Inform power controller of upcoming frequency change */
+	ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
+				      0x80000000);
+	mutex_unlock(&dev_priv->rps.hw_lock);
+
+	if (ret) {
+		DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
+			  ret, frequency);
+		return;
+	}
+
+	current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
+	/* convert from .1 fixpoint MHz with -1MHz offset to kHz */
+	current_freq = current_freq * 500 + 1000;
+
+	/*
+	 * DE PLL has to be disabled when
+	 * - setting to 19.2MHz (bypass, PLL isn't used)
+	 * - before setting to 624MHz (PLL needs toggling)
+	 * - before setting to any frequency from 624MHz (PLL needs toggling)
+	 */
+	if (frequency == 19200 || frequency == 624000 ||
+	    current_freq == 624000) {
+		I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
+		/* Timeout 200us */
+		if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
+			     1))
+			DRM_ERROR("timout waiting for DE PLL unlock\n");
+	}
+
+	if (frequency != 19200) {
+		uint32_t val;
+
+		val = I915_READ(BXT_DE_PLL_CTL);
+		val &= ~BXT_DE_PLL_RATIO_MASK;
+		val |= ratio;
+		I915_WRITE(BXT_DE_PLL_CTL, val);
+
+		I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
+		/* Timeout 200us */
+		if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
+			DRM_ERROR("timeout waiting for DE PLL lock\n");
+
+		val = I915_READ(CDCLK_CTL);
+		val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
+		val |= divider;
+		/*
+		 * Disable SSA Precharge when CD clock frequency < 500 MHz,
+		 * enable otherwise.
+		 */
+		val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
+		if (frequency >= 500000)
+			val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
+
+		val &= ~CDCLK_FREQ_DECIMAL_MASK;
+		/* convert from kHz to .1 fixpoint MHz with -1MHz offset */
+		val |= (frequency - 1000) / 500;
+		I915_WRITE(CDCLK_CTL, val);
+	}
+
+	mutex_lock(&dev_priv->rps.hw_lock);
+	ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
+				      DIV_ROUND_UP(frequency, 25000));
+	mutex_unlock(&dev_priv->rps.hw_lock);
+
+	if (ret) {
+		DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
+			  ret, frequency);
+		return;
+	}
+
+	dev_priv->cdclk_freq = frequency;
+}
+
+void broxton_init_cdclk(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	uint32_t val;
+
+	/*
+	 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
+	 * or else the reset will hang because there is no PCH to respond.
+	 * Move the handshake programming to initialization sequence.
+	 * Previously was left up to BIOS.
+	 */
+	val = I915_READ(HSW_NDE_RSTWRN_OPT);
+	val &= ~RESET_PCH_HANDSHAKE_ENABLE;
+	I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
+
+	/* Enable PG1 for cdclk */
+	intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
+
+	/* check if cd clock is enabled */
+	if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
+		DRM_DEBUG_KMS("Display already initialized\n");
+		return;
+	}
+
+	/*
+	 * FIXME:
+	 * - The initial CDCLK needs to be read from VBT.
+	 *   Need to make this change after VBT has changes for BXT.
+	 * - check if setting the max (or any) cdclk freq is really necessary
+	 *   here, it belongs to modeset time
+	 */
+	broxton_set_cdclk(dev, 624000);
+
+	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
+	udelay(10);
+
+	if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
+		DRM_ERROR("DBuf power enable timeout!\n");
+}
+
+void broxton_uninit_cdclk(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
+	udelay(10);
+
+	if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
+		DRM_ERROR("DBuf power disable timeout!\n");
+
+	/* Set minimum (bypass) frequency, in effect turning off the DE PLL */
+	broxton_set_cdclk(dev, 19200);
+
+	intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
+}
+
 /* returns HPLL frequency in kHz */
 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
 {
@@ -5363,6 +5538,26 @@ static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
 		return 200000;
 }
 
+static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
+			      int max_pixclk)
+{
+	/*
+	 * FIXME:
+	 * - remove the guardband, it's not needed on BXT
+	 * - set 19.2MHz bypass frequency if there are no active pipes
+	 */
+	if (max_pixclk > 576000*9/10)
+		return 624000;
+	else if (max_pixclk > 384000*9/10)
+		return 576000;
+	else if (max_pixclk > 288000*9/10)
+		return 384000;
+	else if (max_pixclk > 144000*9/10)
+		return 288000;
+	else
+		return 144000;
+}
+
 /* compute the max pixel clock for new configuration */
 static int intel_mode_max_pixclk(struct drm_atomic_state *state)
 {
@@ -5392,12 +5587,17 @@ static int valleyview_modeset_global_pipes(struct drm_atomic_state *state,
 	struct drm_i915_private *dev_priv = to_i915(state->dev);
 	struct intel_crtc *intel_crtc;
 	int max_pixclk = intel_mode_max_pixclk(state);
+	int cdclk;
 
 	if (max_pixclk < 0)
 		return max_pixclk;
 
-	if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
-	    dev_priv->cdclk_freq)
+	if (IS_VALLEYVIEW(dev_priv))
+		cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
+	else
+		cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
+
+	if (cdclk == dev_priv->cdclk_freq)
 		return 0;
 
 	/* disable/enable all currently active pipes while we change cdclk */
@@ -8827,6 +9027,23 @@ void hsw_disable_pc8(struct drm_i915_private *dev_priv)
 	intel_prepare_ddi(dev);
 }
 
+static void broxton_modeset_global_resources(struct drm_atomic_state *state)
+{
+	struct drm_device *dev = state->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	int max_pixclk = intel_mode_max_pixclk(state);
+	int req_cdclk;
+
+	/* see the comment in valleyview_modeset_global_resources */
+	if (WARN_ON(max_pixclk < 0))
+		return;
+
+	req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
+
+	if (req_cdclk != dev_priv->cdclk_freq)
+		broxton_set_cdclk(dev, req_cdclk);
+}
+
 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
 				      struct intel_crtc_state *crtc_state)
 {
@@ -11983,7 +12200,7 @@ static int __intel_set_mode(struct drm_crtc *crtc,
 	 * mode set on this crtc.  For other crtcs we need to use the
 	 * adjusted_mode bits in the crtc directly.
 	 */
-	if (IS_VALLEYVIEW(dev)) {
+	if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
 		ret = valleyview_modeset_global_pipes(state, &prepare_pipes);
 		if (ret)
 			goto done;
@@ -14005,6 +14222,9 @@ static void intel_init_display(struct drm_device *dev)
 	} else if (IS_VALLEYVIEW(dev)) {
 		dev_priv->display.modeset_global_resources =
 			valleyview_modeset_global_resources;
+	} else if (IS_BROXTON(dev)) {
+		dev_priv->display.modeset_global_resources =
+			broxton_modeset_global_resources;
 	}
 
 	switch (INTEL_INFO(dev)->gen) {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 6a2ee0c..5ba88eb 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1112,6 +1112,9 @@ void intel_prepare_reset(struct drm_device *dev);
 void intel_finish_reset(struct drm_device *dev);
 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
+void broxton_init_cdclk(struct drm_device *dev);
+void broxton_uninit_cdclk(struct drm_device *dev);
+void broxton_set_cdclk(struct drm_device *dev, int frequency);
 void intel_dp_get_m_n(struct intel_crtc *crtc,
 		      struct intel_crtc_state *pipe_config);
 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
-- 
2.1.0

_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 30.1/49] drm/i915/bxt: add display initialize/uninitialize sequence (PHY)

[Imre Deak]

From: Vandana Kannan <vandana.kannan@intel.com>

Add PHY specific display initialization sequence as per BSpec.

Note that the PHY initialization/uninitialization are done
at their current place only for simplicity, in a future patch - when more
of the runtime PM features will be enabled - these will be moved to
power well#1 and modeset encoder enabling/disabling hooks respectively.

The call to uninitialize the PHY during system/runtime suspend will be
added later in this patchset.

v1: Added function definitions in header files
v2: Imre's review comments addressed
- Moved CDCLK related definitions to i915_reg.h
- Removed defintions for CDCLK frequency
- Split uninit_cdclk() by adding a phy_uninit function
- Calculate freq and decimal based on input frequency
- Program SSA precharge based on input frequency
- Use wait_for 1ms instead 200us udelay for DE PLL locking
- Removed initial value for divider, freq, decimal, ratio.
- Replaced polling loops with wait_for
- Parameterized latency optim setting
- Fix the parts where DE PLL has to be disabled.
- Call CDCLK selection from mode set

v3: (imre)
- add note about the plan to move the cdclk/phy init to a better place
- take rps.hw_lock around pcode access
- fix DDI PHY timeout value
- squash in Vandana's "PORT_CL2CM_DW6_A BUN fix",
  "DDI PHY programming register defn", "Do ddi_phy_init always",
- move PHY register macros next to the corresponding CHV/VLV macros
- move DE PLL register macros here from another patch since they are
  used here first
- add BXT_ prefix to CDCLK flags
- s/COMMON_RESET/COMMON_RESET_DIS/ and clarify related code comments
- fix incorrect read value for the RMW of BXT_PHY_CTL_FAMILY_DDI
- fix using GT_DISPLAY_EDP_POWER_ON vs. GT_DISPLAY_DDI_POWER_ON
  when powering on DDI ports
- fix incorrect port when setting BXT_PORT_TX_DW14_LN for DDI ports
- add missing masking when programming CDCLK_FREQ_DECIMAL
- add missing powering on for DDI-C port, rename OCL2_LDOFUSE_PWR_EN
  to OCL2_LDOFUSE_PWR_DIS to reduce confusion
- add note about mismatch with bspec in the PORT_REF_DW6 fields
- factor out PHY init code to a new function, so we can call it for
  PHY1 and PHY0, instead of open-coding the same

v4: (ville)
- split the CDCLK/PHY parts into two patches, update commit message
  accordingly
- use the existing dpio_phy enum instead of adding a new one for the
  same purpose
- flip the meaning of PHYs so that PHY_A is PHY1 and PHY_BC is PHY0 to
  better match CHV
- s/BXT_PHY/_BXT_PHY/
- use _PIPE for _BXT_PHY instead of open-coding it
- drop _0_2_0_GTTMMADR suffix from BXT_P_CR_GT_DISP_PWRON
- define GT_DISPLAY_POWER_ON in a more standard way
- make a note that the CHV ConfigDB also disagrees about GRC_CODE field
  definitions
- fix lane optimization refactoring fumble from v3
- add per PHY uninit functions to match the init counterparts

Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> (v2)
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  |  96 ++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_ddi.c | 125 +++++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_drv.h |   2 +
 3 files changed, 223 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c79bf8d..1903e37 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1117,6 +1117,102 @@ enum skl_disp_power_wells {
 #define   DPIO_FRC_LATENCY_SHFIT	8
 #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
 #define   DPIO_UPAR_SHIFT		30
+
+/* BXT PHY registers */
+#define _BXT_PHY(phy, a, b)		_PIPE((phy), (a), (b))
+
+#define BXT_P_CR_GT_DISP_PWRON		0x138090
+#define   GT_DISPLAY_POWER_ON(phy)	(1 << (phy))
+
+#define _PHY_CTL_FAMILY_EDP		0x64C80
+#define _PHY_CTL_FAMILY_DDI		0x64C90
+#define   COMMON_RESET_DIS		(1 << 31)
+#define BXT_PHY_CTL_FAMILY(phy)		_BXT_PHY((phy), _PHY_CTL_FAMILY_DDI, \
+							_PHY_CTL_FAMILY_EDP)
+
+/* BXT PHY common lane registers */
+#define _PORT_CL1CM_DW0_A		0x162000
+#define _PORT_CL1CM_DW0_BC		0x6C000
+#define   PHY_POWER_GOOD		(1 << 16)
+#define BXT_PORT_CL1CM_DW0(phy)		_BXT_PHY((phy), _PORT_CL1CM_DW0_BC, \
+							_PORT_CL1CM_DW0_A)
+
+#define _PORT_CL1CM_DW9_A		0x162024
+#define _PORT_CL1CM_DW9_BC		0x6C024
+#define   IREF0RC_OFFSET_SHIFT		8
+#define   IREF0RC_OFFSET_MASK		(0xFF << IREF0RC_OFFSET_SHIFT)
+#define BXT_PORT_CL1CM_DW9(phy)		_BXT_PHY((phy), _PORT_CL1CM_DW9_BC, \
+							_PORT_CL1CM_DW9_A)
+
+#define _PORT_CL1CM_DW10_A		0x162028
+#define _PORT_CL1CM_DW10_BC		0x6C028
+#define   IREF1RC_OFFSET_SHIFT		8
+#define   IREF1RC_OFFSET_MASK		(0xFF << IREF1RC_OFFSET_SHIFT)
+#define BXT_PORT_CL1CM_DW10(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW10_BC, \
+							_PORT_CL1CM_DW10_A)
+
+#define _PORT_CL1CM_DW28_A		0x162070
+#define _PORT_CL1CM_DW28_BC		0x6C070
+#define   OCL1_POWER_DOWN_EN		(1 << 23)
+#define   DW28_OLDO_DYN_PWR_DOWN_EN	(1 << 22)
+#define   SUS_CLK_CONFIG		0x3
+#define BXT_PORT_CL1CM_DW28(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW28_BC, \
+							_PORT_CL1CM_DW28_A)
+
+#define _PORT_CL1CM_DW30_A		0x162078
+#define _PORT_CL1CM_DW30_BC		0x6C078
+#define   OCL2_LDOFUSE_PWR_DIS		(1 << 6)
+#define BXT_PORT_CL1CM_DW30(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW30_BC, \
+							_PORT_CL1CM_DW30_A)
+
+/* Defined for PHY0 only */
+#define BXT_PORT_CL2CM_DW6_BC		0x6C358
+#define   DW6_OLDO_DYN_PWR_DOWN_EN	(1 << 28)
+
+/* BXT PHY Ref registers */
+#define _PORT_REF_DW3_A			0x16218C
+#define _PORT_REF_DW3_BC		0x6C18C
+#define   GRC_DONE			(1 << 22)
+#define BXT_PORT_REF_DW3(phy)		_BXT_PHY((phy), _PORT_REF_DW3_BC, \
+							_PORT_REF_DW3_A)
+
+#define _PORT_REF_DW6_A			0x162198
+#define _PORT_REF_DW6_BC		0x6C198
+/*
+ * FIXME: BSpec/CHV ConfigDB disagrees on the following two fields, fix them
+ * after testing.
+ */
+#define   GRC_CODE_SHIFT		23
+#define   GRC_CODE_MASK			(0x1FF << GRC_CODE_SHIFT)
+#define   GRC_CODE_FAST_SHIFT		16
+#define   GRC_CODE_FAST_MASK		(0x7F << GRC_CODE_FAST_SHIFT)
+#define   GRC_CODE_SLOW_SHIFT		8
+#define   GRC_CODE_SLOW_MASK		(0xFF << GRC_CODE_SLOW_SHIFT)
+#define   GRC_CODE_NOM_MASK		0xFF
+#define BXT_PORT_REF_DW6(phy)		_BXT_PHY((phy), _PORT_REF_DW6_BC,	\
+						      _PORT_REF_DW6_A)
+
+#define _PORT_REF_DW8_A			0x1621A0
+#define _PORT_REF_DW8_BC		0x6C1A0
+#define   GRC_DIS			(1 << 15)
+#define   GRC_RDY_OVRD			(1 << 1)
+#define BXT_PORT_REF_DW8(phy)		_BXT_PHY((phy), _PORT_REF_DW8_BC,	\
+						      _PORT_REF_DW8_A)
+
+/* BXT PHY TX registers */
+#define _BXT_LANE_OFFSET(lane)           (((lane) >> 1) * 0x200 +	\
+					  ((lane) & 1) * 0x80)
+
+#define _PORT_TX_DW14_LN0_A		0x162538
+#define _PORT_TX_DW14_LN0_B		0x6C538
+#define _PORT_TX_DW14_LN0_C		0x6C938
+#define   LATENCY_OPTIM_SHIFT		30
+#define   LATENCY_OPTIM			(1 << LATENCY_OPTIM_SHIFT)
+#define BXT_PORT_TX_DW14_LN(port, lane)	(_PORT3((port), _PORT_TX_DW14_LN0_A,   \
+							_PORT_TX_DW14_LN0_B,   \
+							_PORT_TX_DW14_LN0_C) + \
+					 _BXT_LANE_OFFSET(lane))
+
 /*
  * Fence registers
  */
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 25d697b..31cadb8 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1864,6 +1864,130 @@ static void skl_shared_dplls_init(struct drm_i915_private *dev_priv)
 	}
 }
 
+static void broxton_phy_init(struct drm_i915_private *dev_priv,
+			     enum dpio_phy phy)
+{
+	enum port port;
+	uint32_t val;
+
+	val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
+	val |= GT_DISPLAY_POWER_ON(phy);
+	I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
+
+	/* Considering 10ms timeout until BSpec is updated */
+	if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10))
+		DRM_ERROR("timeout during PHY%d power on\n", phy);
+
+	for (port =  (phy == DPIO_PHY0 ? PORT_B : PORT_A);
+	     port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) {
+		int lane;
+
+		for (lane = 0; lane < 4; lane++) {
+			val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
+			/*
+			 * Note that on CHV this flag is called UPAR, but has
+			 * the same function.
+			 */
+			val &= ~LATENCY_OPTIM;
+			if (lane != 1)
+				val |= LATENCY_OPTIM;
+
+			I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val);
+		}
+	}
+
+	/* Program PLL Rcomp code offset */
+	val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
+	val &= ~IREF0RC_OFFSET_MASK;
+	val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
+	I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
+
+	val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
+	val &= ~IREF1RC_OFFSET_MASK;
+	val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
+	I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
+
+	/* Program power gating */
+	val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
+	val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
+		SUS_CLK_CONFIG;
+	I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
+
+	if (phy == DPIO_PHY0) {
+		val = I915_READ(BXT_PORT_CL2CM_DW6_BC);
+		val |= DW6_OLDO_DYN_PWR_DOWN_EN;
+		I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val);
+	}
+
+	val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
+	val &= ~OCL2_LDOFUSE_PWR_DIS;
+	/*
+	 * On PHY1 disable power on the second channel, since no port is
+	 * connected there. On PHY0 both channels have a port, so leave it
+	 * enabled.
+	 * TODO: port C is only connected on BXT-P, so on BXT0/1 we should
+	 * power down the second channel on PHY0 as well.
+	 */
+	if (phy == DPIO_PHY1)
+		val |= OCL2_LDOFUSE_PWR_DIS;
+	I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
+
+	if (phy == DPIO_PHY0) {
+		uint32_t grc_code;
+		/*
+		 * PHY0 isn't connected to an RCOMP resistor so copy over
+		 * the corresponding calibrated value from PHY1, and disable
+		 * the automatic calibration on PHY0.
+		 */
+		if (wait_for(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE,
+			     10))
+			DRM_ERROR("timeout waiting for PHY1 GRC\n");
+
+		val = I915_READ(BXT_PORT_REF_DW6(DPIO_PHY1));
+		val = (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
+		grc_code = val << GRC_CODE_FAST_SHIFT |
+			   val << GRC_CODE_SLOW_SHIFT |
+			   val;
+		I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code);
+
+		val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0));
+		val |= GRC_DIS | GRC_RDY_OVRD;
+		I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val);
+	}
+
+	val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
+	val |= COMMON_RESET_DIS;
+	I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
+}
+
+void broxton_ddi_phy_init(struct drm_device *dev)
+{
+	/* Enable PHY1 first since it provides Rcomp for PHY0 */
+	broxton_phy_init(dev->dev_private, DPIO_PHY1);
+	broxton_phy_init(dev->dev_private, DPIO_PHY0);
+}
+
+static void broxton_phy_uninit(struct drm_i915_private *dev_priv,
+			       enum dpio_phy phy)
+{
+	uint32_t val;
+
+	val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
+	val &= ~COMMON_RESET_DIS;
+	I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
+}
+
+void broxton_ddi_phy_uninit(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	broxton_phy_uninit(dev_priv, DPIO_PHY1);
+	broxton_phy_uninit(dev_priv, DPIO_PHY0);
+
+	/* FIXME: do this in broxton_phy_uninit per phy */
+	I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 0);
+}
+
 void intel_ddi_pll_init(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -1882,6 +2006,7 @@ void intel_ddi_pll_init(struct drm_device *dev)
 			DRM_ERROR("LCPLL1 is disabled\n");
 	} else if (IS_BROXTON(dev)) {
 		broxton_init_cdclk(dev);
+		broxton_ddi_phy_init(dev);
 	} else {
 		/*
 		 * The LCPLL register should be turned on by the BIOS. For now
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 5ba88eb..5266985 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1115,6 +1115,8 @@ void hsw_disable_pc8(struct drm_i915_private *dev_priv);
 void broxton_init_cdclk(struct drm_device *dev);
 void broxton_uninit_cdclk(struct drm_device *dev);
 void broxton_set_cdclk(struct drm_device *dev, int frequency);
+void broxton_ddi_phy_init(struct drm_device *dev);
+void broxton_ddi_phy_uninit(struct drm_device *dev);
 void intel_dp_get_m_n(struct intel_crtc *crtc,
 		      struct intel_crtc_state *pipe_config);
 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
-- 
2.1.0

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[PATCH v2 31/49] drm/i915/bxt: add description about the BXT PHYs

[Imre Deak]

Extend the VLV/CHV DPIO (PHY) documentation with the BXT specifics.

v2:
- add more detail about the mapping between ports and transcoders (ville)

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 Documentation/DocBook/drm.tmpl  |  4 ++--
 drivers/gpu/drm/i915/i915_reg.h | 18 ++++++++++++------
 2 files changed, 14 insertions(+), 8 deletions(-)

diff --git a/Documentation/DocBook/drm.tmpl b/Documentation/DocBook/drm.tmpl
index f4976cd..a8509c2 100644
--- a/Documentation/DocBook/drm.tmpl
+++ b/Documentation/DocBook/drm.tmpl
@@ -4067,7 +4067,7 @@ int num_ioctls;</synopsis>
         <title>DPIO</title>
 !Pdrivers/gpu/drm/i915/i915_reg.h DPIO
 	<table id="dpiox2">
-	  <title>Dual channel PHY (VLV/CHV)</title>
+	  <title>Dual channel PHY (VLV/CHV/BXT)</title>
 	  <tgroup cols="8">
 	    <colspec colname="c0" />
 	    <colspec colname="c1" />
@@ -4118,7 +4118,7 @@ int num_ioctls;</synopsis>
 	  </tgroup>
 	</table>
 	<table id="dpiox1">
-	  <title>Single channel PHY (CHV)</title>
+	  <title>Single channel PHY (CHV/BXT)</title>
 	  <tgroup cols="4">
 	    <colspec colname="c0" />
 	    <colspec colname="c1" />
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1903e37..abea462 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -715,7 +715,7 @@ enum skl_disp_power_wells {
 /**
  * DOC: DPIO
  *
- * VLV and CHV have slightly peculiar display PHYs for driving DP/HDMI
+ * VLV, CHV and BXT have slightly peculiar display PHYs for driving DP/HDMI
  * ports. DPIO is the name given to such a display PHY. These PHYs
  * don't follow the standard programming model using direct MMIO
  * registers, and instead their registers must be accessed trough IOSF
@@ -746,7 +746,7 @@ enum skl_disp_power_wells {
  * controlled from the display controller side. No DPIO registers
  * need to be accessed during AUX communication,
  *
- * Generally the common lane corresponds to the pipe and
+ * Generally on VLV/CHV the common lane corresponds to the pipe and
  * the spline (PCS/TX) corresponds to the port.
  *
  * For dual channel PHY (VLV/CHV):
@@ -768,11 +768,17 @@ enum skl_disp_power_wells {
  *
  *  port D == PCS/TX CH0
  *
- * Note: digital port B is DDI0, digital port C is DDI1,
- * digital port D is DDI2
+ * On BXT the entire PHY channel corresponds to the port. That means
+ * the PLL is also now associated with the port rather than the pipe,
+ * and so the clock needs to be routed to the appropriate transcoder.
+ * Port A PLL is directly connected to transcoder EDP and port B/C
+ * PLLs can be routed to any transcoder A/B/C.
+ *
+ * Note: DDI0 is digital port B, DD1 is digital port C, and DDI2 is
+ * digital port D (CHV) or port A (BXT).
  */
 /*
- * Dual channel PHY (VLV/CHV)
+ * Dual channel PHY (VLV/CHV/BXT)
  * ---------------------------------
  * |      CH0      |      CH1      |
  * |  CMN/PLL/REF  |  CMN/PLL/REF  |
@@ -784,7 +790,7 @@ enum skl_disp_power_wells {
  * |     DDI0      |     DDI1      | DP/HDMI ports
  * ---------------------------------
  *
- * Single channel PHY (CHV)
+ * Single channel PHY (CHV/BXT)
  * -----------------
  * |      CH0      |
  * |  CMN/PLL/REF  |
-- 
2.1.0

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Re: [PATCH v2 31/49] drm/i915/bxt: add description about the BXT PHYs

[Ville Syrjälä]

On Wed, Apr 15, 2015 at 04:42:58PM +0300, Imre Deak wrote:
> Extend the VLV/CHV DPIO (PHY) documentation with the BXT specifics.
> 
> v2:
> - add more detail about the mapping between ports and transcoders (ville)
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  Documentation/DocBook/drm.tmpl  |  4 ++--
>  drivers/gpu/drm/i915/i915_reg.h | 18 ++++++++++++------
>  2 files changed, 14 insertions(+), 8 deletions(-)
> 
> diff --git a/Documentation/DocBook/drm.tmpl b/Documentation/DocBook/drm.tmpl
> index f4976cd..a8509c2 100644
> --- a/Documentation/DocBook/drm.tmpl
> +++ b/Documentation/DocBook/drm.tmpl
> @@ -4067,7 +4067,7 @@ int num_ioctls;</synopsis>
>          <title>DPIO</title>
>  !Pdrivers/gpu/drm/i915/i915_reg.h DPIO
>  	<table id="dpiox2">
> -	  <title>Dual channel PHY (VLV/CHV)</title>
> +	  <title>Dual channel PHY (VLV/CHV/BXT)</title>
>  	  <tgroup cols="8">
>  	    <colspec colname="c0" />
>  	    <colspec colname="c1" />
> @@ -4118,7 +4118,7 @@ int num_ioctls;</synopsis>
>  	  </tgroup>
>  	</table>
>  	<table id="dpiox1">
> -	  <title>Single channel PHY (CHV)</title>
> +	  <title>Single channel PHY (CHV/BXT)</title>
>  	  <tgroup cols="4">
>  	    <colspec colname="c0" />
>  	    <colspec colname="c1" />
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 1903e37..abea462 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -715,7 +715,7 @@ enum skl_disp_power_wells {
>  /**
>   * DOC: DPIO
>   *
> - * VLV and CHV have slightly peculiar display PHYs for driving DP/HDMI
> + * VLV, CHV and BXT have slightly peculiar display PHYs for driving DP/HDMI
>   * ports. DPIO is the name given to such a display PHY. These PHYs
>   * don't follow the standard programming model using direct MMIO
>   * registers, and instead their registers must be accessed trough IOSF
> @@ -746,7 +746,7 @@ enum skl_disp_power_wells {
>   * controlled from the display controller side. No DPIO registers
>   * need to be accessed during AUX communication,
>   *
> - * Generally the common lane corresponds to the pipe and
> + * Generally on VLV/CHV the common lane corresponds to the pipe and
>   * the spline (PCS/TX) corresponds to the port.
>   *
>   * For dual channel PHY (VLV/CHV):
> @@ -768,11 +768,17 @@ enum skl_disp_power_wells {
>   *
>   *  port D == PCS/TX CH0
>   *
> - * Note: digital port B is DDI0, digital port C is DDI1,
> - * digital port D is DDI2
> + * On BXT the entire PHY channel corresponds to the port. That means
> + * the PLL is also now associated with the port rather than the pipe,
> + * and so the clock needs to be routed to the appropriate transcoder.
> + * Port A PLL is directly connected to transcoder EDP and port B/C
> + * PLLs can be routed to any transcoder A/B/C.
> + *
> + * Note: DDI0 is digital port B, DD1 is digital port C, and DDI2 is
> + * digital port D (CHV) or port A (BXT).
>   */
>  /*
> - * Dual channel PHY (VLV/CHV)
> + * Dual channel PHY (VLV/CHV/BXT)
>   * ---------------------------------
>   * |      CH0      |      CH1      |
>   * |  CMN/PLL/REF  |  CMN/PLL/REF  |
> @@ -784,7 +790,7 @@ enum skl_disp_power_wells {
>   * |     DDI0      |     DDI1      | DP/HDMI ports
>   * ---------------------------------
>   *
> - * Single channel PHY (CHV)
> + * Single channel PHY (CHV/BXT)
>   * -----------------
>   * |      CH0      |
>   * |  CMN/PLL/REF  |
> -- 
> 2.1.0

-- 
Ville Syrjälä
Intel OTC
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[PATCH v4 33/49] drm/i915/bxt: Add DC9 Trigger sequence

[Imre Deak]

From: Suketu Shah <suketu.j.shah@intel.com>

Add triggers for DC9 as per details provided in bxt_enable_dc9
and bxt_disable_dc9 implementations.

v1:
- Add SKL check in gen9_disable_dc5 as it is possible for DC5
  to remain disabled only for SKL.
- Add additional checks for whether DC5 is already disabled during
  DC5-disabling only for BXT.

v2:
- rebase to latest.
- Load CSR during DC9 disabling in the beginning before DC9 is
  disabled.
- Make gen9_disable_dc5 function non-static as it's being called by
  functions in i915_drv.c.
- Enable DC9-related functionality using a macro.

v3: (imre)
- remove BXT_ENABLE_DC9, we want DC9 always, and it's only valid on BXT
- remove DC5 disabling and CSR FW loaded check, these are nop atm
- squash in Vandana's "Do ddi_phy_init always" patch

v4:
- add TODO to re-enable DC5 during resume if CSR FW is available (sagar)

Signed-off-by: Suketu Shah <suketu.j.shah@intel.com>
Signed-off-by: A.Sunil Kamath <sunil.kamath@intel.com> (v2)
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Sagar Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c | 39 ++++++++++++++++++++++++++++++++++++++-
 1 file changed, 38 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index c3fdbb0..f9754c3 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1009,6 +1009,38 @@ static int hsw_suspend_complete(struct drm_i915_private *dev_priv)
 	return 0;
 }
 
+static int bxt_suspend_complete(struct drm_i915_private *dev_priv)
+{
+	struct drm_device *dev = dev_priv->dev;
+
+	/* TODO: when DC5 support is added disable DC5 here. */
+
+	broxton_ddi_phy_uninit(dev);
+	broxton_uninit_cdclk(dev);
+	bxt_enable_dc9(dev_priv);
+
+	return 0;
+}
+
+static int bxt_resume_prepare(struct drm_i915_private *dev_priv)
+{
+	struct drm_device *dev = dev_priv->dev;
+
+	/* TODO: when CSR FW support is added make sure the FW is loaded */
+
+	bxt_disable_dc9(dev_priv);
+
+	/*
+	 * TODO: when DC5 support is added enable DC5 here if the CSR FW
+	 * is available.
+	 */
+	broxton_init_cdclk(dev);
+	broxton_ddi_phy_init(dev);
+	intel_prepare_ddi(dev);
+
+	return 0;
+}
+
 /*
  * Save all Gunit registers that may be lost after a D3 and a subsequent
  * S0i[R123] transition. The list of registers needing a save/restore is
@@ -1467,6 +1499,9 @@ static int intel_runtime_resume(struct device *device)
 
 	if (IS_GEN6(dev_priv))
 		intel_init_pch_refclk(dev);
+
+	if (IS_BROXTON(dev))
+		ret = bxt_resume_prepare(dev_priv);
 	else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 		hsw_disable_pc8(dev_priv);
 	else if (IS_VALLEYVIEW(dev_priv))
@@ -1499,7 +1534,9 @@ static int intel_suspend_complete(struct drm_i915_private *dev_priv)
 	struct drm_device *dev = dev_priv->dev;
 	int ret;
 
-	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
+	if (IS_BROXTON(dev))
+		ret = bxt_suspend_complete(dev_priv);
+	else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 		ret = hsw_suspend_complete(dev_priv);
 	else if (IS_VALLEYVIEW(dev))
 		ret = vlv_suspend_complete(dev_priv);
-- 
2.1.0

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Re: [PATCH v4 30/49] drm/i915/bxt: add display initialize/uninitialize sequence (CDCLK)

[Ville Syrjälä]

On Wed, Apr 15, 2015 at 04:42:56PM +0300, Imre Deak wrote:
> From: Vandana Kannan <vandana.kannan@intel.com>
> 
> Add CDCLK specific display clock initialization sequence as per BSpec.
> 
> Note that the CDCLK initialization/uninitialization are done at their
> current place only for simplicity, in a future patch - when more of the
> runtime PM features will be enabled - these will be moved to power
> well#1 and modeset encoder enabling/disabling hooks respectively. This
> also means that atm dynamic power gating power well #1 is effectively
> disabled.
> 
> The call to uninitialize CDCLK during system/runtime suspend will be
> added later in this patchset.
> 
> v1: Added function definitions in header files
> v2: Imre's review comments addressed
> - Moved CDCLK related definitions to i915_reg.h
> - Removed defintions for CDCLK frequency
> - Split uninit_cdclk() by adding a phy_uninit function
> - Calculate freq and decimal based on input frequency
> - Program SSA precharge based on input frequency
> - Use wait_for 1ms instead 200us udelay for DE PLL locking
> - Removed initial value for divider, freq, decimal, ratio.
> - Replaced polling loops with wait_for
> - Parameterized latency optim setting
> - Fix the parts where DE PLL has to be disabled.
> - Call CDCLK selection from mode set
> 
> v3: (imre)
> - add note about the plan to move the cdclk/phy init to a better place
> - take rps.hw_lock around pcode access
> - move DE PLL register macros here from another patch since they are
>   used here first
> - add BXT_ prefix to CDCLK flags
> - add missing masking when programming CDCLK_FREQ_DECIMAL
> 
> v4: (ville)
> - split the CDCLK/PHY parts into two patches, update commit message
>   accordingly
> - s/DISPLAY_PCU_CONTROL/HSW_PCODE_DE_WRITE_FREQ_REQ/
> - simplify BXT_DE_PLL_RATIO macros
> - fix BXT_DE_PLL_RATIO_MASK
> - s/bxt_select_cdclk_freq/broxton_set_cdclk_freq/
> - move cdclk init/uninit/set code from intel_ddi.c to intel_display.c
> - remove redundant code comments for broxton_set_cdclk_freq()
> - sanitize fixed point<->integer frequency value conversion
> - use DRM_ERROR instead of WARN
> - do RMW when programming BXT_DE_PLL_CTL for safety
> - add note about PLL lock timeout being exactly 200us
> - make PCU error messages more descriptive
> - instead of using 0 freq to mean PLL off/bypass freq use 19200
>   for clarity, as the latter one is the actual rate
> - simplify pcode programming, removing duplicated
>   sandybridge_pcode_write() call
> - sanitize code flow, remove unnecessary scratch vars in
>   broxton_set_cdclk() (imre)
> - Remove bound check for maxmimum freq to match current code.
>   This check will be added later at a more proper platform
>   independent place once atomic support lands.
> - add note to remove freq guard band which isn't needed on BXT
> - add note to reduce freq to minimum if no pipe is enabled
> - combine broxton_modeset_global_pipes() with
>   valleyview_modeset_global_pipes()
> 
> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> (v2)
> Signed-off-by: Imre Deak <imre.deak@intel.com>

That's quite a changelog I caused. Sorry :)

But I like how it's looking now. A few minor FIXMEs in there, but I
agree that those can be dealt with later.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h      |  20 ++++
>  drivers/gpu/drm/i915/intel_ddi.c     |   2 +
>  drivers/gpu/drm/i915/intel_display.c | 226 ++++++++++++++++++++++++++++++++++-
>  drivers/gpu/drm/i915/intel_drv.h     |   3 +
>  4 files changed, 248 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 4b53b20..c79bf8d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5452,6 +5452,9 @@ enum skl_disp_power_wells {
>  #define  DISP_FBC_WM_DIS		(1<<15)
>  #define DISP_ARB_CTL2	0x45004
>  #define  DISP_DATA_PARTITION_5_6	(1<<6)
> +#define DBUF_CTL	0x45008
> +#define  DBUF_POWER_REQUEST		(1<<31)
> +#define  DBUF_POWER_STATE		(1<<30)
>  #define GEN7_MSG_CTL	0x45010
>  #define  WAIT_FOR_PCH_RESET_ACK		(1<<1)
>  #define  WAIT_FOR_PCH_FLR_ACK		(1<<0)
> @@ -6403,6 +6406,7 @@ enum skl_disp_power_wells {
>  #define   GEN6_PCODE_WRITE_D_COMP		0x11
>  #define   GEN6_ENCODE_RC6_VID(mv)		(((mv) - 245) / 5)
>  #define   GEN6_DECODE_RC6_VID(vids)		(((vids) * 5) + 245)
> +#define   HSW_PCODE_DE_WRITE_FREQ_REQ		0x17
>  #define   DISPLAY_IPS_CONTROL			0x19
>  #define	  HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL	0x1A
>  #define GEN6_PCODE_DATA				0x138128
> @@ -6874,6 +6878,13 @@ enum skl_disp_power_wells {
>  #define  CDCLK_FREQ_675_617		(3<<26)
>  #define  CDCLK_FREQ_DECIMAL_MASK	(0x7ff)
>  
> +#define  BXT_CDCLK_CD2X_DIV_SEL_MASK	(3<<22)
> +#define  BXT_CDCLK_CD2X_DIV_SEL_1	(0<<22)
> +#define  BXT_CDCLK_CD2X_DIV_SEL_1_5	(1<<22)
> +#define  BXT_CDCLK_CD2X_DIV_SEL_2	(2<<22)
> +#define  BXT_CDCLK_CD2X_DIV_SEL_4	(3<<22)
> +#define  BXT_CDCLK_SSA_PRECHARGE_ENABLE	(1<<16)
> +
>  /* LCPLL_CTL */
>  #define LCPLL1_CTL		0x46010
>  #define LCPLL2_CTL		0x46014
> @@ -6938,6 +6949,15 @@ enum skl_disp_power_wells {
>  #define GET_CFG_CR1_REG(id) (DPLL1_CFGCR1 + (id - SKL_DPLL1) * 8)
>  #define GET_CFG_CR2_REG(id) (DPLL1_CFGCR2 + (id - SKL_DPLL1) * 8)
>  
> +/* BXT display engine PLL */
> +#define BXT_DE_PLL_CTL			0x6d000
> +#define   BXT_DE_PLL_RATIO(x)		(x)	/* {60,65,100} * 19.2MHz */
> +#define   BXT_DE_PLL_RATIO_MASK		0xff
> +
> +#define BXT_DE_PLL_ENABLE		0x46070
> +#define   BXT_DE_PLL_PLL_ENABLE		(1 << 31)
> +#define   BXT_DE_PLL_LOCK		(1 << 30)
> +
>  /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
>   * since on HSW we can't write to it using I915_WRITE. */
>  #define D_COMP_HSW			(MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 5b50484..25d697b 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1880,6 +1880,8 @@ void intel_ddi_pll_init(struct drm_device *dev)
>  	if (IS_SKYLAKE(dev)) {
>  		if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
>  			DRM_ERROR("LCPLL1 is disabled\n");
> +	} else if (IS_BROXTON(dev)) {
> +		broxton_init_cdclk(dev);
>  	} else {
>  		/*
>  		 * The LCPLL register should be turned on by the BIOS. For now
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index bb5f2a5..5ee5d8c 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5196,6 +5196,181 @@ static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
>  	intel_display_set_init_power(dev_priv, false);
>  }
>  
> +void broxton_set_cdclk(struct drm_device *dev, int frequency)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	uint32_t divider;
> +	uint32_t ratio;
> +	uint32_t current_freq;
> +	int ret;
> +
> +	/* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
> +	switch (frequency) {
> +	case 144000:
> +		divider = BXT_CDCLK_CD2X_DIV_SEL_4;
> +		ratio = BXT_DE_PLL_RATIO(60);
> +		break;
> +	case 288000:
> +		divider = BXT_CDCLK_CD2X_DIV_SEL_2;
> +		ratio = BXT_DE_PLL_RATIO(60);
> +		break;
> +	case 384000:
> +		divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
> +		ratio = BXT_DE_PLL_RATIO(60);
> +		break;
> +	case 576000:
> +		divider = BXT_CDCLK_CD2X_DIV_SEL_1;
> +		ratio = BXT_DE_PLL_RATIO(60);
> +		break;
> +	case 624000:
> +		divider = BXT_CDCLK_CD2X_DIV_SEL_1;
> +		ratio = BXT_DE_PLL_RATIO(65);
> +		break;
> +	case 19200:
> +		/*
> +		 * Bypass frequency with DE PLL disabled. Init ratio, divider
> +		 * to suppress GCC warning.
> +		 */
> +		ratio = 0;
> +		divider = 0;
> +		break;
> +	default:
> +		DRM_ERROR("unsupported CDCLK freq %d", frequency);
> +
> +		return;
> +	}
> +
> +	mutex_lock(&dev_priv->rps.hw_lock);
> +	/* Inform power controller of upcoming frequency change */
> +	ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
> +				      0x80000000);
> +	mutex_unlock(&dev_priv->rps.hw_lock);
> +
> +	if (ret) {
> +		DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
> +			  ret, frequency);
> +		return;
> +	}
> +
> +	current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
> +	/* convert from .1 fixpoint MHz with -1MHz offset to kHz */
> +	current_freq = current_freq * 500 + 1000;
> +
> +	/*
> +	 * DE PLL has to be disabled when
> +	 * - setting to 19.2MHz (bypass, PLL isn't used)
> +	 * - before setting to 624MHz (PLL needs toggling)
> +	 * - before setting to any frequency from 624MHz (PLL needs toggling)
> +	 */
> +	if (frequency == 19200 || frequency == 624000 ||
> +	    current_freq == 624000) {
> +		I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
> +		/* Timeout 200us */
> +		if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
> +			     1))
> +			DRM_ERROR("timout waiting for DE PLL unlock\n");
> +	}
> +
> +	if (frequency != 19200) {
> +		uint32_t val;
> +
> +		val = I915_READ(BXT_DE_PLL_CTL);
> +		val &= ~BXT_DE_PLL_RATIO_MASK;
> +		val |= ratio;
> +		I915_WRITE(BXT_DE_PLL_CTL, val);
> +
> +		I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
> +		/* Timeout 200us */
> +		if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
> +			DRM_ERROR("timeout waiting for DE PLL lock\n");
> +
> +		val = I915_READ(CDCLK_CTL);
> +		val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
> +		val |= divider;
> +		/*
> +		 * Disable SSA Precharge when CD clock frequency < 500 MHz,
> +		 * enable otherwise.
> +		 */
> +		val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
> +		if (frequency >= 500000)
> +			val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
> +
> +		val &= ~CDCLK_FREQ_DECIMAL_MASK;
> +		/* convert from kHz to .1 fixpoint MHz with -1MHz offset */
> +		val |= (frequency - 1000) / 500;
> +		I915_WRITE(CDCLK_CTL, val);
> +	}
> +
> +	mutex_lock(&dev_priv->rps.hw_lock);
> +	ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
> +				      DIV_ROUND_UP(frequency, 25000));
> +	mutex_unlock(&dev_priv->rps.hw_lock);
> +
> +	if (ret) {
> +		DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
> +			  ret, frequency);
> +		return;
> +	}
> +
> +	dev_priv->cdclk_freq = frequency;
> +}
> +
> +void broxton_init_cdclk(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	uint32_t val;
> +
> +	/*
> +	 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
> +	 * or else the reset will hang because there is no PCH to respond.
> +	 * Move the handshake programming to initialization sequence.
> +	 * Previously was left up to BIOS.
> +	 */
> +	val = I915_READ(HSW_NDE_RSTWRN_OPT);
> +	val &= ~RESET_PCH_HANDSHAKE_ENABLE;
> +	I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
> +
> +	/* Enable PG1 for cdclk */
> +	intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
> +
> +	/* check if cd clock is enabled */
> +	if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
> +		DRM_DEBUG_KMS("Display already initialized\n");
> +		return;
> +	}
> +
> +	/*
> +	 * FIXME:
> +	 * - The initial CDCLK needs to be read from VBT.
> +	 *   Need to make this change after VBT has changes for BXT.
> +	 * - check if setting the max (or any) cdclk freq is really necessary
> +	 *   here, it belongs to modeset time
> +	 */
> +	broxton_set_cdclk(dev, 624000);
> +
> +	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
> +	udelay(10);
> +
> +	if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
> +		DRM_ERROR("DBuf power enable timeout!\n");
> +}
> +
> +void broxton_uninit_cdclk(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +
> +	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
> +	udelay(10);
> +
> +	if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
> +		DRM_ERROR("DBuf power disable timeout!\n");
> +
> +	/* Set minimum (bypass) frequency, in effect turning off the DE PLL */
> +	broxton_set_cdclk(dev, 19200);
> +
> +	intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
> +}
> +
>  /* returns HPLL frequency in kHz */
>  static int valleyview_get_vco(struct drm_i915_private *dev_priv)
>  {
> @@ -5363,6 +5538,26 @@ static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
>  		return 200000;
>  }
>  
> +static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
> +			      int max_pixclk)
> +{
> +	/*
> +	 * FIXME:
> +	 * - remove the guardband, it's not needed on BXT
> +	 * - set 19.2MHz bypass frequency if there are no active pipes
> +	 */
> +	if (max_pixclk > 576000*9/10)
> +		return 624000;
> +	else if (max_pixclk > 384000*9/10)
> +		return 576000;
> +	else if (max_pixclk > 288000*9/10)
> +		return 384000;
> +	else if (max_pixclk > 144000*9/10)
> +		return 288000;
> +	else
> +		return 144000;
> +}
> +
>  /* compute the max pixel clock for new configuration */
>  static int intel_mode_max_pixclk(struct drm_atomic_state *state)
>  {
> @@ -5392,12 +5587,17 @@ static int valleyview_modeset_global_pipes(struct drm_atomic_state *state,
>  	struct drm_i915_private *dev_priv = to_i915(state->dev);
>  	struct intel_crtc *intel_crtc;
>  	int max_pixclk = intel_mode_max_pixclk(state);
> +	int cdclk;
>  
>  	if (max_pixclk < 0)
>  		return max_pixclk;
>  
> -	if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
> -	    dev_priv->cdclk_freq)
> +	if (IS_VALLEYVIEW(dev_priv))
> +		cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
> +	else
> +		cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
> +
> +	if (cdclk == dev_priv->cdclk_freq)
>  		return 0;
>  
>  	/* disable/enable all currently active pipes while we change cdclk */
> @@ -8827,6 +9027,23 @@ void hsw_disable_pc8(struct drm_i915_private *dev_priv)
>  	intel_prepare_ddi(dev);
>  }
>  
> +static void broxton_modeset_global_resources(struct drm_atomic_state *state)
> +{
> +	struct drm_device *dev = state->dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	int max_pixclk = intel_mode_max_pixclk(state);
> +	int req_cdclk;
> +
> +	/* see the comment in valleyview_modeset_global_resources */
> +	if (WARN_ON(max_pixclk < 0))
> +		return;
> +
> +	req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
> +
> +	if (req_cdclk != dev_priv->cdclk_freq)
> +		broxton_set_cdclk(dev, req_cdclk);
> +}
> +
>  static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
>  				      struct intel_crtc_state *crtc_state)
>  {
> @@ -11983,7 +12200,7 @@ static int __intel_set_mode(struct drm_crtc *crtc,
>  	 * mode set on this crtc.  For other crtcs we need to use the
>  	 * adjusted_mode bits in the crtc directly.
>  	 */
> -	if (IS_VALLEYVIEW(dev)) {
> +	if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
>  		ret = valleyview_modeset_global_pipes(state, &prepare_pipes);
>  		if (ret)
>  			goto done;
> @@ -14005,6 +14222,9 @@ static void intel_init_display(struct drm_device *dev)
>  	} else if (IS_VALLEYVIEW(dev)) {
>  		dev_priv->display.modeset_global_resources =
>  			valleyview_modeset_global_resources;
> +	} else if (IS_BROXTON(dev)) {
> +		dev_priv->display.modeset_global_resources =
> +			broxton_modeset_global_resources;
>  	}
>  
>  	switch (INTEL_INFO(dev)->gen) {
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 6a2ee0c..5ba88eb 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1112,6 +1112,9 @@ void intel_prepare_reset(struct drm_device *dev);
>  void intel_finish_reset(struct drm_device *dev);
>  void hsw_enable_pc8(struct drm_i915_private *dev_priv);
>  void hsw_disable_pc8(struct drm_i915_private *dev_priv);
> +void broxton_init_cdclk(struct drm_device *dev);
> +void broxton_uninit_cdclk(struct drm_device *dev);
> +void broxton_set_cdclk(struct drm_device *dev, int frequency);
>  void intel_dp_get_m_n(struct intel_crtc *crtc,
>  		      struct intel_crtc_state *pipe_config);
>  void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
> -- 
> 2.1.0

-- 
Ville Syrjälä
Intel OTC
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[PATCH v3 34/49] drm/i915/bxt: Restrict PORT_CLK_SEL programming below gen9

[Imre Deak]

From: Satheeshakrishna M <satheeshakrishna.m@intel.com>

PORT_CLK_SEL programming is needed only on HSW/BDW.

v2:
- don't program PORT_CLK_SEL from mst encoders either (imre)
v3:
- fix the check for GEN9+ in intel_mst_pre_enable_dp() (damien)

Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c    | 4 ++--
 drivers/gpu/drm/i915/intel_dp_mst.c | 6 ++++--
 2 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 31cadb8..6bdccb2 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1565,7 +1565,7 @@ static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
 
 		I915_WRITE(DPLL_CTRL2, val);
 
-	} else {
+	} else if (INTEL_INFO(dev)->gen < 9) {
 		WARN_ON(crtc->config->ddi_pll_sel == PORT_CLK_SEL_NONE);
 		I915_WRITE(PORT_CLK_SEL(port), crtc->config->ddi_pll_sel);
 	}
@@ -1624,7 +1624,7 @@ static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
 	if (IS_SKYLAKE(dev))
 		I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
 					DPLL_CTRL2_DDI_CLK_OFF(port)));
-	else
+	else if (INTEL_INFO(dev)->gen < 9)
 		I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
 }
 
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
index 7335089..3945057 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -173,8 +173,10 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder)
 	if (intel_dp->active_mst_links == 0) {
 		enum port port = intel_ddi_get_encoder_port(encoder);
 
-		I915_WRITE(PORT_CLK_SEL(port),
-			   intel_crtc->config->ddi_pll_sel);
+		/* FIXME: add support for SKL */
+		if (INTEL_INFO(dev)->gen < 9)
+			I915_WRITE(PORT_CLK_SEL(port),
+				   intel_crtc->config->ddi_pll_sel);
 
 		intel_ddi_init_dp_buf_reg(&intel_dig_port->base);
 
-- 
2.1.0

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[PATCH v2 35/49] drm/i915/bxt: fix panel fitter setup in crtc disable/enable

[Imre Deak]

From: Jesse Barnes <jbarnes@virtuousgeek.org>

Broxton has the same panel fitter registers as Skylake.

v2:
- add MISSING_CASE for future platforms (daniel)

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Sagar Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 19 +++++++++++++------
 1 file changed, 13 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 5ee5d8c..11281f4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4881,10 +4881,12 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
 
 	intel_ddi_enable_pipe_clock(intel_crtc);
 
-	if (IS_SKYLAKE(dev))
+	if (INTEL_INFO(dev)->gen == 9)
 		skylake_pfit_update(intel_crtc, 1);
-	else
+	else if (INTEL_INFO(dev)->gen < 9)
 		ironlake_pfit_enable(intel_crtc);
+	else
+		MISSING_CASE(INTEL_INFO(dev)->gen);
 
 	/*
 	 * On ILK+ LUT must be loaded before the pipe is running but with
@@ -5029,10 +5031,12 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
 
 	intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
 
-	if (IS_SKYLAKE(dev))
+	if (INTEL_INFO(dev)->gen == 9)
 		skylake_pfit_update(intel_crtc, 0);
-	else
+	else if (INTEL_INFO(dev)->gen < 9)
 		ironlake_pfit_disable(intel_crtc);
+	else
+		MISSING_CASE(INTEL_INFO(dev)->gen);
 
 	intel_ddi_disable_pipe_clock(intel_crtc);
 
@@ -9199,10 +9203,13 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
 
 	pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
 	if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
-		if (IS_SKYLAKE(dev))
+		if (INTEL_INFO(dev)->gen == 9)
 			skylake_get_pfit_config(crtc, pipe_config);
-		else
+		else if (INTEL_INFO(dev)->gen < 9)
 			ironlake_get_pfit_config(crtc, pipe_config);
+		else
+			MISSING_CASE(INTEL_INFO(dev)->gen);
+
 	} else {
 		pipe_config->scaler_state.scaler_id = -1;
 		pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
-- 
2.1.0

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Re: [PATCH 30.1/49] drm/i915/bxt: add display initialize/uninitialize sequence (PHY)

[Ville Syrjälä]

On Wed, Apr 15, 2015 at 04:42:57PM +0300, Imre Deak wrote:
> From: Vandana Kannan <vandana.kannan@intel.com>
> 
> Add PHY specific display initialization sequence as per BSpec.
> 
> Note that the PHY initialization/uninitialization are done
> at their current place only for simplicity, in a future patch - when more
> of the runtime PM features will be enabled - these will be moved to
> power well#1 and modeset encoder enabling/disabling hooks respectively.
> 
> The call to uninitialize the PHY during system/runtime suspend will be
> added later in this patchset.
> 
> v1: Added function definitions in header files
> v2: Imre's review comments addressed
> - Moved CDCLK related definitions to i915_reg.h
> - Removed defintions for CDCLK frequency
> - Split uninit_cdclk() by adding a phy_uninit function
> - Calculate freq and decimal based on input frequency
> - Program SSA precharge based on input frequency
> - Use wait_for 1ms instead 200us udelay for DE PLL locking
> - Removed initial value for divider, freq, decimal, ratio.
> - Replaced polling loops with wait_for
> - Parameterized latency optim setting
> - Fix the parts where DE PLL has to be disabled.
> - Call CDCLK selection from mode set
> 
> v3: (imre)
> - add note about the plan to move the cdclk/phy init to a better place
> - take rps.hw_lock around pcode access
> - fix DDI PHY timeout value
> - squash in Vandana's "PORT_CL2CM_DW6_A BUN fix",
>   "DDI PHY programming register defn", "Do ddi_phy_init always",
> - move PHY register macros next to the corresponding CHV/VLV macros
> - move DE PLL register macros here from another patch since they are
>   used here first
> - add BXT_ prefix to CDCLK flags
> - s/COMMON_RESET/COMMON_RESET_DIS/ and clarify related code comments
> - fix incorrect read value for the RMW of BXT_PHY_CTL_FAMILY_DDI
> - fix using GT_DISPLAY_EDP_POWER_ON vs. GT_DISPLAY_DDI_POWER_ON
>   when powering on DDI ports
> - fix incorrect port when setting BXT_PORT_TX_DW14_LN for DDI ports
> - add missing masking when programming CDCLK_FREQ_DECIMAL
> - add missing powering on for DDI-C port, rename OCL2_LDOFUSE_PWR_EN
>   to OCL2_LDOFUSE_PWR_DIS to reduce confusion
> - add note about mismatch with bspec in the PORT_REF_DW6 fields
> - factor out PHY init code to a new function, so we can call it for
>   PHY1 and PHY0, instead of open-coding the same
> 
> v4: (ville)
> - split the CDCLK/PHY parts into two patches, update commit message
>   accordingly
> - use the existing dpio_phy enum instead of adding a new one for the
>   same purpose
> - flip the meaning of PHYs so that PHY_A is PHY1 and PHY_BC is PHY0 to
>   better match CHV
> - s/BXT_PHY/_BXT_PHY/
> - use _PIPE for _BXT_PHY instead of open-coding it
> - drop _0_2_0_GTTMMADR suffix from BXT_P_CR_GT_DISP_PWRON
> - define GT_DISPLAY_POWER_ON in a more standard way
> - make a note that the CHV ConfigDB also disagrees about GRC_CODE field
>   definitions
> - fix lane optimization refactoring fumble from v3
> - add per PHY uninit functions to match the init counterparts
> 
> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> (v2)
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Looking OK. Stuffing some/all of it into a power well and/or into the
port enable/disable code may be the right thing to do later, but this
should at least get it up and running for now.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h  |  96 ++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_ddi.c | 125 +++++++++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_drv.h |   2 +
>  3 files changed, 223 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c79bf8d..1903e37 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1117,6 +1117,102 @@ enum skl_disp_power_wells {
>  #define   DPIO_FRC_LATENCY_SHFIT	8
>  #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
>  #define   DPIO_UPAR_SHIFT		30
> +
> +/* BXT PHY registers */
> +#define _BXT_PHY(phy, a, b)		_PIPE((phy), (a), (b))
> +
> +#define BXT_P_CR_GT_DISP_PWRON		0x138090
> +#define   GT_DISPLAY_POWER_ON(phy)	(1 << (phy))
> +
> +#define _PHY_CTL_FAMILY_EDP		0x64C80
> +#define _PHY_CTL_FAMILY_DDI		0x64C90
> +#define   COMMON_RESET_DIS		(1 << 31)
> +#define BXT_PHY_CTL_FAMILY(phy)		_BXT_PHY((phy), _PHY_CTL_FAMILY_DDI, \
> +							_PHY_CTL_FAMILY_EDP)
> +
> +/* BXT PHY common lane registers */
> +#define _PORT_CL1CM_DW0_A		0x162000
> +#define _PORT_CL1CM_DW0_BC		0x6C000
> +#define   PHY_POWER_GOOD		(1 << 16)
> +#define BXT_PORT_CL1CM_DW0(phy)		_BXT_PHY((phy), _PORT_CL1CM_DW0_BC, \
> +							_PORT_CL1CM_DW0_A)
> +
> +#define _PORT_CL1CM_DW9_A		0x162024
> +#define _PORT_CL1CM_DW9_BC		0x6C024
> +#define   IREF0RC_OFFSET_SHIFT		8
> +#define   IREF0RC_OFFSET_MASK		(0xFF << IREF0RC_OFFSET_SHIFT)
> +#define BXT_PORT_CL1CM_DW9(phy)		_BXT_PHY((phy), _PORT_CL1CM_DW9_BC, \
> +							_PORT_CL1CM_DW9_A)
> +
> +#define _PORT_CL1CM_DW10_A		0x162028
> +#define _PORT_CL1CM_DW10_BC		0x6C028
> +#define   IREF1RC_OFFSET_SHIFT		8
> +#define   IREF1RC_OFFSET_MASK		(0xFF << IREF1RC_OFFSET_SHIFT)
> +#define BXT_PORT_CL1CM_DW10(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW10_BC, \
> +							_PORT_CL1CM_DW10_A)
> +
> +#define _PORT_CL1CM_DW28_A		0x162070
> +#define _PORT_CL1CM_DW28_BC		0x6C070
> +#define   OCL1_POWER_DOWN_EN		(1 << 23)
> +#define   DW28_OLDO_DYN_PWR_DOWN_EN	(1 << 22)
> +#define   SUS_CLK_CONFIG		0x3
> +#define BXT_PORT_CL1CM_DW28(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW28_BC, \
> +							_PORT_CL1CM_DW28_A)
> +
> +#define _PORT_CL1CM_DW30_A		0x162078
> +#define _PORT_CL1CM_DW30_BC		0x6C078
> +#define   OCL2_LDOFUSE_PWR_DIS		(1 << 6)
> +#define BXT_PORT_CL1CM_DW30(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW30_BC, \
> +							_PORT_CL1CM_DW30_A)
> +
> +/* Defined for PHY0 only */
> +#define BXT_PORT_CL2CM_DW6_BC		0x6C358
> +#define   DW6_OLDO_DYN_PWR_DOWN_EN	(1 << 28)
> +
> +/* BXT PHY Ref registers */
> +#define _PORT_REF_DW3_A			0x16218C
> +#define _PORT_REF_DW3_BC		0x6C18C
> +#define   GRC_DONE			(1 << 22)
> +#define BXT_PORT_REF_DW3(phy)		_BXT_PHY((phy), _PORT_REF_DW3_BC, \
> +							_PORT_REF_DW3_A)
> +
> +#define _PORT_REF_DW6_A			0x162198
> +#define _PORT_REF_DW6_BC		0x6C198
> +/*
> + * FIXME: BSpec/CHV ConfigDB disagrees on the following two fields, fix them
> + * after testing.
> + */
> +#define   GRC_CODE_SHIFT		23
> +#define   GRC_CODE_MASK			(0x1FF << GRC_CODE_SHIFT)
> +#define   GRC_CODE_FAST_SHIFT		16
> +#define   GRC_CODE_FAST_MASK		(0x7F << GRC_CODE_FAST_SHIFT)
> +#define   GRC_CODE_SLOW_SHIFT		8
> +#define   GRC_CODE_SLOW_MASK		(0xFF << GRC_CODE_SLOW_SHIFT)
> +#define   GRC_CODE_NOM_MASK		0xFF
> +#define BXT_PORT_REF_DW6(phy)		_BXT_PHY((phy), _PORT_REF_DW6_BC,	\
> +						      _PORT_REF_DW6_A)
> +
> +#define _PORT_REF_DW8_A			0x1621A0
> +#define _PORT_REF_DW8_BC		0x6C1A0
> +#define   GRC_DIS			(1 << 15)
> +#define   GRC_RDY_OVRD			(1 << 1)
> +#define BXT_PORT_REF_DW8(phy)		_BXT_PHY((phy), _PORT_REF_DW8_BC,	\
> +						      _PORT_REF_DW8_A)
> +
> +/* BXT PHY TX registers */
> +#define _BXT_LANE_OFFSET(lane)           (((lane) >> 1) * 0x200 +	\
> +					  ((lane) & 1) * 0x80)
> +
> +#define _PORT_TX_DW14_LN0_A		0x162538
> +#define _PORT_TX_DW14_LN0_B		0x6C538
> +#define _PORT_TX_DW14_LN0_C		0x6C938
> +#define   LATENCY_OPTIM_SHIFT		30
> +#define   LATENCY_OPTIM			(1 << LATENCY_OPTIM_SHIFT)
> +#define BXT_PORT_TX_DW14_LN(port, lane)	(_PORT3((port), _PORT_TX_DW14_LN0_A,   \
> +							_PORT_TX_DW14_LN0_B,   \
> +							_PORT_TX_DW14_LN0_C) + \
> +					 _BXT_LANE_OFFSET(lane))
> +
>  /*
>   * Fence registers
>   */
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 25d697b..31cadb8 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1864,6 +1864,130 @@ static void skl_shared_dplls_init(struct drm_i915_private *dev_priv)
>  	}
>  }
>  
> +static void broxton_phy_init(struct drm_i915_private *dev_priv,
> +			     enum dpio_phy phy)
> +{
> +	enum port port;
> +	uint32_t val;
> +
> +	val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
> +	val |= GT_DISPLAY_POWER_ON(phy);
> +	I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
> +
> +	/* Considering 10ms timeout until BSpec is updated */
> +	if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10))
> +		DRM_ERROR("timeout during PHY%d power on\n", phy);
> +
> +	for (port =  (phy == DPIO_PHY0 ? PORT_B : PORT_A);
> +	     port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) {
> +		int lane;
> +
> +		for (lane = 0; lane < 4; lane++) {
> +			val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
> +			/*
> +			 * Note that on CHV this flag is called UPAR, but has
> +			 * the same function.
> +			 */
> +			val &= ~LATENCY_OPTIM;
> +			if (lane != 1)
> +				val |= LATENCY_OPTIM;
> +
> +			I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val);
> +		}
> +	}
> +
> +	/* Program PLL Rcomp code offset */
> +	val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
> +	val &= ~IREF0RC_OFFSET_MASK;
> +	val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
> +	I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
> +
> +	val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
> +	val &= ~IREF1RC_OFFSET_MASK;
> +	val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
> +	I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
> +
> +	/* Program power gating */
> +	val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
> +	val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
> +		SUS_CLK_CONFIG;
> +	I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
> +
> +	if (phy == DPIO_PHY0) {
> +		val = I915_READ(BXT_PORT_CL2CM_DW6_BC);
> +		val |= DW6_OLDO_DYN_PWR_DOWN_EN;
> +		I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val);
> +	}
> +
> +	val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
> +	val &= ~OCL2_LDOFUSE_PWR_DIS;
> +	/*
> +	 * On PHY1 disable power on the second channel, since no port is
> +	 * connected there. On PHY0 both channels have a port, so leave it
> +	 * enabled.
> +	 * TODO: port C is only connected on BXT-P, so on BXT0/1 we should
> +	 * power down the second channel on PHY0 as well.
> +	 */
> +	if (phy == DPIO_PHY1)
> +		val |= OCL2_LDOFUSE_PWR_DIS;
> +	I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
> +
> +	if (phy == DPIO_PHY0) {
> +		uint32_t grc_code;
> +		/*
> +		 * PHY0 isn't connected to an RCOMP resistor so copy over
> +		 * the corresponding calibrated value from PHY1, and disable
> +		 * the automatic calibration on PHY0.
> +		 */
> +		if (wait_for(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE,
> +			     10))
> +			DRM_ERROR("timeout waiting for PHY1 GRC\n");
> +
> +		val = I915_READ(BXT_PORT_REF_DW6(DPIO_PHY1));
> +		val = (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
> +		grc_code = val << GRC_CODE_FAST_SHIFT |
> +			   val << GRC_CODE_SLOW_SHIFT |
> +			   val;
> +		I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code);
> +
> +		val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0));
> +		val |= GRC_DIS | GRC_RDY_OVRD;
> +		I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val);
> +	}
> +
> +	val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
> +	val |= COMMON_RESET_DIS;
> +	I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
> +}
> +
> +void broxton_ddi_phy_init(struct drm_device *dev)
> +{
> +	/* Enable PHY1 first since it provides Rcomp for PHY0 */
> +	broxton_phy_init(dev->dev_private, DPIO_PHY1);
> +	broxton_phy_init(dev->dev_private, DPIO_PHY0);
> +}
> +
> +static void broxton_phy_uninit(struct drm_i915_private *dev_priv,
> +			       enum dpio_phy phy)
> +{
> +	uint32_t val;
> +
> +	val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
> +	val &= ~COMMON_RESET_DIS;
> +	I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
> +}
> +
> +void broxton_ddi_phy_uninit(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +
> +	broxton_phy_uninit(dev_priv, DPIO_PHY1);
> +	broxton_phy_uninit(dev_priv, DPIO_PHY0);
> +
> +	/* FIXME: do this in broxton_phy_uninit per phy */
> +	I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 0);
> +}
> +
>  void intel_ddi_pll_init(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -1882,6 +2006,7 @@ void intel_ddi_pll_init(struct drm_device *dev)
>  			DRM_ERROR("LCPLL1 is disabled\n");
>  	} else if (IS_BROXTON(dev)) {
>  		broxton_init_cdclk(dev);
> +		broxton_ddi_phy_init(dev);
>  	} else {
>  		/*
>  		 * The LCPLL register should be turned on by the BIOS. For now
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 5ba88eb..5266985 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1115,6 +1115,8 @@ void hsw_disable_pc8(struct drm_i915_private *dev_priv);
>  void broxton_init_cdclk(struct drm_device *dev);
>  void broxton_uninit_cdclk(struct drm_device *dev);
>  void broxton_set_cdclk(struct drm_device *dev, int frequency);
> +void broxton_ddi_phy_init(struct drm_device *dev);
> +void broxton_ddi_phy_uninit(struct drm_device *dev);
>  void intel_dp_get_m_n(struct intel_crtc *crtc,
>  		      struct intel_crtc_state *pipe_config);
>  void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
> -- 
> 2.1.0

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH v3 34/49] drm/i915/bxt: Restrict PORT_CLK_SEL programming below gen9

[Sagar Arun Kamble]

On Wed, 2015-04-15 at 17:15 +0300, Imre Deak wrote:
> From: Satheeshakrishna M <satheeshakrishna.m@intel.com>
> 
> PORT_CLK_SEL programming is needed only on HSW/BDW.
> 
> v2:
> - don't program PORT_CLK_SEL from mst encoders either (imre)
> v3:
> - fix the check for GEN9+ in intel_mst_pre_enable_dp() (damien)
> 
> Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Reviewed-by: Sagar Kamble <sagar.a.kamble at intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ddi.c    | 4 ++--
>  drivers/gpu/drm/i915/intel_dp_mst.c | 6 ++++--
>  2 files changed, 6 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 31cadb8..6bdccb2 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1565,7 +1565,7 @@ static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
>  
>  		I915_WRITE(DPLL_CTRL2, val);
>  
> -	} else {
> +	} else if (INTEL_INFO(dev)->gen < 9) {
>  		WARN_ON(crtc->config->ddi_pll_sel == PORT_CLK_SEL_NONE);
>  		I915_WRITE(PORT_CLK_SEL(port), crtc->config->ddi_pll_sel);
>  	}
> @@ -1624,7 +1624,7 @@ static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
>  	if (IS_SKYLAKE(dev))
>  		I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
>  					DPLL_CTRL2_DDI_CLK_OFF(port)));
> -	else
> +	else if (INTEL_INFO(dev)->gen < 9)
>  		I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
>  }
>  
> diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
> index 7335089..3945057 100644
> --- a/drivers/gpu/drm/i915/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/intel_dp_mst.c
> @@ -173,8 +173,10 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder)
>  	if (intel_dp->active_mst_links == 0) {
>  		enum port port = intel_ddi_get_encoder_port(encoder);
>  
> -		I915_WRITE(PORT_CLK_SEL(port),
> -			   intel_crtc->config->ddi_pll_sel);
> +		/* FIXME: add support for SKL */
> +		if (INTEL_INFO(dev)->gen < 9)
> +			I915_WRITE(PORT_CLK_SEL(port),
> +				   intel_crtc->config->ddi_pll_sel);
>  
>  		intel_ddi_init_dp_buf_reg(&intel_dig_port->base);
>  


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Re: [PATCH 29/49] drm/i915: Rename vlv_cdclk_freq to cdclk_freq

[Ville Syrjälä]

On Tue, Mar 17, 2015 at 11:39:55AM +0200, Imre Deak wrote:
> From: Vandana Kannan <vandana.kannan@intel.com>
> 
> Rename vlv_cdclk_freq to cdclk_freq so that it can be used for all
> platforms as required. Needed by the next patch.
> 
> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
> Signed-off-by: A.Sunil Kamath <sunil.kamath@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.h      |  2 +-
>  drivers/gpu/drm/i915/intel_display.c | 18 ++++++++++--------
>  2 files changed, 11 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 52e5f18..1b2a294 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1659,7 +1659,7 @@ struct drm_i915_private {
>  	int num_fence_regs; /* 8 on pre-965, 16 otherwise */
>  
>  	unsigned int fsb_freq, mem_freq, is_ddr3;
> -	unsigned int vlv_cdclk_freq;
> +	unsigned int cdclk_freq;
>  	unsigned int hpll_freq;
>  
>  	/**
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index e54e948..b91862e 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4879,16 +4879,16 @@ static void vlv_update_cdclk(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  
> -	dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
> +	dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
>  	DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
> -			 dev_priv->vlv_cdclk_freq);
> +			 dev_priv->cdclk_freq);
>  
>  	/*
>  	 * Program the gmbus_freq based on the cdclk frequency.
>  	 * BSpec erroneously claims we should aim for 4MHz, but
>  	 * in fact 1MHz is the correct frequency.
>  	 */
> -	I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
> +	I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
>  }
>  
>  /* Adjust CDclk dividers to allow high res or save power if possible */
> @@ -4897,7 +4897,8 @@ static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	u32 val, cmd;
>  
> -	WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
> +	WARN_ON(dev_priv->display.get_display_clock_speed(dev)
> +					!= dev_priv->cdclk_freq);
>  
>  	if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
>  		cmd = 2;
> @@ -4961,7 +4962,8 @@ static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	u32 val, cmd;
>  
> -	WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
> +	WARN_ON(dev_priv->display.get_display_clock_speed(dev)
> +						!= dev_priv->cdclk_freq);
>  
>  	switch (cdclk) {
>  	case 333333:
> @@ -5050,7 +5052,7 @@ static void valleyview_modeset_global_pipes(struct drm_device *dev,
>  	int max_pixclk = intel_mode_max_pixclk(dev_priv);
>  
>  	if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
> -	    dev_priv->vlv_cdclk_freq)
> +	    dev_priv->cdclk_freq)
>  		return;
>  
>  	/* disable/enable all currently active pipes while we change cdclk */
> @@ -5068,7 +5070,7 @@ static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
>  	else
>  		default_credits = PFI_CREDIT(8);
>  
> -	if (DIV_ROUND_CLOSEST(dev_priv->vlv_cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
> +	if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
>  		/* CHV suggested value is 31 or 63 */
>  		if (IS_CHERRYVIEW(dev_priv))
>  			credits = PFI_CREDIT_31;
> @@ -5101,7 +5103,7 @@ static void valleyview_modeset_global_resources(struct drm_device *dev)
>  	int max_pixclk = intel_mode_max_pixclk(dev_priv);
>  	int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
>  
> -	if (req_cdclk != dev_priv->vlv_cdclk_freq) {
> +	if (req_cdclk != dev_priv->cdclk_freq) {
>  		/*
>  		 * FIXME: We can end up here with all power domains off, yet
>  		 * with a CDCLK frequency other than the minimum. To account
> -- 
> 2.1.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 32/49] drm/i915/bxt: Implement enable/disable for Display C9 state

[Daniel Vetter]

On Tue, Mar 17, 2015 at 11:39:58AM +0200, Imre Deak wrote:
> From: "A.Sunil Kamath" <sunil.kamath@intel.com>
> 
> v2: Modified as per review comments from Imre
> - Mention enabling instead of allowing in the debug trace and
>   remove unnecessary comments.
> 
> v3:
> - Rebase to latest.
> - Move DC9-related functions from intel_display.c to intel_runtime_pm.c.
> 
> v4: (imre)
> - remove DC5 disabling, it's a nop at this point
> - squashed in Suketu's "Assert the requirements to enter or exit DC9"
>   patch
> - remove check for RUNTIME_PM from assert_can_enable_dc9, it's not a
>   dependency
> 
> Signed-off-by: A.Sunil Kamath <sunil.kamath@intel.com> (v3)
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h         |  5 +++
>  drivers/gpu/drm/i915/intel_drv.h        |  2 +
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 66 +++++++++++++++++++++++++++++++++
>  3 files changed, 73 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 95532b4..4c781cb 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6942,6 +6942,11 @@ enum bxt_phy {
>  #define   BXT_DE_PLL_PLL_ENABLE		(1 << 31)
>  #define   BXT_DE_PLL_LOCK		(1 << 30)
>  
> +/* GEN9 DC */
> +#define DC_STATE_EN			0x45504
> +#define  DC_STATE_EN_UPTO_DC5		(1<<0)
> +#define  DC_STATE_EN_DC9		(1<<3)
> +
>  /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
>   * since on HSW we can't write to it using I915_WRITE. */
>  #define D_COMP_HSW			(MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 4bc2041..262314b 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1024,6 +1024,8 @@ void hsw_disable_pc8(struct drm_i915_private *dev_priv);
>  void bxt_init_cdclk(struct drm_device *dev);
>  void bxt_uninit_cdclk(struct drm_device *dev);
>  void bxt_ddi_phy_init(struct drm_device *dev);
> +void bxt_enable_dc9(struct drm_i915_private *dev_priv);
> +void bxt_disable_dc9(struct drm_i915_private *dev_priv);
>  void intel_dp_get_m_n(struct intel_crtc *crtc,
>  		      struct intel_crtc_state *pipe_config);
>  void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index ff5cce3..8fe2fde 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -351,6 +351,72 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv,
>  	BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) |	\
>  	BIT(POWER_DOMAIN_INIT))
>  
> +static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
> +{
> +	struct drm_device *dev = dev_priv->dev;
> +
> +	WARN(!IS_BROXTON(dev), "Platform doesn't support DC9.\n");
> +	WARN((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
> +		"DC9 already programmed to be enabled.\n");
> +	WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
> +		"DC5 still not disabled to enable DC9.\n");
> +	WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on.\n");
> +	WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n");
> +
> +	 /*
> +	  * TODO: check for the following to verify the conditions to enter DC9
> +	  * state are satisfied:
> +	  * 1] Check relevant display engine registers to verify if mode set
> +	  * disable sequence was followed.
> +	  * 2] Check if display uninitialize sequence is initialized.
> +	  */
> +}
> +
> +static void assert_can_disable_dc9(struct drm_i915_private *dev_priv)
> +{
> +	WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n");
> +	WARN(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
> +		"DC9 already programmed to be disabled.\n");
> +	WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
> +		"DC5 still not disabled.\n");
> +
> +	 /*
> +	  * TODO: check for the following to verify DC9 state was indeed
> +	  * entered before programming to disable it:
> +	  * 1] Check relevant display engine registers to verify if mode
> +	  *  set disable sequence was followed.
> +	  * 2] Check if display uninitialize sequence is initialized.
> +	  */
> +}
> +
> +void bxt_enable_dc9(struct drm_i915_private *dev_priv)
> +{
> +	uint32_t val;
> +
> +	assert_can_enable_dc9(dev_priv);
> +
> +	DRM_DEBUG_KMS("Enabling DC9\n");
> +
> +	val = I915_READ(DC_STATE_EN);
> +	val |= DC_STATE_EN_DC9;
> +	I915_WRITE(DC_STATE_EN, val);
> +	POSTING_READ(DC_STATE_EN);
> +}
> +
> +void bxt_disable_dc9(struct drm_i915_private *dev_priv)
> +{
> +	uint32_t val;
> +
> +	assert_can_disable_dc9(dev_priv);
> +
> +	DRM_DEBUG_KMS("Disabling DC9\n");
> +
> +	val = I915_READ(DC_STATE_EN);
> +	val &= ~DC_STATE_EN_DC9;
> +	I915_WRITE(DC_STATE_EN, val);
> +	POSTING_READ(DC_STATE_EN);
> +}

Standard comment about patch splitting: Please don't add functions or
structures (or new member fields and other variables) without using them
in the same patch: That way the patch can't be understood fully when just
linearly reading through patches and hence somewhat defeats the purpose of
patch splitting.

Instead I recommend to first wire up dummy functions to sketch the larger
picture and then in the next patch fill in details.

Thanks, Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [PATCH 42/49] drm/i915/bxt: Assign PLL for pipe

[Daniel Vetter]

On Tue, Mar 17, 2015 at 11:40:08AM +0200, Imre Deak wrote:
> From: Satheeshakrishna M <satheeshakrishna.m@intel.com>
> 
> Assign PLL for pipe (dependent on port attached to the pipe)
> 
> v2:
> - fix incorrect encoder vs. new_encoder check for crtc (imre)
> 
> v3:
> - warn and return error if no encoder is attached (imre)
> 
> Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> (v2)
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ddi.c     | 21 ------------------
>  drivers/gpu/drm/i915/intel_display.c | 41 ++++++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_drv.h     |  1 +
>  3 files changed, 42 insertions(+), 21 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index fa4f8f4..0a5d71e 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -491,27 +491,6 @@ intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
>  	return ret;
>  }
>  
> -static struct intel_encoder *
> -intel_ddi_get_crtc_new_encoder(struct intel_crtc *crtc)
> -{
> -	struct drm_device *dev = crtc->base.dev;
> -	struct intel_encoder *intel_encoder, *ret = NULL;
> -	int num_encoders = 0;
> -
> -	for_each_intel_encoder(dev, intel_encoder) {
> -		if (intel_encoder->new_crtc == crtc) {
> -			ret = intel_encoder;
> -			num_encoders++;
> -		}
> -	}
> -
> -	WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
> -	     pipe_name(crtc->pipe));
> -
> -	BUG_ON(ret == NULL);
> -	return ret;
> -}
> -
>  #define LC_FREQ 2700
>  #define LC_FREQ_2K U64_C(LC_FREQ * 2000)
>  
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 3606366..411bf50 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4037,6 +4037,27 @@ void intel_put_shared_dpll(struct intel_crtc *crtc)
>  	crtc->config->shared_dpll = DPLL_ID_PRIVATE;
>  }
>  
> +struct intel_encoder *
> +intel_ddi_get_crtc_new_encoder(struct intel_crtc *crtc)
> +{
> +	struct drm_device *dev = crtc->base.dev;
> +	struct intel_encoder *intel_encoder, *ret = NULL;
> +	int num_encoders = 0;
> +
> +	for_each_intel_encoder(dev, intel_encoder) {
> +		if (intel_encoder->new_crtc == crtc) {
> +			ret = intel_encoder;
> +			num_encoders++;
> +		}
> +	}
> +
> +	WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
> +	     pipe_name(crtc->pipe));
> +
> +	BUG_ON(ret == NULL);
> +	return ret;
> +}

Imo no need to move this function around, so I dropped that part.
-Daniel

> +
>  struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
>  						struct intel_crtc_state *crtc_state)
>  {
> @@ -4057,6 +4078,26 @@ struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
>  		goto found;
>  	}
>  
> +	if (IS_BROXTON(dev_priv->dev)) {
> +		/* PLL is attached to port in bxt */
> +		struct intel_encoder *encoder;
> +		struct intel_digital_port *intel_dig_port;
> +
> +		encoder = intel_ddi_get_crtc_new_encoder(crtc);
> +		if (WARN_ON(!encoder))
> +			return NULL;
> +
> +		intel_dig_port = enc_to_dig_port(&encoder->base);
> +		/* 1:1 mapping between ports and PLLs */
> +		i = (enum intel_dpll_id)intel_dig_port->port;
> +		pll = &dev_priv->shared_dplls[i];
> +		DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
> +			crtc->base.base.id, pll->name);
> +		WARN_ON(pll->new_config->crtc_mask);
> +
> +		goto found;
> +	}
> +
>  	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
>  		pll = &dev_priv->shared_dplls[i];
>  
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 56a5cc9..097fb85 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -991,6 +991,7 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv,
>  			bool state);
>  #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
>  #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
> +struct intel_encoder *intel_ddi_get_crtc_new_encoder(struct intel_crtc *crtc);
>  struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
>  						struct intel_crtc_state *state);
>  void intel_put_shared_dpll(struct intel_crtc *crtc);
> -- 
> 2.1.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [PATCH 46/49] drm/i915: Iterate through the initialized DDIs to prepare their buffers

[Ander Conselvan De Oliveira]

On Tue, 2015-03-17 at 11:40 +0200, Imre Deak wrote:
> From: Damien Lespiau <damien.lespiau@intel.com>
> 
> Not every DDIs is necessarily connected can be strapped off and, in the
> future, we'll have platforms with a different number of default DDI
> ports. So, let's only call intel_prepare_ddi_buffers() on DDI ports that
> are actually detected.
> 
> We also use the opportunity to give a struct intel_digital_port to
> intel_prepare_ddi_buffers() as we'll need it in a following patch to
> query if the port supports HMDI or not.
> 
> On my HSW machine this removes the initialization of a couple of
> (unused) DDIs.
> 
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h  |  4 ++++
>  drivers/gpu/drm/i915/intel_ddi.c | 16 ++++++++++++----
>  2 files changed, 16 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index e4dd4bba..e6402b0 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -251,6 +251,10 @@ enum hpd_pin {
>  			    &dev->mode_config.connector_list,	\
>  			    base.head)
>  
> +#define for_each_digital_port(dev, digital_port)		\
> +	list_for_each_entry(digital_port,			\
> +			    &dev->mode_config.encoder_list,	\
> +			    base.base.head)

This breaks HSW machines with CRTs. We can't just assume all the
encoders are digital ports.

Ander

>  
>  #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
>  	list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index ff62054..5c18018 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -189,10 +189,12 @@ enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
>   * in either FDI or DP modes only, as HDMI connections will work with both
>   * of those
>   */
> -static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port)
> +static void intel_prepare_ddi_buffers(struct drm_device *dev,
> +				      struct intel_digital_port *intel_dig_port)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	u32 reg;
> +	int port = intel_dig_port->port;
>  	int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry,
>  	    size;
>  	int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
> @@ -307,13 +309,19 @@ static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port)
>   */
>  void intel_prepare_ddi(struct drm_device *dev)
>  {
> -	int port;
> +	struct intel_digital_port *intel_dig_port;
> +	bool visited[I915_MAX_PORTS] = { 0, };
>  
>  	if (!HAS_DDI(dev))
>  		return;
>  
> -	for (port = PORT_A; port <= PORT_E; port++)
> -		intel_prepare_ddi_buffers(dev, port);
> +	for_each_digital_port(dev, intel_dig_port) {
> +		if (visited[intel_dig_port->port])
> +			continue;
> +
> +		intel_prepare_ddi_buffers(dev, intel_dig_port);
> +		visited[intel_dig_port->port] = true;
> +	}
>  }
>  
>  static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,


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Re: [PATCH 46/49] drm/i915: Iterate through the initialized DDIs to prepare their buffers

[Imre Deak]

On Fri, 2015-04-24 at 15:47 +0300, Ander Conselvan De Oliveira wrote:
> On Tue, 2015-03-17 at 11:40 +0200, Imre Deak wrote:
> > From: Damien Lespiau <damien.lespiau@intel.com>
> > 
> > Not every DDIs is necessarily connected can be strapped off and, in the
> > future, we'll have platforms with a different number of default DDI
> > ports. So, let's only call intel_prepare_ddi_buffers() on DDI ports that
> > are actually detected.
> > 
> > We also use the opportunity to give a struct intel_digital_port to
> > intel_prepare_ddi_buffers() as we'll need it in a following patch to
> > query if the port supports HMDI or not.
> > 
> > On my HSW machine this removes the initialization of a couple of
> > (unused) DDIs.
> > 
> > Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_drv.h  |  4 ++++
> >  drivers/gpu/drm/i915/intel_ddi.c | 16 ++++++++++++----
> >  2 files changed, 16 insertions(+), 4 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index e4dd4bba..e6402b0 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -251,6 +251,10 @@ enum hpd_pin {
> >  			    &dev->mode_config.connector_list,	\
> >  			    base.head)
> >  
> > +#define for_each_digital_port(dev, digital_port)		\
> > +	list_for_each_entry(digital_port,			\
> > +			    &dev->mode_config.encoder_list,	\
> > +			    base.base.head)
> 
> This breaks HSW machines with CRTs. We can't just assume all the
> encoders are digital ports.

I posted a fix for this:
http://lists.freedesktop.org/archives/intel-gfx/2015-April/064993.html

--Imre


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