[PATCH 0/3] GIC counter fixes

[PATCH 0/3] GIC counter fixes

[Markos Chandras]

Hi,

Here are a few patches to ensure the GIC counter is running before we attempt
to use it since the default value on a MIPS core can be '1' which means
the GIC counter will be stopped after a CPU reset. These patches are based
on 4.0-rc1.

Markos Chandras (3):
  irqchip: irq-mips-gic: Add new functions to start/stop the GIC counter
  clocksource: mips-gic-timer: Ensure GIC counter is running
  MIPS: Malta: malta-time: Ensure GIC counter is running

 arch/mips/mti-malta/malta-time.c     |  4 +++-
 drivers/clocksource/mips-gic-timer.c |  3 +++
 drivers/irqchip/irq-mips-gic.c       | 21 +++++++++++++++++++++
 include/linux/irqchip/mips-gic.h     |  2 ++
 4 files changed, 29 insertions(+), 1 deletion(-)

-- 
2.3.3

[PATCH 0/3] GIC counter fixes

[Markos Chandras]

Hi,

Here are a few patches to ensure the GIC counter is running before we attempt
to use it since the default value on a MIPS core can be '1' which means
the GIC counter will be stopped after a CPU reset. These patches are based
on 4.0-rc1.

Markos Chandras (3):
  irqchip: irq-mips-gic: Add new functions to start/stop the GIC counter
  clocksource: mips-gic-timer: Ensure GIC counter is running
  MIPS: Malta: malta-time: Ensure GIC counter is running

 arch/mips/mti-malta/malta-time.c     |  4 +++-
 drivers/clocksource/mips-gic-timer.c |  3 +++
 drivers/irqchip/irq-mips-gic.c       | 21 +++++++++++++++++++++
 include/linux/irqchip/mips-gic.h     |  2 ++
 4 files changed, 29 insertions(+), 1 deletion(-)

-- 
2.3.3

[PATCH 1/3] irqchip: irq-mips-gic: Add new functions to start/stop the GIC counter

[Markos Chandras]

We add new functions to start and stop the GIC counter since there are no
guarantees the counter will be running after a CPU reset. The GIC counter
is stopped by setting the 29th bit on the GIC Config register and it is
started by clearing that bit.

Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Bresticker <abrestic@chromium.org>
Cc: Qais Yousef <qais.yousef@imgtec.com>
Cc: <linux-kernel@vger.kernel.org>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
---
 drivers/irqchip/irq-mips-gic.c   | 21 +++++++++++++++++++++
 include/linux/irqchip/mips-gic.h |  2 ++
 2 files changed, 23 insertions(+)

diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c
index 9acdc080e7ec..f2d269bca789 100644
--- a/drivers/irqchip/irq-mips-gic.c
+++ b/drivers/irqchip/irq-mips-gic.c
@@ -166,6 +166,27 @@ cycle_t gic_read_compare(void)
 
 	return (((cycle_t) hi) << 32) + lo;
 }
+
+void gic_start_count(void)
+{
+	u32 gicconfig;
+
+	/* Start the counter */
+	gicconfig = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG));
+	gicconfig &= ~(1 << GIC_SH_CONFIG_COUNTSTOP_SHF);
+	gic_write(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig);
+}
+
+void gic_stop_count(void)
+{
+	u32 gicconfig;
+
+	/* Stop the counter */
+	gicconfig = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG));
+	gicconfig |= 1 << GIC_SH_CONFIG_COUNTSTOP_SHF;
+	gic_write(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig);
+}
+
 #endif
 
 static bool gic_local_irq_is_routable(int intr)
diff --git a/include/linux/irqchip/mips-gic.h b/include/linux/irqchip/mips-gic.h
index e6a6aac451db..3ea2e4754c40 100644
--- a/include/linux/irqchip/mips-gic.h
+++ b/include/linux/irqchip/mips-gic.h
@@ -240,6 +240,8 @@ extern unsigned int gic_get_count_width(void);
 extern cycle_t gic_read_compare(void);
 extern void gic_write_compare(cycle_t cnt);
 extern void gic_write_cpu_compare(cycle_t cnt, int cpu);
+extern void gic_start_count(void);
+extern void gic_stop_count(void);
 extern void gic_send_ipi(unsigned int intr);
 extern unsigned int plat_ipi_call_int_xlate(unsigned int);
 extern unsigned int plat_ipi_resched_int_xlate(unsigned int);
-- 
2.3.3

[PATCH 1/3] irqchip: irq-mips-gic: Add new functions to start/stop the GIC counter

[Markos Chandras]

We add new functions to start and stop the GIC counter since there are no
guarantees the counter will be running after a CPU reset. The GIC counter
is stopped by setting the 29th bit on the GIC Config register and it is
started by clearing that bit.

Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Bresticker <abrestic@chromium.org>
Cc: Qais Yousef <qais.yousef@imgtec.com>
Cc: <linux-kernel@vger.kernel.org>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
---
 drivers/irqchip/irq-mips-gic.c   | 21 +++++++++++++++++++++
 include/linux/irqchip/mips-gic.h |  2 ++
 2 files changed, 23 insertions(+)

diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c
index 9acdc080e7ec..f2d269bca789 100644
--- a/drivers/irqchip/irq-mips-gic.c
+++ b/drivers/irqchip/irq-mips-gic.c
@@ -166,6 +166,27 @@ cycle_t gic_read_compare(void)
 
 	return (((cycle_t) hi) << 32) + lo;
 }
+
+void gic_start_count(void)
+{
+	u32 gicconfig;
+
+	/* Start the counter */
+	gicconfig = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG));
+	gicconfig &= ~(1 << GIC_SH_CONFIG_COUNTSTOP_SHF);
+	gic_write(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig);
+}
+
+void gic_stop_count(void)
+{
+	u32 gicconfig;
+
+	/* Stop the counter */
+	gicconfig = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG));
+	gicconfig |= 1 << GIC_SH_CONFIG_COUNTSTOP_SHF;
+	gic_write(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig);
+}
+
 #endif
 
 static bool gic_local_irq_is_routable(int intr)
diff --git a/include/linux/irqchip/mips-gic.h b/include/linux/irqchip/mips-gic.h
index e6a6aac451db..3ea2e4754c40 100644
--- a/include/linux/irqchip/mips-gic.h
+++ b/include/linux/irqchip/mips-gic.h
@@ -240,6 +240,8 @@ extern unsigned int gic_get_count_width(void);
 extern cycle_t gic_read_compare(void);
 extern void gic_write_compare(cycle_t cnt);
 extern void gic_write_cpu_compare(cycle_t cnt, int cpu);
+extern void gic_start_count(void);
+extern void gic_stop_count(void);
 extern void gic_send_ipi(unsigned int intr);
 extern unsigned int plat_ipi_call_int_xlate(unsigned int);
 extern unsigned int plat_ipi_resched_int_xlate(unsigned int);
-- 
2.3.3

[PATCH 2/3] clocksource: mips-gic-timer: Ensure GIC counter is running

[Markos Chandras]

Start the GIC counter after configuring the clocksource since there
are no guarantees the counter will be running after a CPU reset.

Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: <linux-kernel@vger.kernel.org>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
---
 drivers/clocksource/mips-gic-timer.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/clocksource/mips-gic-timer.c b/drivers/clocksource/mips-gic-timer.c
index 3bd31b1321f6..16adbc1fa4c1 100644
--- a/drivers/clocksource/mips-gic-timer.c
+++ b/drivers/clocksource/mips-gic-timer.c
@@ -133,6 +133,9 @@ static void __init __gic_clocksource_init(void)
 	clocksource_register_hz(&gic_clocksource, gic_frequency);
 
 	gic_clockevent_init();
+
+	/* And finally start the counter */
+	gic_start_count();
 }
 
 void __init gic_clocksource_init(unsigned int frequency)
-- 
2.3.3

[PATCH 2/3] clocksource: mips-gic-timer: Ensure GIC counter is running

[Markos Chandras]

Start the GIC counter after configuring the clocksource since there
are no guarantees the counter will be running after a CPU reset.

Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: <linux-kernel@vger.kernel.org>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
---
 drivers/clocksource/mips-gic-timer.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/clocksource/mips-gic-timer.c b/drivers/clocksource/mips-gic-timer.c
index 3bd31b1321f6..16adbc1fa4c1 100644
--- a/drivers/clocksource/mips-gic-timer.c
+++ b/drivers/clocksource/mips-gic-timer.c
@@ -133,6 +133,9 @@ static void __init __gic_clocksource_init(void)
 	clocksource_register_hz(&gic_clocksource, gic_frequency);
 
 	gic_clockevent_init();
+
+	/* And finally start the counter */
+	gic_start_count();
 }
 
 void __init gic_clocksource_init(unsigned int frequency)
-- 
2.3.3

[PATCH 3/3] MIPS: Malta: malta-time: Ensure GIC counter is running

[Markos Chandras]

Start the GIC counter before we try to determine its frequency.

Cc: <linux-kernel@vger.kernel.org>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
---
 arch/mips/mti-malta/malta-time.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/mips/mti-malta/malta-time.c b/arch/mips/mti-malta/malta-time.c
index ce02dbdedc62..128a74bd7cea 100644
--- a/arch/mips/mti-malta/malta-time.c
+++ b/arch/mips/mti-malta/malta-time.c
@@ -87,8 +87,10 @@ static void __init estimate_frequencies(void)
 
 	/* Initialize counters. */
 	start = read_c0_count();
-	if (gic_present)
+	if (gic_present) {
+		gic_start_count();
 		gicstart = gic_read_count();
+	}
 
 	/* Read counter exactly on falling edge of update flag. */
 	while (CMOS_READ(RTC_REG_A) & RTC_UIP);
-- 
2.3.3

[PATCH 3/3] MIPS: Malta: malta-time: Ensure GIC counter is running

[Markos Chandras]

Start the GIC counter before we try to determine its frequency.

Cc: <linux-kernel@vger.kernel.org>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
---
 arch/mips/mti-malta/malta-time.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/mips/mti-malta/malta-time.c b/arch/mips/mti-malta/malta-time.c
index ce02dbdedc62..128a74bd7cea 100644
--- a/arch/mips/mti-malta/malta-time.c
+++ b/arch/mips/mti-malta/malta-time.c
@@ -87,8 +87,10 @@ static void __init estimate_frequencies(void)
 
 	/* Initialize counters. */
 	start = read_c0_count();
-	if (gic_present)
+	if (gic_present) {
+		gic_start_count();
 		gicstart = gic_read_count();
+	}
 
 	/* Read counter exactly on falling edge of update flag. */
 	while (CMOS_READ(RTC_REG_A) & RTC_UIP);
-- 
2.3.3

Re: [PATCH 2/3] clocksource: mips-gic-timer: Ensure GIC counter is running

[Daniel Lezcano]

On 03/23/2015 01:32 PM, Markos Chandras wrote:
> Start the GIC counter after configuring the clocksource since there
> are no guarantees the counter will be running after a CPU reset.
>
> Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Cc: <linux-kernel@vger.kernel.org>
> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>

Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>

> ---
>   drivers/clocksource/mips-gic-timer.c | 3 +++
>   1 file changed, 3 insertions(+)
>
> diff --git a/drivers/clocksource/mips-gic-timer.c b/drivers/clocksource/mips-gic-timer.c
> index 3bd31b1321f6..16adbc1fa4c1 100644
> --- a/drivers/clocksource/mips-gic-timer.c
> +++ b/drivers/clocksource/mips-gic-timer.c
> @@ -133,6 +133,9 @@ static void __init __gic_clocksource_init(void)
>   	clocksource_register_hz(&gic_clocksource, gic_frequency);
>
>   	gic_clockevent_init();
> +
> +	/* And finally start the counter */
> +	gic_start_count();
>   }
>
>   void __init gic_clocksource_init(unsigned int frequency)
>


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Re: [PATCH 1/3] irqchip: irq-mips-gic: Add new functions to start/stop the GIC counter

[Jason Cooper]

On Mon, Mar 23, 2015 at 12:32:01PM +0000, Markos Chandras wrote:
> We add new functions to start and stop the GIC counter since there are no
> guarantees the counter will be running after a CPU reset. The GIC counter
> is stopped by setting the 29th bit on the GIC Config register and it is
> started by clearing that bit.
> 
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Cc: Jason Cooper <jason@lakedaemon.net>
> Cc: Andrew Bresticker <abrestic@chromium.org>
> Cc: Qais Yousef <qais.yousef@imgtec.com>
> Cc: <linux-kernel@vger.kernel.org>
> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
> ---
>  drivers/irqchip/irq-mips-gic.c   | 21 +++++++++++++++++++++
>  include/linux/irqchip/mips-gic.h |  2 ++
>  2 files changed, 23 insertions(+)

Applied to irqchip/core

thx,

Jason.