From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58330) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ya6D1-0001hJ-U0 for qemu-devel@nongnu.org; Mon, 23 Mar 2015 13:32:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Ya6Cu-0005OB-A7 for qemu-devel@nongnu.org; Mon, 23 Mar 2015 13:32:14 -0400 Received: from cantor2.suse.de ([195.135.220.15]:52963 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ya6Cu-0005Nl-0K for qemu-devel@nongnu.org; Mon, 23 Mar 2015 13:32:08 -0400 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Mon, 23 Mar 2015 18:32:02 +0100 Message-Id: <1427131923-4670-4-git-send-email-afaerber@suse.de> In-Reply-To: <1427131923-4670-1-git-send-email-afaerber@suse.de> References: <1427131923-4670-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH RFC 3/4] pc: Create sockets and cores for CPUs List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Richard Henderson , =?UTF-8?q?Andreas=20F=C3=A4rber?= , "Michael S. Tsirkin" Inline realized=3Dtrue from pc_new_cpu() so that the realization can be deferred, as it would otherwise create a device[n] node. Signed-off-by: Andreas F=C3=A4rber --- hw/i386/pc.c | 66 ++++++++++++++++++++++++++++++++++++++++++++++++++++--= ------ 1 file changed, 58 insertions(+), 8 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 2c48277..492c262 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -54,11 +54,14 @@ #include "exec/memory.h" #include "exec/address-spaces.h" #include "sysemu/arch_init.h" +#include "sysemu/cpus.h" #include "qemu/bitmap.h" #include "qemu/config-file.h" #include "hw/acpi/acpi.h" #include "hw/acpi/cpu_hotplug.h" #include "hw/cpu/icc_bus.h" +#include "hw/i386/cpu-socket.h" +#include "hw/i386/cpu-core.h" #include "hw/boards.h" #include "hw/pci/pci_host.h" #include "acpi-build.h" @@ -990,6 +993,17 @@ void pc_acpi_smi_interrupt(void *opaque, int irq, in= t level) } } =20 +static inline size_t pc_cpu_core_size(void) +{ + return sizeof(X86CPUCore); +} + +static inline X86CPUCore *pc_cpu_socket_get_core(X86CPUSocket *socket, + unsigned int index) +{ + return &socket->core[index]; +} + static X86CPU *pc_new_cpu(const char *cpu_model, int64_t apic_id, DeviceState *icc_bridge, Error **errp) { @@ -1009,7 +1023,6 @@ static X86CPU *pc_new_cpu(const char *cpu_model, in= t64_t apic_id, qdev_set_parent_bus(DEVICE(cpu), qdev_get_child_bus(icc_bridge, "icc= ")); =20 object_property_set_int(OBJECT(cpu), apic_id, "apic-id", &local_err)= ; - object_property_set_bool(OBJECT(cpu), true, "realized", &local_err); =20 out: if (local_err) { @@ -1060,15 +1073,19 @@ void pc_hot_add_cpu(const int64_t id, Error **err= p) error_propagate(errp, local_err); return; } + object_property_set_bool(OBJECT(cpu), true, "realized", errp); object_unref(OBJECT(cpu)); } =20 void pc_cpus_init(const char *cpu_model, DeviceState *icc_bridge) { - int i; + int i, j, k; + X86CPUSocket *socket; + X86CPUCore *core; X86CPU *cpu =3D NULL; Error *error =3D NULL; unsigned long apic_id_limit; + int sockets, cpu_index =3D 0; =20 /* init CPUs */ if (cpu_model =3D=3D NULL) { @@ -1087,14 +1104,41 @@ void pc_cpus_init(const char *cpu_model, DeviceSt= ate *icc_bridge) exit(1); } =20 - for (i =3D 0; i < smp_cpus; i++) { - cpu =3D pc_new_cpu(cpu_model, x86_cpu_apic_id_from_index(i), - icc_bridge, &error); + sockets =3D smp_cpus / smp_cores / smp_threads; + for (i =3D 0; i < sockets; i++) { + socket =3D g_malloc0(sizeof(*socket) + smp_cores * pc_cpu_core_s= ize()); + object_initialize(socket, sizeof(*socket), TYPE_X86_CPU_SOCKET); + OBJECT(socket)->free =3D g_free; + + for (j =3D 0; j < smp_cores; j++) { + core =3D pc_cpu_socket_get_core(socket, j); + object_initialize(core, sizeof(*core), TYPE_X86_CPU_CORE); + object_property_add_child(OBJECT(socket), "core[*]", + OBJECT(core), &error); + if (error) { + goto error; + } + + for (k =3D 0; k < smp_threads; k++) { + cpu =3D pc_new_cpu(cpu_model, + x86_cpu_apic_id_from_index(cpu_index), + icc_bridge, &error); + if (error) { + goto error; + } + object_property_add_child(OBJECT(core), "thread[*]", + OBJECT(cpu), &error); + object_unref(OBJECT(cpu)); + if (error) { + goto error; + } + cpu_index++; + } + } + object_property_set_bool(OBJECT(socket), true, "realized", &erro= r); if (error) { - error_report_err(error); - exit(1); + goto error; } - object_unref(OBJECT(cpu)); } =20 /* map APIC MMIO area if CPU has APIC */ @@ -1106,6 +1150,12 @@ void pc_cpus_init(const char *cpu_model, DeviceSta= te *icc_bridge) =20 /* tell smbios about cpuid version and features */ smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_ED= X]); + +error: + if (error) { + error_report_err(error); + exit(1); + } } =20 /* pci-info ROM file. Little endian format */ --=20 2.1.4