From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tomeu Vizoso Subject: [PATCH] drm/tegra: Reset the SOR during initialization Date: Wed, 25 Mar 2015 09:59:39 +0100 Message-ID: <1427273979-394-1-git-send-email-tomeu.vizoso@collabora.com> References: <20150324102447.GA18115@ulmo.nvidia.com> Return-path: In-Reply-To: <20150324102447.GA18115-AwZRO8vwLAwmlAP/+Wk3EA@public.gmane.org> Sender: linux-tegra-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org Cc: Tomeu Vizoso , Thierry Reding , =?UTF-8?q?Terje=20Bergstr=C3=B6m?= , David Airlie , Stephen Warren , Alexandre Courbot , dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: linux-tegra@vger.kernel.org As there isn't a way for the firmware on the Nyan chromebooks to hand over the display to the kernel, and the kernel isn't redoing the whole configuration at present. With this patch, the SOR is brought to a known state and we get correct display on every boot. Signed-off-by: Tomeu Vizoso --- v7: * Move the reset to the host1x_client_ops.init callback as suggested by Thierry * Reduced the time during which the reset line is asserted from 20ms to 2ms --- drivers/gpu/drm/tegra/sor.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c index 2afe478..027a25d22 100644 --- a/drivers/gpu/drm/tegra/sor.c +++ b/drivers/gpu/drm/tegra/sor.c @@ -1354,12 +1354,30 @@ static int tegra_sor_init(struct host1x_client *client) } } + /* + * XXX: Remove this reset once proper hand-over from firmware to + * kernel is possible. + */ + err = reset_control_assert(sor->rst); + if (err < 0) { + dev_err(sor->dev, "failed to assert SOR reset: %d\n", err); + return err; + } + err = clk_prepare_enable(sor->clk); if (err < 0) { dev_err(sor->dev, "failed to enable clock: %d\n", err); return err; } + msleep(2); + + err = reset_control_deassert(sor->rst); + if (err < 0) { + dev_err(sor->dev, "failed to deassert SOR reset: %d\n", err); + return err; + } + err = clk_prepare_enable(sor->clk_safe); if (err < 0) return err; -- 2.1.0 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752082AbbCYJAj (ORCPT ); Wed, 25 Mar 2015 05:00:39 -0400 Received: from mail-wi0-f173.google.com ([209.85.212.173]:38437 "EHLO mail-wi0-f173.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750735AbbCYJAg (ORCPT ); Wed, 25 Mar 2015 05:00:36 -0400 From: Tomeu Vizoso To: linux-tegra@vger.kernel.org Cc: Tomeu Vizoso , Thierry Reding , =?UTF-8?q?Terje=20Bergstr=C3=B6m?= , David Airlie , Stephen Warren , Alexandre Courbot , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH] drm/tegra: Reset the SOR during initialization Date: Wed, 25 Mar 2015 09:59:39 +0100 Message-Id: <1427273979-394-1-git-send-email-tomeu.vizoso@collabora.com> X-Mailer: git-send-email 2.1.0 In-Reply-To: <20150324102447.GA18115@ulmo.nvidia.com> References: <20150324102447.GA18115@ulmo.nvidia.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org As there isn't a way for the firmware on the Nyan chromebooks to hand over the display to the kernel, and the kernel isn't redoing the whole configuration at present. With this patch, the SOR is brought to a known state and we get correct display on every boot. Signed-off-by: Tomeu Vizoso --- v7: * Move the reset to the host1x_client_ops.init callback as suggested by Thierry * Reduced the time during which the reset line is asserted from 20ms to 2ms --- drivers/gpu/drm/tegra/sor.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c index 2afe478..027a25d22 100644 --- a/drivers/gpu/drm/tegra/sor.c +++ b/drivers/gpu/drm/tegra/sor.c @@ -1354,12 +1354,30 @@ static int tegra_sor_init(struct host1x_client *client) } } + /* + * XXX: Remove this reset once proper hand-over from firmware to + * kernel is possible. + */ + err = reset_control_assert(sor->rst); + if (err < 0) { + dev_err(sor->dev, "failed to assert SOR reset: %d\n", err); + return err; + } + err = clk_prepare_enable(sor->clk); if (err < 0) { dev_err(sor->dev, "failed to enable clock: %d\n", err); return err; } + msleep(2); + + err = reset_control_deassert(sor->rst); + if (err < 0) { + dev_err(sor->dev, "failed to deassert SOR reset: %d\n", err); + return err; + } + err = clk_prepare_enable(sor->clk_safe); if (err < 0) return err; -- 2.1.0