From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ian Campbell Subject: [PATCH 13/19] xen: arm: Annotate registers trapped by MDCR_EL2.TDRA Date: Tue, 31 Mar 2015 11:07:36 +0100 Message-ID: <1427796462-24376-13-git-send-email-ian.campbell@citrix.com> References: <1427796446.2115.34.camel@citrix.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1427796446.2115.34.camel@citrix.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: xen-devel@lists.xen.org Cc: julien.grall@linaro.org, tim@xen.org, Ian Campbell , stefano.stabellini@eu.citrix.com List-Id: xen-devel@lists.xenproject.org Signed-off-by: Ian Campbell --- xen/arch/arm/traps.c | 32 ++++++++++++++++++++++++++++++++ xen/include/asm-arm/cpregs.h | 4 ++++ xen/include/asm-arm/sysregs.h | 1 + 3 files changed, 37 insertions(+) diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 21bef01..7c37cec 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -1790,6 +1790,17 @@ static void do_cp14_32(struct cpu_user_regs *regs, const union hsr hsr) switch ( hsr.bits & HSR_CP32_REGS_MASK ) { + /* + * MDCR_EL2.TDRA + * + * ARMv7 (DDI 0406C.b): B1.14.15 + * ARMv8 (DDI 0487A.d): D1-1508 Table D1-57 + * + * Unhandled: + * DBGDRAR + * DBGDSAR + */ + case HSR_CPREG32(DBGDIDR): /* * Read-only register. Accessible by EL0 if DBGDSCRext.UDCCdis @@ -1840,6 +1851,8 @@ static void do_cp14_32(struct cpu_user_regs *regs, const union hsr hsr) * * ARMv7 (DDI 0406C.b): B1.14.16 * ARMv8 (DDI 0487A.d): D1-1507 Table D1-54 + * + * And all other unknown registers. */ default: gdprintk(XENLOG_ERR, @@ -1870,6 +1883,17 @@ static void do_cp14_64(struct cpu_user_regs *regs, const union hsr hsr) * * ARMv7 (DDI 0406C.b): B1.14.16 * ARMv8 (DDI 0487A.d): D1-1507 Table D1-54 + * + * MDCR_EL2.TDRA + * + * ARMv7 (DDI 0406C.b): B1.14.15 + * ARMv8 (DDI 0487A.d): D1-1508 Table D1-57 + * + * Unhandled: + * DBGDRAR64 + * DBGDSAR64 + * + * And all other unknown registers. */ gdprintk(XENLOG_ERR, "%s p14, %d, r%d, r%d, cr%d @ 0x%"PRIregister"\n", @@ -1936,6 +1960,14 @@ static void do_sysreg(struct cpu_user_regs *regs, *x = v->arch.actlr; break; + /* + * MDCR_EL2.TDRA + * + * ARMv8 (DDI 0487A.d): D1-1508 Table D1-57 + */ + case HSR_SYSREG_MDRAR_EL1: + return handle_ro_raz(regs, x, hsr.sysreg.read, hsr, 1); + /* RAZ/WI registers: */ /* - Debug */ case HSR_SYSREG_MDSCR_EL1: diff --git a/xen/include/asm-arm/cpregs.h b/xen/include/asm-arm/cpregs.h index afe9148..9db8cfd 100644 --- a/xen/include/asm-arm/cpregs.h +++ b/xen/include/asm-arm/cpregs.h @@ -89,10 +89,14 @@ #define TEECR p14,6,c0,c0,0 /* ThumbEE Configuration Register */ /* CP14 CR1: */ +#define DBGDRAR64 p14,0,c1 /* Debug ROM Address Register (64-bit access) */ +#define DBGDRAR p14,0,c1,c0,0 /* Debug ROM Address Register (32-bit access) */ #define TEEHBR p14,6,c1,c0,0 /* ThumbEE Handler Base Register */ #define JOSCR p14,7,c1,c0,0 /* Jazelle OS Control Register */ /* CP14 CR2: */ +#define DBGDSAR64 p14,0,c2 /* Debug Self Address Offset Register (64-bit access) */ +#define DBGDSAR p14,0,c2,c0,0 /* Debug Self Address Offset Register (32-bit access) */ #define JMCR p14,7,c2,c0,0 /* Jazelle Main Configuration Register */ diff --git a/xen/include/asm-arm/sysregs.h b/xen/include/asm-arm/sysregs.h index d75e154..55457fd 100644 --- a/xen/include/asm-arm/sysregs.h +++ b/xen/include/asm-arm/sysregs.h @@ -45,6 +45,7 @@ #define HSR_SYSREG_DCCISW HSR_SYSREG(1,0,c7,c14,2) #define HSR_SYSREG_MDSCR_EL1 HSR_SYSREG(2,0,c0,c2,2) +#define HSR_SYSREG_MDRAR_EL1 HSR_SYSREG(2,0,c1,c0,0) #define HSR_SYSREG_OSLAR_EL1 HSR_SYSREG(2,0,c1,c0,4) #define HSR_SYSREG_OSDLR_EL1 HSR_SYSREG(2,0,c1,c3,4) #define HSR_SYSREG_MDCCSR_EL0 HSR_SYSREG(2,3,c0,c1,0) -- 1.7.10.4