From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ian Campbell Subject: [PATCH 19/19] xen: arm: Annotate source of ICC SGI register trapping Date: Tue, 31 Mar 2015 11:07:42 +0100 Message-ID: <1427796462-24376-19-git-send-email-ian.campbell@citrix.com> References: <1427796446.2115.34.camel@citrix.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1427796446.2115.34.camel@citrix.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: xen-devel@lists.xen.org Cc: julien.grall@linaro.org, tim@xen.org, Ian Campbell , stefano.stabellini@eu.citrix.com List-Id: xen-devel@lists.xenproject.org I was unable to find an ARMv8 ARM reference to this, so refer to the GIC Architecture Specification instead. ARMv8 ARM does cover other ways of trapping these accesses via ICH_HCR_EL2 but we don't use those and they trap additional registers as well. Signed-off-by: Ian Campbell --- xen/arch/arm/traps.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index cc5b8dd..71e349a 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -2144,6 +2144,12 @@ static void do_sysreg(struct cpu_user_regs *regs, return inject_undef_exception(regs, hsr); break; + /* + * HCR_EL2.FMO or HCR_EL2.IMO + * + * ARMv8: GIC Architecture Specification (PRD03-GENC-010745 24.0) + * Section 4.6.8. + */ case HSR_SYSREG_ICC_SGI1R_EL1: if ( !vgic_emulate(regs, hsr) ) { -- 1.7.10.4