[PATCH 1/2] drm/i915/vlv: save/restore the power context base reg

[PATCH 1/2] drm/i915/vlv: save/restore the power context base reg

[Jesse Barnes]

Some BIOSes (e.g. the one on the Minnowboard) don't save/restore this
reg.  If it's unlocked, we can just restore the previous value, and if
it's locked (in case the BIOS re-programmed it for us) the write will be
ignored and we'll still have "did it move" sanity check in the PM code to
warn us if something is still amiss.

References: https://bugs.freedesktop.org/show_bug.cgi?id=89611
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_drv.c | 2 ++
 drivers/gpu/drm/i915/i915_drv.h | 1 +
 2 files changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index c1a3cdb5..4d6d6f0 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1104,6 +1104,7 @@ static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
 	/* Gunit-Display CZ domain, 0x182028-0x1821CF */
 	s->gu_ctl0		= I915_READ(VLV_GU_CTL0);
 	s->gu_ctl1		= I915_READ(VLV_GU_CTL1);
+	s->pcbr			= I915_READ(VLV_PCBR);
 	s->clock_gate_dis2	= I915_READ(VLV_GUNIT_CLOCK_GATE2);
 
 	/*
@@ -1198,6 +1199,7 @@ static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
 	/* Gunit-Display CZ domain, 0x182028-0x1821CF */
 	I915_WRITE(VLV_GU_CTL0,			s->gu_ctl0);
 	I915_WRITE(VLV_GU_CTL1,			s->gu_ctl1);
+	I915_WRITE(VLV_PCBR,			s->pcbr);
 	I915_WRITE(VLV_GUNIT_CLOCK_GATE2,	s->clock_gate_dis2);
 }
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b13c552..f3ac683 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -994,6 +994,7 @@ struct vlv_s0ix_state {
 	/* Display 2 CZ domain */
 	u32 gu_ctl0;
 	u32 gu_ctl1;
+	u32 pcbr;
 	u32 clock_gate_dis2;
 };
 
-- 
1.9.1

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[PATCH 2/2] drm/i915/vlv: remove wait for previous GFX clk disable request

[Jesse Barnes]

Looks like it was introduced in:

commit 650ad970a39f8b6164fe8613edc150f585315289
Author: Imre Deak <imre.deak@intel.com>
Date:   Fri Apr 18 16:35:02 2014 +0300

    drm/i915: vlv: factor out vlv_force_gfx_clock and check for pending force-of

but I'm not sure why.  It has caused problems for us in the past (see
85250ddff7a603dfe0ec0503a9e6395f79424f61 and
8d4eee9cd7a170342dc6fbc2ee19ae77031a8cd5) and doesn't seem to be
required, so let's just drop it.

References: https://bugs.freedesktop.org/show_bug.cgi?id=89611
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_drv.c | 14 --------------
 1 file changed, 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 4d6d6f0..c3fdbb0 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1208,21 +1208,7 @@ int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
 	u32 val;
 	int err;
 
-	val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
-
 #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
-	/* Wait for a previous force-off to settle */
-	if (force_on && !IS_CHERRYVIEW(dev_priv->dev)) {
-		/* WARN_ON only for the Valleyview */
-		WARN_ON(!!(val & VLV_GFX_CLK_FORCE_ON_BIT) == force_on);
-
-		err = wait_for(!COND, 20);
-		if (err) {
-			DRM_ERROR("timeout waiting for GFX clock force-off (%08x)\n",
-				  I915_READ(VLV_GTLC_SURVIVABILITY_REG));
-			return err;
-		}
-	}
 
 	val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
 	val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
-- 
1.9.1

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Re: [PATCH 1/2] drm/i915/vlv: save/restore the power context base reg

[Jani Nikula]

On Thu, 02 Apr 2015, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> Some BIOSes (e.g. the one on the Minnowboard) don't save/restore this
> reg.  If it's unlocked, we can just restore the previous value, and if
> it's locked (in case the BIOS re-programmed it for us) the write will be
> ignored and we'll still have "did it move" sanity check in the PM code to
> warn us if something is still amiss.
>
> References: https://bugs.freedesktop.org/show_bug.cgi?id=89611

Both patches

Tested-by: Darren Hart <dvhart@linux.intel.com>
Cc: stable@vger.kernel.org


> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/i915_drv.c | 2 ++
>  drivers/gpu/drm/i915/i915_drv.h | 1 +
>  2 files changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index c1a3cdb5..4d6d6f0 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1104,6 +1104,7 @@ static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
>  	/* Gunit-Display CZ domain, 0x182028-0x1821CF */
>  	s->gu_ctl0		= I915_READ(VLV_GU_CTL0);
>  	s->gu_ctl1		= I915_READ(VLV_GU_CTL1);
> +	s->pcbr			= I915_READ(VLV_PCBR);
>  	s->clock_gate_dis2	= I915_READ(VLV_GUNIT_CLOCK_GATE2);
>  
>  	/*
> @@ -1198,6 +1199,7 @@ static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
>  	/* Gunit-Display CZ domain, 0x182028-0x1821CF */
>  	I915_WRITE(VLV_GU_CTL0,			s->gu_ctl0);
>  	I915_WRITE(VLV_GU_CTL1,			s->gu_ctl1);
> +	I915_WRITE(VLV_PCBR,			s->pcbr);
>  	I915_WRITE(VLV_GUNIT_CLOCK_GATE2,	s->clock_gate_dis2);
>  }
>  
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index b13c552..f3ac683 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -994,6 +994,7 @@ struct vlv_s0ix_state {
>  	/* Display 2 CZ domain */
>  	u32 gu_ctl0;
>  	u32 gu_ctl1;
> +	u32 pcbr;
>  	u32 clock_gate_dis2;
>  };
>  
> -- 
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
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Re: [PATCH 1/2] drm/i915/vlv: save/restore the power context base reg

[Imre Deak]

On Wed, 2015-04-01 at 14:22 -0700, Jesse Barnes wrote:
> Some BIOSes (e.g. the one on the Minnowboard) don't save/restore this
> reg.  If it's unlocked, we can just restore the previous value, and if
> it's locked (in case the BIOS re-programmed it for us) the write will be
> ignored and we'll still have "did it move" sanity check in the PM code to
> warn us if something is still amiss.
> 
> References: https://bugs.freedesktop.org/show_bug.cgi?id=89611
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>

Yea, the BIOS is supposed to program this reg according to the Gunit
doc, but we can't have any guarantee anyway.. I guess this is a problem
only for S3, but I can't see any problem saving/restoring it also during
s0ix, so:
Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.c | 2 ++
>  drivers/gpu/drm/i915/i915_drv.h | 1 +
>  2 files changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index c1a3cdb5..4d6d6f0 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1104,6 +1104,7 @@ static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
>  	/* Gunit-Display CZ domain, 0x182028-0x1821CF */
>  	s->gu_ctl0		= I915_READ(VLV_GU_CTL0);
>  	s->gu_ctl1		= I915_READ(VLV_GU_CTL1);
> +	s->pcbr			= I915_READ(VLV_PCBR);
>  	s->clock_gate_dis2	= I915_READ(VLV_GUNIT_CLOCK_GATE2);
>  
>  	/*
> @@ -1198,6 +1199,7 @@ static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
>  	/* Gunit-Display CZ domain, 0x182028-0x1821CF */
>  	I915_WRITE(VLV_GU_CTL0,			s->gu_ctl0);
>  	I915_WRITE(VLV_GU_CTL1,			s->gu_ctl1);
> +	I915_WRITE(VLV_PCBR,			s->pcbr);
>  	I915_WRITE(VLV_GUNIT_CLOCK_GATE2,	s->clock_gate_dis2);
>  }
>  
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index b13c552..f3ac683 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -994,6 +994,7 @@ struct vlv_s0ix_state {
>  	/* Display 2 CZ domain */
>  	u32 gu_ctl0;
>  	u32 gu_ctl1;
> +	u32 pcbr;
>  	u32 clock_gate_dis2;
>  };
>  


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Re: [PATCH 2/2] drm/i915/vlv: remove wait for previous GFX clk disable request

[Imre Deak]

On Wed, 2015-04-01 at 14:22 -0700, Jesse Barnes wrote:
> Looks like it was introduced in:
> 
> commit 650ad970a39f8b6164fe8613edc150f585315289
> Author: Imre Deak <imre.deak@intel.com>
> Date:   Fri Apr 18 16:35:02 2014 +0300
> 
>     drm/i915: vlv: factor out vlv_force_gfx_clock and check for pending force-of
> 
> but I'm not sure why.  It has caused problems for us in the past (see
> 85250ddff7a603dfe0ec0503a9e6395f79424f61 and
> 8d4eee9cd7a170342dc6fbc2ee19ae77031a8cd5) and doesn't seem to be
> required, so let's just drop it.
> 
> References: https://bugs.freedesktop.org/show_bug.cgi?id=89611
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/i915_drv.c | 14 --------------
>  1 file changed, 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 4d6d6f0..c3fdbb0 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1208,21 +1208,7 @@ int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
>  	u32 val;
>  	int err;
>  
> -	val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
> -
>  #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
> -	/* Wait for a previous force-off to settle */
> -	if (force_on && !IS_CHERRYVIEW(dev_priv->dev)) {
> -		/* WARN_ON only for the Valleyview */
> -		WARN_ON(!!(val & VLV_GFX_CLK_FORCE_ON_BIT) == force_on);
> -
> -		err = wait_for(!COND, 20);
> -		if (err) {
> -			DRM_ERROR("timeout waiting for GFX clock force-off (%08x)\n",
> -				  I915_READ(VLV_GTLC_SURVIVABILITY_REG));
> -			return err;
> -		}
> -	}

The reason I added this is that it's not clear what happens if you try
to force the clock on while the previous force-off operation is still
pending. That is if Punit will correctly cancel turning off the clock in
this case. Since the docs don't clarify this either I thought the above
is safer. Is it the WARN that triggers and only during resume (we also
call the function from vlv_set_rps_idle)? If so, then it's not a real
timeout but BIOS has left the force-on flag set and we could just skip
calling vlv_force_gfx_clock(true) in that case.

If the HW people can confirm that the above isn't needed then I'm also
ok to remove it.

>  
>  	val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
>  	val &= ~VLV_GFX_CLK_FORCE_ON_BIT;


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Re: [PATCH 1/2] drm/i915/vlv: save/restore the power context base reg

[Deepak S]

On Thursday 02 April 2015 02:52 AM, Jesse Barnes wrote:
> Some BIOSes (e.g. the one on the Minnowboard) don't save/restore this
> reg.  If it's unlocked, we can just restore the previous value, and if
> it's locked (in case the BIOS re-programmed it for us) the write will be
> ignored and we'll still have "did it move" sanity check in the PM code to
> warn us if something is still amiss.

Looks fine to me
Reviewed-by: Deepak S<deepak.s@linux.intel.com>

> References: https://bugs.freedesktop.org/show_bug.cgi?id=89611
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>   drivers/gpu/drm/i915/i915_drv.c | 2 ++
>   drivers/gpu/drm/i915/i915_drv.h | 1 +
>   2 files changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index c1a3cdb5..4d6d6f0 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1104,6 +1104,7 @@ static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
>   	/* Gunit-Display CZ domain, 0x182028-0x1821CF */
>   	s->gu_ctl0		= I915_READ(VLV_GU_CTL0);
>   	s->gu_ctl1		= I915_READ(VLV_GU_CTL1);
> +	s->pcbr			= I915_READ(VLV_PCBR);
>   	s->clock_gate_dis2	= I915_READ(VLV_GUNIT_CLOCK_GATE2);
>   
>   	/*
> @@ -1198,6 +1199,7 @@ static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
>   	/* Gunit-Display CZ domain, 0x182028-0x1821CF */
>   	I915_WRITE(VLV_GU_CTL0,			s->gu_ctl0);
>   	I915_WRITE(VLV_GU_CTL1,			s->gu_ctl1);
> +	I915_WRITE(VLV_PCBR,			s->pcbr);
>   	I915_WRITE(VLV_GUNIT_CLOCK_GATE2,	s->clock_gate_dis2);
>   }
>   
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index b13c552..f3ac683 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -994,6 +994,7 @@ struct vlv_s0ix_state {
>   	/* Display 2 CZ domain */
>   	u32 gu_ctl0;
>   	u32 gu_ctl1;
> +	u32 pcbr;
>   	u32 clock_gate_dis2;
>   };
>   

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Re: [PATCH 2/2] drm/i915/vlv: remove wait for previous GFX clk disable request

[Deepak S]

On Thursday 02 April 2015 02:52 AM, Jesse Barnes wrote:
> Looks like it was introduced in:
>
> commit 650ad970a39f8b6164fe8613edc150f585315289
> Author: Imre Deak <imre.deak@intel.com>
> Date:   Fri Apr 18 16:35:02 2014 +0300
>
>      drm/i915: vlv: factor out vlv_force_gfx_clock and check for pending force-of
>
> but I'm not sure why.  It has caused problems for us in the past (see
> 85250ddff7a603dfe0ec0503a9e6395f79424f61 and
> 8d4eee9cd7a170342dc6fbc2ee19ae77031a8cd5) and doesn't seem to be
> required, so let's just drop it.
>
> References: https://bugs.freedesktop.org/show_bug.cgi?id=89611
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>   drivers/gpu/drm/i915/i915_drv.c | 14 --------------
>   1 file changed, 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 4d6d6f0..c3fdbb0 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1208,21 +1208,7 @@ int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
>   	u32 val;
>   	int err;
>   
> -	val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
> -
>   #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
> -	/* Wait for a previous force-off to settle */
> -	if (force_on && !IS_CHERRYVIEW(dev_priv->dev)) {
> -		/* WARN_ON only for the Valleyview */
> -		WARN_ON(!!(val & VLV_GFX_CLK_FORCE_ON_BIT) == force_on);
> -
> -		err = wait_for(!COND, 20);
> -		if (err) {
> -			DRM_ERROR("timeout waiting for GFX clock force-off (%08x)\n",
> -				  I915_READ(VLV_GTLC_SURVIVABILITY_REG));
> -			return err;
> -		}
> -	}
>   

I agree, I do not think we need to wait for previous Gfx clk force-off.
Also, I do not see any race condition happening between diff Gfx force clk in driver. Lets just drop it :)

Reviewed-by: Deepak S  <deepak.s@linux.intel.com>

>   	val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
>   	val &= ~VLV_GFX_CLK_FORCE_ON_BIT;

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Re: [PATCH 2/2] drm/i915/vlv: remove wait for previous GFX clk disable request

[Darren Hart]

Jesse Barnes <jbarnes <at> virtuousgeek.org> writes:
> Looks like it was introduced in:
> 
> commit 650ad970a39f8b6164fe8613edc150f585315289
> Author: Imre Deak <imre.deak <at> intel.com>
> Date:   Fri Apr 18 16:35:02 2014 +0300
> 
>     drm/i915: vlv: factor out vlv_force_gfx_clock and check for pending
>     force-of
> 
> but I'm not sure why.  It has caused problems for us in the past (see
> 85250ddff7a603dfe0ec0503a9e6395f79424f61 and
> 8d4eee9cd7a170342dc6fbc2ee19ae77031a8cd5) and doesn't seem to be
> required, so let's just drop it.
> 
> References: https://bugs.freedesktop.org/show_bug.cgi?id=89611
> Signed-off-by: Jesse Barnes <jbarnes <at> virtuousgeek.org>


Thanks Jesse,

With this and 1/2 applied I was able to suspend/resume twice in a row
successfully on a MinnowBoard MAX dual-core (E3825) with the 0.78
firmware.

Tested-by: Darren Hart <dvhart@linux.intel.com>

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Re: [PATCH 2/2] drm/i915/vlv: remove wait for previous GFX clk disable request

[Jani Nikula]

On Thu, 02 Apr 2015, Darren Hart <darren.hart@intel.com> wrote:
> Jesse Barnes <jbarnes <at> virtuousgeek.org> writes:
>> Looks like it was introduced in:
>> 
>> commit 650ad970a39f8b6164fe8613edc150f585315289
>> Author: Imre Deak <imre.deak <at> intel.com>
>> Date:   Fri Apr 18 16:35:02 2014 +0300
>> 
>>     drm/i915: vlv: factor out vlv_force_gfx_clock and check for pending
>>     force-of
>> 
>> but I'm not sure why.  It has caused problems for us in the past (see
>> 85250ddff7a603dfe0ec0503a9e6395f79424f61 and
>> 8d4eee9cd7a170342dc6fbc2ee19ae77031a8cd5) and doesn't seem to be
>> required, so let's just drop it.
>> 
>> References: https://bugs.freedesktop.org/show_bug.cgi?id=89611
>> Signed-off-by: Jesse Barnes <jbarnes <at> virtuousgeek.org>
>
>
> Thanks Jesse,
>
> With this and 1/2 applied I was able to suspend/resume twice in a row
> successfully on a MinnowBoard MAX dual-core (E3825) with the 0.78
> firmware.
>
> Tested-by: Darren Hart <dvhart@linux.intel.com>

Both patches pushed to drm-intel-fixes, along with a cherry-pick of
85250ddff7a6 ("drm/i915/chv: Remove Wait for a previous gfx force-off")
from drm-next to avoid conflicts, all cc: stable. Thanks for the
patches, review, and testing.

BR,
Jani.



>
> _______________________________________________
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-- 
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