From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52122) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YiPmF-0001y6-Pj for qemu-devel@nongnu.org; Wed, 15 Apr 2015 12:03:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YiPmB-0001uT-QC for qemu-devel@nongnu.org; Wed, 15 Apr 2015 12:02:59 -0400 Received: from mail-oi0-f50.google.com ([209.85.218.50]:36292) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YiPmB-0001uM-Kl for qemu-devel@nongnu.org; Wed, 15 Apr 2015 12:02:55 -0400 Received: by oift201 with SMTP id t201so29221358oif.3 for ; Wed, 15 Apr 2015 09:02:55 -0700 (PDT) From: Greg Bellows Date: Wed, 15 Apr 2015 11:02:06 -0500 Message-Id: <1429113742-8371-1-git-send-email-greg.bellows@linaro.org> Subject: [Qemu-devel] [PATCH v3 00/16] target-arm: Add GICv1/SecExt and GICv2/Grouping List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: Greg Bellows This patch series adds ARM GICv1 and GICv2 security extension support. As a result GIC interrupt grouping and FIQ enablement have also been added. FIQ enablement is limited to ARM the ARM vexpress and virt machines. At the current moment, the security extension capability is not enabled as it depends on ARM secure address space support for proper operation. Instead, secure checks are hardwired as non-secure. v2 -> v3 - Add missing return in gic_dist_readb() - Fix typos in patch 7 - Add sign off to patches - Rebased to current upstream v1 -> v2 - Fixed GIC_SET macro logic for group 0 and 1 - Fixed gic_update to use correct GIC_CTLR bit for group 1 - Reworked gic_set/get_cpu_control to better handle non-security extension case for GICv1. - Fixed various BPR read/write issues. - Fixed EOIR ackctl issue. - Fixed issue with gic_acknowledge not properly checking secure state. - Fixed gic_update use of incorrect bit to check cpu_control group 1 enablement. - Added clarifying comments - Various fixes based on initial version review comments (see individual patches for details). Fabian Aggeler (15): hw/intc/arm_gic: Request FIQ sources hw/arm/vexpress.c: Wire FIQ between CPU <> GIC hw/intc/arm_gic: Add Security Extensions property hw/intc/arm_gic: Add ns_access() function hw/intc/arm_gic: Add Interrupt Group Registers hw/intc/arm_gic: Make ICDDCR/GICD_CTLR banked hw/intc/arm_gic: Make ICCICR/GICC_CTLR banked hw/intc/arm_gic: Make ICCBPR/GICC_BPR banked hw/intc/arm_gic: Implement Non-secure view of RPR hw/intc/arm_gic: Handle grouping for GICC_HPPIR hw/intc/arm_gic: Change behavior of EOIR writes hw/intc/arm_gic: Change behavior of IAR writes hw/intc/arm_gic: Restrict priority view hw/intc/arm_gic: Break out gic_update() function hw/intc/arm_gic: add gic_update() for grouping Greg Bellows (1): hw/arm/virt.c: Wire FIQ between CPU <> GIC hw/arm/vexpress.c | 2 + hw/arm/virt.c | 2 + hw/intc/arm_gic.c | 498 ++++++++++++++++++++++++++++++++++++--- hw/intc/arm_gic_common.c | 9 +- hw/intc/arm_gic_kvm.c | 8 +- hw/intc/armv7m_nvic.c | 2 +- hw/intc/gic_internal.h | 25 ++ include/hw/intc/arm_gic_common.h | 23 +- 8 files changed, 527 insertions(+), 42 deletions(-) -- 1.8.3.2