From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52231) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YiPmW-0002Uq-T7 for qemu-devel@nongnu.org; Wed, 15 Apr 2015 12:03:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YiPmR-0001xb-SM for qemu-devel@nongnu.org; Wed, 15 Apr 2015 12:03:16 -0400 Received: from mail-oi0-f42.google.com ([209.85.218.42]:33151) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YiPmR-0001xF-OA for qemu-devel@nongnu.org; Wed, 15 Apr 2015 12:03:11 -0400 Received: by oica37 with SMTP id a37so26929527oic.0 for ; Wed, 15 Apr 2015 09:03:11 -0700 (PDT) From: Greg Bellows Date: Wed, 15 Apr 2015 11:02:07 -0500 Message-Id: <1429113742-8371-2-git-send-email-greg.bellows@linaro.org> In-Reply-To: <1429113742-8371-1-git-send-email-greg.bellows@linaro.org> References: <1429113742-8371-1-git-send-email-greg.bellows@linaro.org> Subject: [Qemu-devel] [PATCH v3 01/16] hw/intc/arm_gic: Request FIQ sources List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: Fabian Aggeler , Greg Bellows From: Fabian Aggeler Preparing for FIQ lines from GIC to CPUs, which is needed for GIC Security Extensions. Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows --- hw/intc/arm_gic.c | 3 +++ include/hw/intc/arm_gic_common.h | 1 + 2 files changed, 4 insertions(+) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index a04c822..e9fb8b9 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -790,6 +790,9 @@ void gic_init_irqs_and_distributor(GICState *s) for (i = 0; i < NUM_CPU(s); i++) { sysbus_init_irq(sbd, &s->parent_irq[i]); } + for (i = 0; i < NUM_CPU(s); i++) { + sysbus_init_irq(sbd, &s->parent_fiq[i]); + } memory_region_init_io(&s->iomem, OBJECT(s), &gic_dist_ops, s, "gic_dist", 0x1000); } diff --git a/include/hw/intc/arm_gic_common.h b/include/hw/intc/arm_gic_common.h index f6887ed..01c6f24 100644 --- a/include/hw/intc/arm_gic_common.h +++ b/include/hw/intc/arm_gic_common.h @@ -50,6 +50,7 @@ typedef struct GICState { /*< public >*/ qemu_irq parent_irq[GIC_NCPU]; + qemu_irq parent_fiq[GIC_NCPU]; bool enabled; bool cpu_enabled[GIC_NCPU]; -- 1.8.3.2