From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52314) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YiPme-0002iS-0Y for qemu-devel@nongnu.org; Wed, 15 Apr 2015 12:03:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YiPmY-0001z0-B0 for qemu-devel@nongnu.org; Wed, 15 Apr 2015 12:03:23 -0400 Received: from mail-oi0-f51.google.com ([209.85.218.51]:33303) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YiPmY-0001yv-6i for qemu-devel@nongnu.org; Wed, 15 Apr 2015 12:03:18 -0400 Received: by oica37 with SMTP id a37so26933526oic.0 for ; Wed, 15 Apr 2015 09:03:17 -0700 (PDT) From: Greg Bellows Date: Wed, 15 Apr 2015 11:02:11 -0500 Message-Id: <1429113742-8371-6-git-send-email-greg.bellows@linaro.org> In-Reply-To: <1429113742-8371-1-git-send-email-greg.bellows@linaro.org> References: <1429113742-8371-1-git-send-email-greg.bellows@linaro.org> Subject: [Qemu-devel] [PATCH v3 05/16] hw/intc/arm_gic: Add ns_access() function List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: Fabian Aggeler , Greg Bellows From: Fabian Aggeler Security Extensions for GICv1 and GICv2 use register banking to provide transparent access to seperate Secure and Non-secure copies of GIC configuration registers. This function will later be replaced by code determining the security state of a read/write access to a register. Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows --- hw/intc/arm_gic.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index cdf7408..e0bce6e 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -45,6 +45,13 @@ static inline int gic_get_current_cpu(GICState *s) return 0; } +/* Security state of a read / write access */ +static inline bool ns_access(void) +{ + /* TODO: use actual security state */ + return true; +} + /* TODO: Many places that call this routine could be optimized. */ /* Update interrupt status after enabled or pending bits have been changed. */ void gic_update(GICState *s) -- 1.8.3.2