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From: linus.walleij@linaro.org (Linus Walleij)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 05/13] coresight: etb: let runtime PM handle core clock
Date: Fri, 17 Apr 2015 10:58:52 +0200	[thread overview]
Message-ID: <1429261140-13910-6-git-send-email-linus.walleij@linaro.org> (raw)
In-Reply-To: <1429261140-13910-1-git-send-email-linus.walleij@linaro.org>

This uses runtime PM to manage the PCLK ("amba_pclk") instead
of screwing around with the framework by going in and taking
a copy from the amba device. The amba bus core will uprepare
and disable the clock when the device is unused when
CONFIG_PM is selected, else the clock will be always on.

Prior to this patch, as the AMBA primecell bus code enables
the PCLK, it would be left on after probe as
the clk_prepare_enable() and clk_disable_unprepare() was
called and thus just increase and decreas the refcount by
one, without it reaching zero and actually disabling the
clock. Now the runtime PM callbacks will make sure the PCLK
is properly disabled after probe.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
 drivers/coresight/coresight-etb10.c | 35 +++++++++--------------------------
 1 file changed, 9 insertions(+), 26 deletions(-)

diff --git a/drivers/coresight/coresight-etb10.c b/drivers/coresight/coresight-etb10.c
index c9acd406f0d0..c4587510a826 100644
--- a/drivers/coresight/coresight-etb10.c
+++ b/drivers/coresight/coresight-etb10.c
@@ -22,7 +22,7 @@
 #include <linux/uaccess.h>
 #include <linux/slab.h>
 #include <linux/spinlock.h>
-#include <linux/clk.h>
+#include <linux/pm_runtime.h>
 #include <linux/seq_file.h>
 #include <linux/coresight.h>
 #include <linux/amba/bus.h>
@@ -68,7 +68,6 @@
  * @dev:	the device entity associated to this component.
  * @csdev:	component vitals needed by the framework.
  * @miscdev:	specifics to handle "/dev/xyz.etb" entry.
- * @clk:	the clock this component is associated to.
  * @spinlock:	only one at a time pls.
  * @in_use:	synchronise user space access to etb buffer.
  * @buf:	area of memory where ETB buffer content gets sent.
@@ -81,7 +80,6 @@ struct etb_drvdata {
 	struct device		*dev;
 	struct coresight_device	*csdev;
 	struct miscdevice	miscdev;
-	struct clk		*clk;
 	spinlock_t		spinlock;
 	atomic_t		in_use;
 	u8			*buf;
@@ -92,17 +90,14 @@ struct etb_drvdata {
 
 static unsigned int etb_get_buffer_depth(struct etb_drvdata *drvdata)
 {
-	int ret;
 	u32 depth = 0;
 
-	ret = clk_prepare_enable(drvdata->clk);
-	if (ret)
-		return ret;
+	pm_runtime_get_sync(drvdata->dev);
 
 	/* RO registers don't need locking */
 	depth = readl_relaxed(drvdata->base + ETB_RAM_DEPTH_REG);
 
-	clk_disable_unprepare(drvdata->clk);
+	pm_runtime_put(drvdata->dev);
 	return depth;
 }
 
@@ -137,12 +132,9 @@ static void etb_enable_hw(struct etb_drvdata *drvdata)
 static int etb_enable(struct coresight_device *csdev)
 {
 	struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
-	int ret;
 	unsigned long flags;
 
-	ret = clk_prepare_enable(drvdata->clk);
-	if (ret)
-		return ret;
+	pm_runtime_get_sync(drvdata->dev);
 
 	spin_lock_irqsave(&drvdata->spinlock, flags);
 	etb_enable_hw(drvdata);
@@ -252,7 +244,7 @@ static void etb_disable(struct coresight_device *csdev)
 	drvdata->enable = false;
 	spin_unlock_irqrestore(&drvdata->spinlock, flags);
 
-	clk_disable_unprepare(drvdata->clk);
+	pm_runtime_put(drvdata->dev);
 
 	dev_info(drvdata->dev, "ETB disabled\n");
 }
@@ -339,16 +331,12 @@ static const struct file_operations etb_fops = {
 static ssize_t status_show(struct device *dev,
 			   struct device_attribute *attr, char *buf)
 {
-	int ret;
 	unsigned long flags;
 	u32 etb_rdr, etb_sr, etb_rrp, etb_rwp;
 	u32 etb_trg, etb_cr, etb_ffsr, etb_ffcr;
 	struct etb_drvdata *drvdata = dev_get_drvdata(dev->parent);
 
-	ret = clk_prepare_enable(drvdata->clk);
-	if (ret)
-		goto out;
-
+	pm_runtime_get_sync(drvdata->dev);
 	spin_lock_irqsave(&drvdata->spinlock, flags);
 	CS_UNLOCK(drvdata->base);
 
@@ -364,7 +352,7 @@ static ssize_t status_show(struct device *dev,
 	CS_LOCK(drvdata->base);
 	spin_unlock_irqrestore(&drvdata->spinlock, flags);
 
-	clk_disable_unprepare(drvdata->clk);
+	pm_runtime_put(drvdata->dev);
 
 	return sprintf(buf,
 		       "Depth:\t\t0x%x\n"
@@ -377,7 +365,7 @@ static ssize_t status_show(struct device *dev,
 		       "Flush ctrl:\t0x%x\n",
 		       etb_rdr, etb_sr, etb_rrp, etb_rwp,
 		       etb_trg, etb_cr, etb_ffsr, etb_ffcr);
-out:
+
 	return -EINVAL;
 }
 static DEVICE_ATTR_RO(status);
@@ -449,13 +437,8 @@ static int etb_probe(struct amba_device *adev, const struct amba_id *id)
 
 	spin_lock_init(&drvdata->spinlock);
 
-	drvdata->clk = adev->pclk;
-	ret = clk_prepare_enable(drvdata->clk);
-	if (ret)
-		return ret;
-
 	drvdata->buffer_depth = etb_get_buffer_depth(drvdata);
-	clk_disable_unprepare(drvdata->clk);
+	pm_runtime_put(&adev->dev);
 
 	if (drvdata->buffer_depth < 0)
 		return -EINVAL;
-- 
1.9.3

  parent reply	other threads:[~2015-04-17  8:58 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-04-17  8:58 [PATCH 00/13] Enable CoreSight for the Ux500 Linus Walleij
2015-04-17  8:58 ` [PATCH 01/13] coresight: etm: print what version of ETM/PTM is detected Linus Walleij
2015-04-17  8:58 ` [PATCH 02/13] coresight: support the TPIU version found in Ux500 Linus Walleij
2015-04-17  8:58 ` [PATCH 03/13] coresight: etm: let runtime PM handle core clock Linus Walleij
2015-04-17  9:06   ` Ulf Hansson
2015-04-17  8:58 ` [PATCH 04/13] coresight: tpiu: " Linus Walleij
2015-04-17  9:07   ` Ulf Hansson
2015-04-17  8:58 ` Linus Walleij [this message]
2015-04-17  9:08   ` [PATCH 05/13] coresight: etb: " Ulf Hansson
2015-04-17  8:58 ` [PATCH 06/13] coresight: funnel: " Linus Walleij
2015-04-17  9:09   ` Ulf Hansson
2015-04-17  8:58 ` [PATCH 07/13] coresight: tmc: " Linus Walleij
2015-04-17  9:10   ` Ulf Hansson
2015-04-17  8:58 ` [PATCH 08/13] coresight: etm: retrieve and handle atclk Linus Walleij
2015-04-17  9:18   ` Ulf Hansson
2015-04-17  8:58 ` [PATCH 09/13] coresight: tpiu: " Linus Walleij
2015-04-17  9:20   ` Ulf Hansson
2015-04-17  8:58 ` [PATCH 10/13] coresight: etb: " Linus Walleij
2015-04-17  9:21   ` Ulf Hansson
2015-04-17  8:58 ` [PATCH 11/13] coresight: funnel: " Linus Walleij
2015-04-17  9:21   ` Ulf Hansson
2015-04-17  8:58 ` [PATCH 12/13] coresight: replicator: " Linus Walleij
2015-04-17  9:31   ` Ulf Hansson
2015-04-17  8:59 ` [PATCH 13/13] ARM: ux500: add CoreSight blocks to DTS file Linus Walleij
2015-04-17 15:41   ` Mathieu Poirier
2015-04-17 15:53 ` [PATCH 00/13] Enable CoreSight for the Ux500 Mathieu Poirier
2015-04-24 14:53 ` Ivan T. Ivanov
2015-04-24 15:31   ` Ulf Hansson
2015-04-24 19:40     ` Ivan T. Ivanov

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