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diff for duplicates of <1429522047-16675-2-git-send-email-pi-cheng.chen@linaro.org>

diff --git a/a/1.txt b/N1/1.txt
index 00d9087..9c084ff 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -1,7 +1,7 @@
 This patch implements MT8173 specific cpufreq driver with OPP table defined
 in the driver code.
 
-Signed-off-by: pi-cheng.chen <pi-cheng.chen@linaro.org>
+Signed-off-by: pi-cheng.chen <pi-cheng.chen-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
 ---
  drivers/cpufreq/Kconfig.arm      |   6 +
  drivers/cpufreq/Makefile         |   1 +
@@ -46,7 +46,7 @@ index 0000000..a310e72
 @@ -0,0 +1,509 @@
 +/*
 +* Copyright (c) 2015 Linaro Ltd.
-+* Author: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
++* Author: Pi-Cheng Chen <pi-cheng.chen-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
 +*
 +* This program is free software; you can redistribute it and/or modify
 +* it under the terms of the GNU General Public License version 2 as
@@ -554,4 +554,9 @@ index 0000000..a310e72
 +
 +module_init(mt8173_cpufreq_driver_init);
 -- 
-1.9.1
\ No newline at end of file
+1.9.1
+
+--
+To unsubscribe from this list: send the line "unsubscribe devicetree" in
+the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
+More majordomo info at  http://vger.kernel.org/majordomo-info.html
\ No newline at end of file
diff --git a/a/content_digest b/N1/content_digest
index 991c872..37ebfae 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -2,7 +2,10 @@
   "ref\0001429522047-16675-1-git-send-email-pi-cheng.chen\@linaro.org\0"
 ]
 [
-  "From\0pi-cheng.chen <pi-cheng.chen\@linaro.org>\0"
+  "ref\0001429522047-16675-1-git-send-email-pi-cheng.chen-QSEj5FYQhm4dnm+yROfE0A\@public.gmane.org\0"
+]
+[
+  "From\0pi-cheng.chen <pi-cheng.chen-QSEj5FYQhm4dnm+yROfE0A\@public.gmane.org>\0"
 ]
 [
   "Subject\0[PATCH 1/2] cpufreq: mediatek: Add MT8173 cpufreq driver\0"
@@ -11,22 +14,22 @@
   "Date\0Mon, 20 Apr 2015 17:27:26 +0800\0"
 ]
 [
-  "To\0Viresh Kumar <viresh.kumar\@linaro.org>",
-  " Mike Turquette <mturquette\@linaro.org>",
-  " Matthias Brugger <matthias.bgg\@gmail.com>\0"
+  "To\0Viresh Kumar <viresh.kumar-QSEj5FYQhm4dnm+yROfE0A\@public.gmane.org>",
+  " Mike Turquette <mturquette-QSEj5FYQhm4dnm+yROfE0A\@public.gmane.org>",
+  " Matthias Brugger <matthias.bgg-Re5JQEeQqe8AvxtiuMwx3w\@public.gmane.org>\0"
 ]
 [
-  "Cc\0pi-cheng.chen <pi-cheng.chen\@linaro.org>",
-  " Joe.C <yingjoe.chen\@mediatek.com>",
-  " Eddie Huang <eddie.huang\@mediatek.com>",
-  " Howard Chen <ibanezchen\@gmail.com>",
-  " fan.chen\@mediatek.com",
-  " devicetree\@vger.kernel.org",
-  " linux-arm-kernel\@lists.infradead.org",
-  " linux-kernel\@vger.kernel.org",
-  " linux-pm\@vger.kernel.org",
-  " linaro-kernel\@lists.linaro.org",
-  " linux-mediatek\@lists.infradead.org\0"
+  "Cc\0pi-cheng.chen <pi-cheng.chen-QSEj5FYQhm4dnm+yROfE0A\@public.gmane.org>",
+  " Joe.C <yingjoe.chen-NuS5LvNUpcJWk0Htik3J/w\@public.gmane.org>",
+  " Eddie Huang <eddie.huang-NuS5LvNUpcJWk0Htik3J/w\@public.gmane.org>",
+  " Howard Chen <ibanezchen-Re5JQEeQqe8AvxtiuMwx3w\@public.gmane.org>",
+  " fan.chen-NuS5LvNUpcJWk0Htik3J/w\@public.gmane.org",
+  " devicetree-u79uwXL29TY76Z2rM5mHXA\@public.gmane.org",
+  " linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r\@public.gmane.org",
+  " linux-kernel-u79uwXL29TY76Z2rM5mHXA\@public.gmane.org",
+  " linux-pm-u79uwXL29TY76Z2rM5mHXA\@public.gmane.org",
+  " linaro-kernel-cunTk1MwBs8s++Sfvej+rw\@public.gmane.org",
+  " linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r\@public.gmane.org\0"
 ]
 [
   "\0000:1\0"
@@ -38,7 +41,7 @@
   "This patch implements MT8173 specific cpufreq driver with OPP table defined\n",
   "in the driver code.\n",
   "\n",
-  "Signed-off-by: pi-cheng.chen <pi-cheng.chen\@linaro.org>\n",
+  "Signed-off-by: pi-cheng.chen <pi-cheng.chen-QSEj5FYQhm4dnm+yROfE0A\@public.gmane.org>\n",
   "---\n",
   " drivers/cpufreq/Kconfig.arm      |   6 +\n",
   " drivers/cpufreq/Makefile         |   1 +\n",
@@ -83,7 +86,7 @@
   "\@\@ -0,0 +1,509 \@\@\n",
   "+/*\n",
   "+* Copyright (c) 2015 Linaro Ltd.\n",
-  "+* Author: Pi-Cheng Chen <pi-cheng.chen\@linaro.org>\n",
+  "+* Author: Pi-Cheng Chen <pi-cheng.chen-QSEj5FYQhm4dnm+yROfE0A\@public.gmane.org>\n",
   "+*\n",
   "+* This program is free software; you can redistribute it and/or modify\n",
   "+* it under the terms of the GNU General Public License version 2 as\n",
@@ -591,7 +594,12 @@
   "+\n",
   "+module_init(mt8173_cpufreq_driver_init);\n",
   "-- \n",
-  "1.9.1"
+  "1.9.1\n",
+  "\n",
+  "--\n",
+  "To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n",
+  "the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA\@public.gmane.org\n",
+  "More majordomo info at  http://vger.kernel.org/majordomo-info.html"
 ]
 
-ce455205a148bdd0850e1386d423e49c43eb5c360ec2b2d02454497c5de0e43a
+060bf5efdc411b6c88cb813ed82ab30def8c30fe66e3a02310206da213026af7

diff --git a/a/1.txt b/N2/1.txt
index 00d9087..f7872d9 100644
--- a/a/1.txt
+++ b/N2/1.txt
@@ -91,7 +91,7 @@ index 0000000..a310e72
 + * hardware limitation: 100mV < Vsram - Vproc < 200mV
 + * When scaling up/down the clock frequency of a cluster, the clock source need
 + * to be switched to another stable PLL clock temporarily, and switched back to
-+ * the original PLL after the it becomes stable at target frequency.
++ * the original PLL after the it becomes stable@target frequency.
 + * Hence the voltage inputs of cluster need to be set to an intermediate voltage
 + * before the clock frequency being scaled up/down.
 + */
diff --git a/a/content_digest b/N2/content_digest
index 991c872..751878c 100644
--- a/a/content_digest
+++ b/N2/content_digest
@@ -2,7 +2,7 @@
   "ref\0001429522047-16675-1-git-send-email-pi-cheng.chen\@linaro.org\0"
 ]
 [
-  "From\0pi-cheng.chen <pi-cheng.chen\@linaro.org>\0"
+  "From\0pi-cheng.chen\@linaro.org (pi-cheng.chen)\0"
 ]
 [
   "Subject\0[PATCH 1/2] cpufreq: mediatek: Add MT8173 cpufreq driver\0"
@@ -11,22 +11,7 @@
   "Date\0Mon, 20 Apr 2015 17:27:26 +0800\0"
 ]
 [
-  "To\0Viresh Kumar <viresh.kumar\@linaro.org>",
-  " Mike Turquette <mturquette\@linaro.org>",
-  " Matthias Brugger <matthias.bgg\@gmail.com>\0"
-]
-[
-  "Cc\0pi-cheng.chen <pi-cheng.chen\@linaro.org>",
-  " Joe.C <yingjoe.chen\@mediatek.com>",
-  " Eddie Huang <eddie.huang\@mediatek.com>",
-  " Howard Chen <ibanezchen\@gmail.com>",
-  " fan.chen\@mediatek.com",
-  " devicetree\@vger.kernel.org",
-  " linux-arm-kernel\@lists.infradead.org",
-  " linux-kernel\@vger.kernel.org",
-  " linux-pm\@vger.kernel.org",
-  " linaro-kernel\@lists.linaro.org",
-  " linux-mediatek\@lists.infradead.org\0"
+  "To\0linux-arm-kernel\@lists.infradead.org\0"
 ]
 [
   "\0000:1\0"
@@ -128,7 +113,7 @@
   "+ * hardware limitation: 100mV < Vsram - Vproc < 200mV\n",
   "+ * When scaling up/down the clock frequency of a cluster, the clock source need\n",
   "+ * to be switched to another stable PLL clock temporarily, and switched back to\n",
-  "+ * the original PLL after the it becomes stable at target frequency.\n",
+  "+ * the original PLL after the it becomes stable\@target frequency.\n",
   "+ * Hence the voltage inputs of cluster need to be set to an intermediate voltage\n",
   "+ * before the clock frequency being scaled up/down.\n",
   "+ */\n",
@@ -594,4 +579,4 @@
   "1.9.1"
 ]
 
-ce455205a148bdd0850e1386d423e49c43eb5c360ec2b2d02454497c5de0e43a
+cf78e54ea1b6dfbc854c85662c023ec72d679b263218988deeddccd74fb27316

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