From mboxrd@z Thu Jan 1 00:00:00 1970 From: Helin Zhang Subject: [PATCH v2 02/33] i40e: disable setting of phy configuration Date: Thu, 30 Apr 2015 23:03:08 +0800 Message-ID: <1430406219-23901-3-git-send-email-helin.zhang@intel.com> References: <1429518150-28098-1-git-send-email-helin.zhang@intel.com> <1430406219-23901-1-git-send-email-helin.zhang@intel.com> Cc: monica.kenguva-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org, steven.j.murray-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org, shannon.nelson-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org To: dev-VfR2kkLFssw@public.gmane.org Return-path: In-Reply-To: <1430406219-23901-1-git-send-email-helin.zhang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org> List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces-VfR2kkLFssw@public.gmane.org Sender: "dev" There was a known link issue on 40G ports on NVM version (FVL3E), when setting phy configuration. As a workaround, setting of phy configuration should be disabled. The impact is that the link cannot be forcedly configured, which doesn't affect any feature functions. The workaround can be removed when a formal fix is ready later. Signed-off-by: Helin Zhang --- lib/librte_pmd_i40e/i40e_ethdev.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/lib/librte_pmd_i40e/i40e_ethdev.c b/lib/librte_pmd_i40e/i40e_ethdev.c index 40c90d7..49d1067 100644 --- a/lib/librte_pmd_i40e/i40e_ethdev.c +++ b/lib/librte_pmd_i40e/i40e_ethdev.c @@ -791,6 +791,10 @@ i40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed) I40E_LINK_SPEED_100MB; int ret = -ENOTSUP; + /* Skip it on 40G interfaces, as a workaround for the link issue */ + if (i40e_is_40G_device(hw->device_id)) + return I40E_SUCCESS; + status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab, NULL); if (status) -- 1.8.1.4