From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965581AbbEERr0 (ORCPT ); Tue, 5 May 2015 13:47:26 -0400 Received: from mail-bl2on0127.outbound.protection.outlook.com ([65.55.169.127]:27344 "EHLO na01-bl2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S965520AbbEERrU (ORCPT ); Tue, 5 May 2015 13:47:20 -0400 Authentication-Results: spf=fail (sender IP is 192.88.158.2) smtp.mailfrom=freescale.com; freescale.mail.onmicrosoft.com; dkim=none (message not signed) header.d=none; From: Ramneek Mehresh To: CC: , , , , Ramneek Mehresh , Shengzhou Liu Subject: [PATCH 1/9] usb:fsl:otg: Add controller version based ULPI and UTMI phy Date: Tue, 5 May 2015 23:28:28 +0530 Message-ID: <1430848716-32157-1-git-send-email-ramneek.mehresh@freescale.com> X-Mailer: git-send-email 1.8.3.1 X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.158.2;CTRY:US;IPV:NLI;EFV:NLI;SFV:NSPM;SFS:(10019020)(6009001)(339900001)(189002)(199003)(6806004)(106466001)(48376002)(92566002)(33646002)(575784001)(229853001)(19580395003)(86362001)(2351001)(77096005)(77156002)(47776003)(107886002)(46102003)(105606002)(110136002)(87936001)(50986999)(85426001)(5001960100002)(62966003)(104016003)(36756003)(19580405001)(50466002)(50226001)(76506005)(42866002)(4001430100001);DIR:OUT;SFP:1102;SCL:1;SRVR:BLUPR03MB389;H:az84smr01.freescale.net;FPR:;SPF:Fail;MLV:sfv;MX:1;A:1;LANG:en; MIME-Version: 1.0 Content-Type: text/plain X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BLUPR03MB389; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:(601004)(5005006)(3002001);SRVR:BLUPR03MB389;BCL:0;PCL:0;RULEID:;SRVR:BLUPR03MB389; X-Forefront-PRVS: 0567A15835 X-OriginatorOrg: freescale.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 May 2015 17:47:17.2349 (UTC) X-MS-Exchange-CrossTenant-Id: 710a03f5-10f6-4d38-9ff4-a80b81da590d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=710a03f5-10f6-4d38-9ff4-a80b81da590d;Ip=[192.88.158.2];Helo=[az84smr01.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BLUPR03MB389 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add controller version based ULPI and UTMI phy initialization for otg driver Signed-off-by: Shengzhou Liu Signed-off-by: Ramneek Mehresh Reviewed-by: Fleming Andrew-AFLEMING Tested-by: Fleming Andrew-AFLEMING --- drivers/usb/phy/phy-fsl-usb.c | 20 ++++++++++++++++++++ drivers/usb/phy/phy-fsl-usb.h | 7 +++++++ 2 files changed, 27 insertions(+) diff --git a/drivers/usb/phy/phy-fsl-usb.c b/drivers/usb/phy/phy-fsl-usb.c index 94eb292..f90093a 100644 --- a/drivers/usb/phy/phy-fsl-usb.c +++ b/drivers/usb/phy/phy-fsl-usb.c @@ -923,12 +923,32 @@ int usb_otg_start(struct platform_device *pdev) temp &= ~(PORTSC_PHY_TYPE_SEL | PORTSC_PTW); switch (pdata->phy_mode) { case FSL_USB2_PHY_ULPI: + if (pdata->controller_ver) { + /* controller version 1.6 or above */ + setbits32(&p_otg->dr_mem_map->control, + USB_CTRL_ULPI_PHY_CLK_SEL); + /* + * Due to controller issue of PHY_CLK_VALID in ULPI + * mode, we set USB_CTRL_USB_EN before checking + * PHY_CLK_VALID, otherwise PHY_CLK_VALID doesn't work. + */ + clrsetbits_be32(&p_otg->dr_mem_map->control, + USB_CTRL_UTMI_PHY_EN, USB_CTRL_IOENB); + } temp |= PORTSC_PTS_ULPI; break; case FSL_USB2_PHY_UTMI_WIDE: temp |= PORTSC_PTW_16BIT; /* fall through */ case FSL_USB2_PHY_UTMI: + if (pdata->controller_ver) { + /* controller version 1.6 or above */ + setbits32(&p_otg->dr_mem_map->control, + USB_CTRL_UTMI_PHY_EN); + /* Delay for UTMI PHY CLK to become stable - 10ms */ + mdelay(FSL_UTMI_PHY_DLY); + } + setbits32(&p_otg->dr_mem_map->control, USB_CTRL_UTMI_PHY_EN); temp |= PORTSC_PTS_UTMI; /* fall through */ default: diff --git a/drivers/usb/phy/phy-fsl-usb.h b/drivers/usb/phy/phy-fsl-usb.h index 2314995..4a78fb3 100644 --- a/drivers/usb/phy/phy-fsl-usb.h +++ b/drivers/usb/phy/phy-fsl-usb.h @@ -199,6 +199,13 @@ /* control Register Bit Masks */ #define USB_CTRL_IOENB (0x1<<2) #define USB_CTRL_ULPI_INT0EN (0x1<<0) +#define USB_CTRL_WU_INT_EN (0x1<<1) +#define USB_CTRL_LINE_STATE_FILTER__EN (0x1<<3) +#define USB_CTRL_KEEP_OTG_ON (0x1<<4) +#define USB_CTRL_OTG_PORT (0x1<<5) +#define USB_CTRL_PLL_RESET (0x1<<8) +#define USB_CTRL_UTMI_PHY_EN (0x1<<9) +#define USB_CTRL_ULPI_PHY_CLK_SEL (0x1<<10) /* BCSR5 */ #define BCSR5_INT_USB (0x02) -- 1.8.3.1