From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47932) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YpzwU-0004AN-GH for qemu-devel@nongnu.org; Wed, 06 May 2015 10:04:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YpzwO-0002cT-8p for qemu-devel@nongnu.org; Wed, 06 May 2015 10:04:54 -0400 Received: from mail-wi0-x229.google.com ([2a00:1450:400c:c05::229]:36984) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YpzwO-0002cE-1n for qemu-devel@nongnu.org; Wed, 06 May 2015 10:04:48 -0400 Received: by widdi4 with SMTP id di4so23783768wid.0 for ; Wed, 06 May 2015 07:04:47 -0700 (PDT) From: shlomopongratz@gmail.com Date: Wed, 6 May 2015 17:04:38 +0300 Message-Id: <1430921082-16779-1-git-send-email-shlomopongratz@gmail.com> Subject: [Qemu-devel] [PATCH RFC V2 0/4] Implement GIC-500 from GICv3 family for arm64 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, Shlomo Pongratz From: Shlomo Pongratz This patch is a first step toward 128 cores support for arm64. At first only 64 cores are supported for two reasons: First the largest integer type has the size of 64 bits and modifying essential data structures in order to support 128 cores will require the usage of bitops. Second currently the Linux (kernel) can be configured to support up to 64 cores thus there is no urgency with 128 cores support. Things left to do: Currently the booting Linux may got stuck. The probability of getting stuck increases with the number of cores. I'll appreciate core review. There is a need to support flexible clusters size. The GIC-500 can support up to 128 cores, up to 32 clusters and up to 8 cores is a cluster. So for example, if one wishes to have 16 cores, the options are: 2 clusters of 8 cores each, 4 clusters with 4 cores each Currently only the first option is supported. There is an issue of passing clock affinity to via the dtb. In the dtb interrupt section there are only 24 bit left to affinity since the variable is a 32 bit entity and 8 bits are reserved for flags. See Documentation/devicetree/bindings/arm/arch_timer.txt. Note that this issue is not seems to be critical as when checking /proc/irq/3/smp_affinity with 32 cores all 32 bits are one. The last issue is to add support for 128 cores. This requires the usage of bitops and currently can be tested up to 64 cores. V2: - Split the original patch to 4 patches - Add SRE API to the GIC code. - Add call to gicv3_update to armv8_gicv3_set_priority_mask. - Cosmetic changes. - Fix number of irq when reading GICD_TYPER. Shlomo Pongratz (4): Use Aff1 with mpidr Implment GIC-500 GICv3 support Add virtv2 machine that uses GIC-500 hw/arm/Makefile.objs | 2 +- hw/arm/virtv2.c | 774 +++++++++++++++++ hw/intc/Makefile.objs | 2 + hw/intc/arm_gicv3.c | 1626 ++++++++++++++++++++++++++++++++++++ hw/intc/arm_gicv3_common.c | 199 +++++ hw/intc/gicv3_internal.h | 151 ++++ include/hw/intc/arm_gicv3.h | 44 + include/hw/intc/arm_gicv3_common.h | 110 +++ target-arm/cpu.h | 8 + target-arm/cpu64.c | 84 ++ target-arm/helper.c | 12 +- target-arm/psci.c | 18 +- 12 files changed, 3025 insertions(+), 5 deletions(-) create mode 100644 hw/arm/virtv2.c create mode 100644 hw/intc/arm_gicv3.c create mode 100644 hw/intc/arm_gicv3_common.c create mode 100644 hw/intc/gicv3_internal.h create mode 100644 include/hw/intc/arm_gicv3.h create mode 100644 include/hw/intc/arm_gicv3_common.h -- 1.9.1