[Qemu-devel] [PULL 0/5] tricore-patches

[Qemu-devel] [PULL 0/5] tricore-patches

[Bastian Koppelmann]

The following changes since commit ec62ad1e27ffd1f7ff2172a916d161cc385e73bd:

  Merge remote-tracking branch 'remotes/kraxel/tags/pull-gtk-20150508-1' into staging (2015-05-11 10:43:08 +0100)

are available in the git repository at:

  https://github.com/bkoppelmann/qemu-tricore-upstream.git tags/pull-tricore-20150511

for you to fetch changes up to 3446a11181c6e8263dbd9c13c28986df4317099e:

  target-tricore: fix rfe not restoring the PC (2015-05-11 14:25:49 +0200)

----------------------------------------------------------------
TriCore bugfixes

----------------------------------------------------------------
Bastian Koppelmann (5):
      target-tricore: Fix LOOP using wrong register for compare
      target-tricore: fix SLR_LD_W and SLR_LD_W_POSTINC insn being a 2 byte memory access insted of 4
      target-tricore: fix BO_OFF10_SEXT calculating the wrong offset
      target-tricore: fix rslcx restoring the upper context instead of the lower
      target-tricore: fix rfe not restoring the PC

 target-tricore/op_helper.c       | 3 ++-
 target-tricore/translate.c       | 6 +++---
 target-tricore/tricore-opcodes.h | 2 +-
 3 files changed, 6 insertions(+), 5 deletions(-)
-- 
2.4.0

[Qemu-devel] [PULL 1/5] target-tricore: Fix LOOP using wrong register for compare

[Bastian Koppelmann]

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
 target-tricore/translate.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 54a48cd..d2cd640 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -3440,7 +3440,7 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1,
         break;
     case OPCM_32_BRR_LOOP:
         if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_LOOP) {
-            gen_loop(ctx, r1, offset * 2);
+            gen_loop(ctx, r2, offset * 2);
         } else {
             /* OPC2_32_BRR_LOOPU */
             gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
-- 
2.4.0

[Qemu-devel] [PULL 2/5] target-tricore: fix SLR_LD_W and SLR_LD_W_POSTINC insn being a 2 byte memory access insted of 4

[Bastian Koppelmann]

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
 target-tricore/translate.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index d2cd640..663b2a0 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -3745,10 +3745,10 @@ static void decode_slr_opc(DisasContext *ctx, int op1)
         tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2);
         break;
     case OPC1_16_SLR_LD_W:
-        tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
+        tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
         break;
     case OPC1_16_SLR_LD_W_POSTINC:
-        tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
+        tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
         tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
         break;
     }
-- 
2.4.0

[Qemu-devel] [PULL 3/5] target-tricore: fix BO_OFF10_SEXT calculating the wrong offset

[Bastian Koppelmann]

The lower part of the combined offset was sign extended and could lead to
wrong results.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
 target-tricore/tricore-opcodes.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target-tricore/tricore-opcodes.h b/target-tricore/tricore-opcodes.h
index d3a9bc1..2291f75 100644
--- a/target-tricore/tricore-opcodes.h
+++ b/target-tricore/tricore-opcodes.h
@@ -107,7 +107,7 @@
 /* BO Format */
 #define MASK_OP_BO_OFF10(op)   (MASK_BITS_SHIFT(op, 16, 21) + \
                                (MASK_BITS_SHIFT(op, 28, 31) << 6))
-#define MASK_OP_BO_OFF10_SEXT(op)   (MASK_BITS_SHIFT_SEXT(op, 16, 21) + \
+#define MASK_OP_BO_OFF10_SEXT(op)   (MASK_BITS_SHIFT(op, 16, 21) + \
                                     (MASK_BITS_SHIFT_SEXT(op, 28, 31) << 6))
 #define MASK_OP_BO_OP2(op)     MASK_BITS_SHIFT(op, 22, 27)
 #define MASK_OP_BO_S2(op)      MASK_BITS_SHIFT(op, 12, 15)
-- 
2.4.0

[Qemu-devel] [PULL 4/5] target-tricore: fix rslcx restoring the upper context instead of the lower

[Bastian Koppelmann]

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
Note here, that I swaped the attributes here as compared to the patch on the list, since this was wrong.

 target-tricore/op_helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target-tricore/op_helper.c b/target-tricore/op_helper.c
index 9907e07..1dc25c2 100644
--- a/target-tricore/op_helper.c
+++ b/target-tricore/op_helper.c
@@ -2581,7 +2581,7 @@ void helper_rslcx(CPUTriCoreState *env)
          ((env->PCXI & MASK_PCXI_PCXO) << 6);
     /* {new_PCXI, A[11], A[10], A[11], D[8], D[9], D[10], D[11], A[12],
         A[13], A[14], A[15], D[12], D[13], D[14], D[15]} = M(EA, 16 * word); */
-    restore_context_upper(env, ea, &new_PCXI, &env->gpr_a[11]);
+    restore_context_lower(env, ea, &env->gpr_a[11], &new_PCXI);
     /* M(EA, word) = FCX; */
     cpu_stl_data(env, ea, env->FCX);
     /* M(EA, word) = FCX; */
-- 
2.4.0

[Qemu-devel] [PULL 5/5] target-tricore: fix rfe not restoring the PC

[Bastian Koppelmann]

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
 target-tricore/op_helper.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target-tricore/op_helper.c b/target-tricore/op_helper.c
index 1dc25c2..9919b5b 100644
--- a/target-tricore/op_helper.c
+++ b/target-tricore/op_helper.c
@@ -2458,6 +2458,7 @@ void helper_rfe(CPUTriCoreState *env)
     if (!cdc_zero(&(env->PSW)) && (env->PSW & MASK_PSW_CDE)) {
         /* raise MNG trap */
     }
+    env->PC = env->gpr_a[11] & ~0x1;
     /* ICR.IE = PCXI.PIE; */
     env->ICR = (env->ICR & ~MASK_ICR_IE) + ((env->PCXI & MASK_PCXI_PIE) >> 15);
     /* ICR.CCPN = PCXI.PCPN; */
-- 
2.4.0

Re: [Qemu-devel] [PULL 0/5] tricore-patches

[Peter Maydell]

On 11 May 2015 at 13:30, Bastian Koppelmann
<kbastian@mail.uni-paderborn.de> wrote:
> The following changes since commit ec62ad1e27ffd1f7ff2172a916d161cc385e73bd:
>
>   Merge remote-tracking branch 'remotes/kraxel/tags/pull-gtk-20150508-1' into staging (2015-05-11 10:43:08 +0100)
>
> are available in the git repository at:
>
>   https://github.com/bkoppelmann/qemu-tricore-upstream.git tags/pull-tricore-20150511
>
> for you to fetch changes up to 3446a11181c6e8263dbd9c13c28986df4317099e:
>
>   target-tricore: fix rfe not restoring the PC (2015-05-11 14:25:49 +0200)
>
> ----------------------------------------------------------------
> TriCore bugfixes
>

Applied, thanks.

-- PMM

Re: [Qemu-devel] [PULL 0/5] tricore-patches

[Peter Maydell]

On 11 January 2017 at 13:45, Bastian Koppelmann
<kbastian@mail.uni-paderborn.de> wrote:
> The following changes since commit 50788a3fdbade5f8ed1c8296988578133c52c6aa:
>
>   target-tricore: Add updfl instruction (2017-01-11 14:37:37 +0100)
>
> are available in the git repository at:
>
>   https://github.com/bkoppelmann/qemu-tricore-upstream.git tags/pull-tricore-2017-01-11-2
>
> for you to fetch changes up to 50788a3fdbade5f8ed1c8296988578133c52c6aa:
>
>   target-tricore: Add updfl instruction (2017-01-11 14:37:37 +0100)
>
> ----------------------------------------------------------------
> TriCore FPU patches
>
> ----------------------------------------------------------------
>
> Bastian Koppelmann (3):
>   target-tricore: Added FTOUZ instruction
>   target-tricore: Added MADD.F and MSUB.F instructions
>   target-tricore: Add updfl instruction
>
> Peer Adelt (2):
>   target-tricore: Added new MOV instruction variant
>   target-tricore: Added new JNE instruction variant
>
>  target/tricore/fpu_helper.c      | 134 ++++++++++++++++++++++++++++++++++++++-
>  target/tricore/helper.h          |   4 ++
>  target/tricore/translate.c       |  48 ++++++++++++++
>  target/tricore/tricore-opcodes.h |   3 +
>  4 files changed, 188 insertions(+), 1 deletion(-)

Applied, thanks.

-- PMM

[Qemu-devel] [PULL 0/5] tricore-patches

[Bastian Koppelmann]

The following changes since commit 50788a3fdbade5f8ed1c8296988578133c52c6aa:
                                                                                                                                                                                                                                                                                  
  target-tricore: Add updfl instruction (2017-01-11 14:37:37 +0100)

are available in the git repository at: 

  https://github.com/bkoppelmann/qemu-tricore-upstream.git tags/pull-tricore-2017-01-11-2

for you to fetch changes up to 50788a3fdbade5f8ed1c8296988578133c52c6aa:

  target-tricore: Add updfl instruction (2017-01-11 14:37:37 +0100)

----------------------------------------------------------------
TriCore FPU patches

----------------------------------------------------------------

Bastian Koppelmann (3):
  target-tricore: Added FTOUZ instruction
  target-tricore: Added MADD.F and MSUB.F instructions
  target-tricore: Add updfl instruction

Peer Adelt (2):
  target-tricore: Added new MOV instruction variant
  target-tricore: Added new JNE instruction variant

 target/tricore/fpu_helper.c      | 134 ++++++++++++++++++++++++++++++++++++++-
 target/tricore/helper.h          |   4 ++
 target/tricore/translate.c       |  48 ++++++++++++++
 target/tricore/tricore-opcodes.h |   3 +
 4 files changed, 188 insertions(+), 1 deletion(-)

-- 
2.11.0