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From: Rhyland Klein <rklein@nvidia.com>
To: Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: Mike Turquette <mturquette@linaro.org>,
	Stephen Warren <swarren@wwwdotorg.org>,
	Stephen Boyd <sboyd@codeaurora.org>,
	Thierry Reding <thierry.reding@gmail.com>,
	Alexandre Courbot <gnurou@gmail.com>,
	Bill Huang <bilhuang@nvidia.com>,
	Paul Walmsley <pwalmsley@nvidia.com>, Jim Lin <jilin@nvidia.com>,
	Benson Leung <bleung@chromium.org>,
	linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org,
	linux-kernel@vger.kernel.org, Rhyland Klein <rklein@nvidia.com>
Subject: [PATCH v5 04/21] clk: tegra: pll: add tegra_pll_wait_for_lock to clk header
Date: Tue, 12 May 2015 13:23:47 -0400	[thread overview]
Message-ID: <1431451444-23155-6-git-send-email-rklein@nvidia.com> (raw)
In-Reply-To: <1431451444-23155-1-git-send-email-rklein@nvidia.com>

Create a wrapper interface to make use of the existing
clk_pll_wait_for_lock. This will be useful for implementations
of callbacks in Tegra SoC specific clock drivers.

Signed-off-by: Rhyland Klein <rklein@nvidia.com>
---
 drivers/clk/tegra/clk-pll.c |    5 +++++
 drivers/clk/tegra/clk.h     |    1 +
 2 files changed, 6 insertions(+)

diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 05c6d08a6695..b9a739ce4b98 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -269,6 +269,11 @@ static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll)
 	return -1;
 }
 
+int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll)
+{
+	return clk_pll_wait_for_lock(pll);
+}
+
 static int clk_pll_is_enabled(struct clk_hw *hw)
 {
 	struct tegra_clk_pll *pll = to_clk_pll(hw);
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index 4a37a0d38624..2c60319a886f 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -659,5 +659,6 @@ void tegra114_clock_deassert_dfll_dvco_reset(void);
 
 typedef void (*tegra_clk_apply_init_table_func)(void);
 extern tegra_clk_apply_init_table_func tegra_clk_apply_init_table;
+int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll);
 
 #endif /* TEGRA_CLK_H */
-- 
1.7.9.5

  reply	other threads:[~2015-05-12 17:23 UTC|newest]

Thread overview: 74+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-05-12 17:23 [PATCH v5 00/21] Tegra210 Clock Support Rhyland Klein
2015-05-12 17:23 ` Rhyland Klein
2015-05-12 17:23 ` Rhyland Klein [this message]
2015-05-12 21:52   ` [PATCH v5 04/21] clk: tegra: pll: add tegra_pll_wait_for_lock to clk header Benson Leung
2015-05-12 17:23 ` [PATCH v5 05/21] clk: tegra: pll: simplify clk_enable_path Rhyland Klein
2015-05-12 17:23 ` [PATCH v5 06/21] clk: tegra: pll: update warning msg Rhyland Klein
     [not found] ` <1431451444-23155-1-git-send-email-rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-05-12 17:23   ` [PATCH v5 01/21] clk: tegra: Update struct tegra_clk_pll_params kerneldoc Rhyland Klein
2015-05-12 17:23     ` Rhyland Klein
2015-05-12 17:23   ` [PATCH v5 01/21] FROMLIST: " Rhyland Klein
2015-05-12 17:23     ` Rhyland Klein
2015-05-12 17:23   ` [PATCH v5 02/21] clk: tegra: Modify tegra_audio_clk_init to accept more plls Rhyland Klein
2015-05-12 17:23     ` Rhyland Klein
2015-05-12 17:23   ` [PATCH v5 03/21] clk: tegra: periph: add new periph clks and muxes for Tegra210 Rhyland Klein
2015-05-12 17:23     ` Rhyland Klein
2015-05-12 17:23   ` [PATCH v5 07/21] clk: tegra: pll-params: change misc_reg count from 3 -> 6 Rhyland Klein
2015-05-12 17:23     ` Rhyland Klein
2015-05-12 17:23   ` [PATCH v5 10/21] clk: tegra: pll: Add logic for out-of-table rates for T210 Rhyland Klein
2015-05-12 17:23     ` Rhyland Klein
     [not found]     ` <1431451444-23155-12-git-send-email-rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-05-13  0:01       ` Benson Leung
2015-05-13  0:01         ` Benson Leung
2015-05-12 17:23   ` [PATCH v5 13/21] clk: tegra: pll: Add support for PLLMB " Rhyland Klein
2015-05-12 17:23     ` Rhyland Klein
     [not found]     ` <1431451444-23155-15-git-send-email-rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-05-13 22:04       ` Benson Leung
2015-05-13 22:04         ` Benson Leung
2015-05-12 17:23   ` [PATCH v5 15/21] clk: tegra: pll: Add dyn_ramp callback Rhyland Klein
2015-05-12 17:23     ` Rhyland Klein
     [not found]     ` <1431451444-23155-17-git-send-email-rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-05-13 22:20       ` Benson Leung
2015-05-13 22:20         ` Benson Leung
2015-05-12 17:24   ` [PATCH v5 20/21] clk: tegra210: add support for Tegra210 clocks Rhyland Klein
2015-05-12 17:24     ` Rhyland Klein
2015-05-14 20:23     ` Benson Leung
2015-05-20 17:17       ` Rhyland Klein
2015-05-20 17:17         ` Rhyland Klein
     [not found]     ` <1431451444-23155-22-git-send-email-rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-05-20  9:47       ` Jim Lin
2015-05-20  9:47         ` Jim Lin
     [not found]         ` <555C582A.7050508-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-05-20 17:16           ` Rhyland Klein
2015-05-20 17:16             ` Rhyland Klein
2015-05-12 17:23 ` [PATCH v5 08/21] clk: tegra: pll: Don't unconditionally set LOCK flags Rhyland Klein
2015-05-12 17:23 ` [PATCH v5 09/21] clk: tegra: pll: Add logic for handling SDM data Rhyland Klein
     [not found]   ` <1431451444-23155-11-git-send-email-rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-05-18 22:35     ` Benson Leung
2015-05-18 22:35       ` Benson Leung
2015-05-12 17:23 ` [PATCH v5 11/21] clk: tegra: pll: Add code to handle if resets are supported by PLL Rhyland Klein
2015-05-12 17:23 ` [PATCH v5 12/21] clk: tegra: pll: Add specialized logic for T210 Rhyland Klein
     [not found]   ` <1431451444-23155-14-git-send-email-rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-05-13 20:59     ` Benson Leung
2015-05-13 20:59       ` Benson Leung
     [not found]       ` <CANLzEkuqCB+wF65MrtWwnsgTDhw0T9Vae9C5sBALGDbPvwrr_w-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2015-05-20 17:24         ` Rhyland Klein
2015-05-20 17:24           ` Rhyland Klein
     [not found]           ` <555CC357.5090105-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-05-20 17:26             ` Benson Leung
2015-05-20 17:26               ` Benson Leung
2015-05-12 17:23 ` [PATCH v5 14/21] clk: tegra: pll: Adjust vco_min if SDM present Rhyland Klein
     [not found]   ` <1431451444-23155-16-git-send-email-rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-05-13 22:11     ` Benson Leung
2015-05-13 22:11       ` Benson Leung
2015-06-04 18:52     ` Stephen Boyd
2015-06-04 18:52       ` Stephen Boyd
2015-05-12 17:23 ` [PATCH v5 16/21] clk: tegra: pll: Add Set_default logic Rhyland Klein
2015-05-14  0:04   ` Benson Leung
2015-05-20 17:20     ` Rhyland Klein
2015-05-20 17:20       ` Rhyland Klein
2015-05-12 17:24 ` [PATCH v5 17/21] clk: tegra: pll: Add logic for SS Rhyland Klein
2015-05-14  0:25   ` Benson Leung
     [not found]     ` <CANLzEks10KmCAx4tK0oSejJ6Z+oBRS2+pcsktvStQrogCarTJQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2015-05-20 17:19       ` Rhyland Klein
2015-05-20 17:19         ` Rhyland Klein
2015-05-12 17:24 ` [PATCH v5 18/21] clk: tegra: pll: Fix _pll_ramp_calc_pll logic and _calc_dynamic_ramp_rate Rhyland Klein
     [not found]   ` <1431451444-23155-20-git-send-email-rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-05-14  0:29     ` Benson Leung
2015-05-14  0:29       ` Benson Leung
2015-05-12 17:24 ` [PATCH v5 19/21] clk: tegra: Add Super Gen5 Logic Rhyland Klein
2015-05-13 20:36   ` Benson Leung
2015-05-14 19:37   ` Benson Leung
     [not found]     ` <CANLzEkvUAhXCCvtdHEfmJGONkzNu_dBHj1UUm6Et93kXV1Mz0g-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2015-05-25  8:19       ` Bill Huang
2015-05-25  8:19         ` Bill Huang
2015-05-25  8:19         ` Bill Huang
2015-05-12 17:24 ` [PATCH v5 21/21] clk: tegra: pll: Fix issues with rates for VCO PLLs Rhyland Klein
     [not found]   ` <1431451444-23155-23-git-send-email-rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-05-14 20:02     ` Benson Leung
2015-05-14 20:02       ` Benson Leung

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