From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42446) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YsYje-0001tQ-3I for qemu-devel@nongnu.org; Wed, 13 May 2015 11:38:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YsYjZ-0002m9-HO for qemu-devel@nongnu.org; Wed, 13 May 2015 11:38:14 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:15727) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YsYjZ-0002lK-BT for qemu-devel@nongnu.org; Wed, 13 May 2015 11:38:09 -0400 From: Yongbok Kim Date: Wed, 13 May 2015 16:37:36 +0100 Message-ID: <1431531457-17127-2-git-send-email-yongbok.kim@imgtec.com> In-Reply-To: <1431531457-17127-1-git-send-email-yongbok.kim@imgtec.com> References: <1431531457-17127-1-git-send-email-yongbok.kim@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH v3 1/2] target-mips: Misaligned memory accesses for R6 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, leon.alrae@imgtec.com, afaerber@suse.de, rth@twiddle.net Release 6 requires misaligned memory access support for all ordinary memo= ry access instructions (for example, LW/SW, LWC1/SWC1). However misaligned support is not provided for certain special memory acc= esses such as atomics (for example, LL/SC). Allows misaligned accesses from mips_cpu_do_unaligned_access() callback, if it is a R6 core. As the helper functions of LL/SC is checking misalign= ment, just allowing all for R6 is good enough. Signed-off-by: Yongbok Kim Reviewed-by: Andreas F=C3=A4rber --- target-mips/op_helper.c | 7 +++++++ target-mips/translate_init.c | 2 +- 2 files changed, 8 insertions(+), 1 deletions(-) diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index 73a8e45..58f02cf 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -2215,6 +2215,13 @@ void mips_cpu_do_unaligned_access(CPUState *cs, va= ddr addr, int error_code =3D 0; int excp; =20 + if (env->insn_flags & ISA_MIPS32R6) { + /* Release 6 provides support for misaligned memory access for + * all ordinary memory reference instructions + * */ + return; + } + env->CP0_BadVAddr =3D addr; =20 if (access_type =3D=3D MMU_DATA_STORE) { diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index 85a65e7..ec54fef 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -607,7 +607,7 @@ static const mips_def_t mips_defs[] =3D }, { /* A generic CPU supporting MIPS64 Release 6 ISA. - FIXME: Support IEEE 754-2008 FP and misaligned memory accesse= s. + FIXME: Support IEEE 754-2008 FP. Eventually this should be replaced by a real CPU model= . */ .name =3D "MIPS64R6-generic", .CP0_PRid =3D 0x00010000, --=20 1.7.5.4