From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42547) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YuQVt-0001fD-2l for qemu-devel@nongnu.org; Mon, 18 May 2015 15:15:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YuQVr-0000BS-Qy for qemu-devel@nongnu.org; Mon, 18 May 2015 15:15:44 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:34173) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YuQVr-0008QT-6u for qemu-devel@nongnu.org; Mon, 18 May 2015 15:15:43 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1YuQVV-0007u2-3g for qemu-devel@nongnu.org; Mon, 18 May 2015 20:15:21 +0100 From: Peter Maydell Date: Mon, 18 May 2015 20:15:00 +0100 Message-Id: <1431976521-30352-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PULL 00/21] target-arm queue List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org target-arm queue: mostly the new Xilinx board, plus a handful of other minor things. -- PMM The following changes since commit 385057cbec9b4a0eb6150330c572e875ed714965: Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2015-05-15' into staging (2015-05-15 17:51:20 +0100) are available in the git repository at: git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20150518-3 for you to fetch changes up to 18084b2f71b22b3ec3bf4828b8cb83d1d39e8502: target-arm: Remove unneeded '+' (2015-05-18 20:04:19 +0100) ---------------------------------------------------------------- target-arm: * New board model: xlnx-ep108 * Some more preparation for AArch64 EL2/EL3 * Fix bugs in access checking for generic counter registers * Remove a stray '+' sign ---------------------------------------------------------------- Edgar E. Iglesias (3): target-arm: Correct accessfn for CNTP_{CT}VAL_EL0 target-arm: Correct accessfn for CNTV_TVAL_EL0 target-arm: Remove unneeded '+' Greg Bellows (3): target-arm: Add TTBR regime function and use target-arm: Add EL3 and EL2 TCR checking target-arm: Add WFx syndrome function Peter Crosthwaite (14): target-arm: cpu64: generalise name of A57 regs target-arm: cpu64: Add support for Cortex-A53 arm: Introduce Xilinx ZynqMP SoC arm: xlnx-zynqmp: Add GIC arm: xlnx-zynqmp: Connect CPU Timers to GIC net: cadence_gem: Clean up variable names net: cadence_gem: Split state struct and type into header arm: xlnx-zynqmp: Add GEM support char: cadence_uart: Clean up variable names char: cadence_uart: Split state struct and type into header arm: xlnx-zynqmp: Add UART support arm: Add xlnx-ep108 machine arm: xlnx-ep108: Add external RAM arm: xlnx-ep108: Add bootloading Timothy Baldwin (1): linux-user/arm: Correct TARGET_NR_timerfd to TARGET_NR_timerfd_create default-configs/aarch64-softmmu.mak | 2 +- hw/arm/Makefile.objs | 1 + hw/arm/xlnx-ep108.c | 82 ++++++++++++++ hw/arm/xlnx-zynqmp.c | 211 ++++++++++++++++++++++++++++++++++++ hw/char/cadence_uart.c | 115 ++++++++------------ hw/net/cadence_gem.c | 95 +++++----------- include/hw/arm/xlnx-zynqmp.h | 58 ++++++++++ include/hw/char/cadence_uart.h | 53 +++++++++ include/hw/net/cadence_gem.h | 73 +++++++++++++ linux-user/arm/syscall_nr.h | 2 +- target-arm/cpu64.c | 61 ++++++++++- target-arm/helper.c | 75 +++++++++---- target-arm/internals.h | 6 + 13 files changed, 671 insertions(+), 163 deletions(-) create mode 100644 hw/arm/xlnx-ep108.c create mode 100644 hw/arm/xlnx-zynqmp.c create mode 100644 include/hw/arm/xlnx-zynqmp.h create mode 100644 include/hw/char/cadence_uart.h create mode 100644 include/hw/net/cadence_gem.h