From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932146AbbESICm (ORCPT ); Tue, 19 May 2015 04:02:42 -0400 Received: from mail-bl2on0135.outbound.protection.outlook.com ([65.55.169.135]:15797 "EHLO na01-bl2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753323AbbESIC3 (ORCPT ); Tue, 19 May 2015 04:02:29 -0400 Authentication-Results: spf=none (sender IP is 165.204.84.222) smtp.mailfrom=amd.com; intel.com; dkim=none (message not signed) header.d=none; X-WSS-ID: 0NOL7NU-08-J5V-02 X-M-MSG: From: Huang Rui To: Borislav Petkov , Len Brown , "Rafael J. Wysocki" , Thomas Gleixner CC: , , Fengguang Wu , Aaron Lu , Tony Li , Huang Rui Subject: [RFC PATCH 1/4] x86, mwaitt: add monitorx and mwaitx instruction Date: Tue, 19 May 2015 16:01:09 +0800 Message-ID: <1432022472-2224-2-git-send-email-ray.huang@amd.com> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1432022472-2224-1-git-send-email-ray.huang@amd.com> References: <1432022472-2224-1-git-send-email-ray.huang@amd.com> MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-Microsoft-Exchange-Diagnostics: 1;BN1BFFO11FD012;1:nIX1ta6zTzc+XLeory7f96IXi3iBzp9WXCL277/Z/ZIJXMpP/zLovuQlHt//cW/ifWFFFKmjPEVKi0eFn8V85Ppx2ztpFD//WQfJta7s7z7yA2rT1ZKUzTURupKUC3y2V607xKfyxTSRJNHizjpwxuZ/Y7iHf+PdZEkI4+2i0QovcKXjt8HG4dHJQYra01xVK1UJkYyWHTyOmIoVIG6NORMWlDy2HWnUKD9p1r3oc/nrV+yc/bvkGtLD8pxx1hVkaa6jF994j7cx+Btq9LN6xlGhW8tyaNf0mlY6x2nvEllRCuW2miurmfUZj97jl5D4FN5ViEXRGY1Xii8Rr+/cLQ== X-Forefront-Antispam-Report: CIP:165.204.84.222;CTRY:US;IPV:NLI;EFV:NLI;SFV:NSPM;SFS:(10019020)(6009001)(428002)(189002)(199003)(53416004)(106466001)(5001770100001)(5001860100001)(36756003)(68736005)(77096005)(105586002)(47776003)(64706001)(189998001)(229853001)(97736004)(62966003)(2950100001)(77156002)(33646002)(5001830100001)(4001540100001)(19580395003)(19580405001)(92566002)(101416001)(50986999)(76176999)(50226001)(86362001)(575784001)(46102003)(87936001)(50466002)(48376002)(217873001);DIR:OUT;SFP:1102;SCL:1;SRVR:BY1PR02MB1114;H:atltwp02.amd.com;FPR:;SPF:None;PTR:InfoDomainNonexistent;MX:1;A:1;LANG:en; X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BY1PR02MB1114;UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BY1PR02MB1276; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:(601004)(5005006)(3002001);SRVR:BY1PR02MB1114;BCL:0;PCL:0;RULEID:;SRVR:BY1PR02MB1114; X-Forefront-PRVS: 0581B5AB35 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 May 2015 08:02:23.9757 (UTC) X-MS-Exchange-CrossTenant-Id: fde4dada-be84-483f-92cc-e026cbee8e96 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=fde4dada-be84-483f-92cc-e026cbee8e96;Ip=[165.204.84.222];Helo=[atltwp02.amd.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY1PR02MB1114 X-OriginatorOrg: amd.com Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On AMD Carrizo processors (Family 15h, Model 60h-6fh), there is a new feature called MWAITT (Mwait with a timer) as an extension of Monitor/Mwait. MWAITT, another name is MWAITX (MWAIT with extensions), has a configurable timer that causes MWAITX to exit on expiration. Compared with MONITOR/MWAIT, there are minor differences in opcode and input parameters. MWAITX ECX[1]: enable timer if set MWAITX EBX[31:0]: max wait time expressed in SW P0 clocks The software P0 frequency is the same as the TSC frequency. Max timeout = EBX/(TSC frequency) Signed-off-by: Huang Rui --- arch/x86/include/asm/cpufeature.h | 1 + arch/x86/include/asm/mwait.h | 25 +++++++++++++++++++++++++ 2 files changed, 26 insertions(+) diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h index 3d6606f..3ef1f6e 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -176,6 +176,7 @@ #define X86_FEATURE_PERFCTR_NB ( 6*32+24) /* NB performance counter extensions */ #define X86_FEATURE_BPEXT (6*32+26) /* data breakpoint extension */ #define X86_FEATURE_PERFCTR_L2 ( 6*32+28) /* L2 performance counter extensions */ +#define X86_FEATURE_MWAITT ( 6*32+29) /* Mwait extension (MonitorX/MwaitX) */ /* * Auxiliary flags: Linux defined - For features scattered in various diff --git a/arch/x86/include/asm/mwait.h b/arch/x86/include/asm/mwait.h index 653dfa7..b91136f 100644 --- a/arch/x86/include/asm/mwait.h +++ b/arch/x86/include/asm/mwait.h @@ -23,6 +23,14 @@ static inline void __monitor(const void *eax, unsigned long ecx, :: "a" (eax), "c" (ecx), "d"(edx)); } +static inline void __monitorx(const void *eax, unsigned long ecx, + unsigned long edx) +{ + /* "monitorx %eax, %ecx, %edx;" */ + asm volatile(".byte 0x0f, 0x01, 0xfa;" + :: "a" (eax), "c" (ecx), "d"(edx)); +} + static inline void __mwait(unsigned long eax, unsigned long ecx) { /* "mwait %eax, %ecx;" */ @@ -30,6 +38,14 @@ static inline void __mwait(unsigned long eax, unsigned long ecx) :: "a" (eax), "c" (ecx)); } +static inline void __mwaitx(unsigned long eax, unsigned long ebx, + unsigned long ecx) +{ + /* "mwaitx %eax, %ebx, %ecx;" */ + asm volatile(".byte 0x0f, 0x01, 0xfb;" + :: "a" (eax), "b" (ebx), "c" (ecx)); +} + static inline void __sti_mwait(unsigned long eax, unsigned long ecx) { trace_hardirqs_on(); @@ -38,6 +54,15 @@ static inline void __sti_mwait(unsigned long eax, unsigned long ecx) :: "a" (eax), "c" (ecx)); } +static inline void __sti_mwaitx(unsigned long eax, unsigned long ebx, + unsigned long ecx) +{ + trace_hardirqs_on(); + /* "mwaitx %eax, %ebx, %ecx;" */ + asm volatile("sti; .byte 0x0f, 0x01, 0xfb;" + :: "a" (eax), "b" (ebx), "c" (ecx)); +} + /* * This uses new MONITOR/MWAIT instructions on P4 processors with PNI, * which can obviate IPI to trigger checking of need_resched. -- 2.1.0